JPH1187223A - Electron beam exposure apparatus and electron beam exposure method - Google Patents

Abstract

(57) [Summary] Electron beam exposure capable of securing a wiring width within a predetermined allowable range even when a writing pattern is misaligned when drawing by irradiating an object with an electron beam. An apparatus and an electron beam exposure method are provided. An object (44) is irradiated with an electron beam.
In the electron beam exposure apparatus 1 that draws a pattern on
With respect to a boundary drawing pattern 51a that straddles a boundary 51f between ranges that can be drawn at one time, a predetermined blank area 51b including the boundary 51f is provided in the control computer 10 so that the drawing basic data is separated from the drawing patterns 52 by a predetermined amount. A removal operation processing unit 12a that processes the 12e to generate the removed drawing data 12f; an additional operation processing unit 12b that adds the additional drawing data 12g of the auxiliary pattern 51e for supplementing the blank area 51b to the removed drawing data 12f; Is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron beam lithography technique for irradiating an electron beam photosensitive resist coated on a semiconductor substrate (wafer) with an electron beam and drawing a circuit pattern on the electron beam photosensitive resist material. The present invention relates to an improvement of an electron beam exposure apparatus and an electron beam exposure method using the method.

[0002]

2. Description of the Related Art In the following description, the terms circuit pattern, drawing pattern, and wiring pattern are used. The term "circuit pattern" refers to the wiring of a semiconductor integrated circuit by an electron beam exposure apparatus in the process of manufacturing the semiconductor integrated circuit. A pattern of the entire integrated circuit that draws an arrangement pattern on an electron beam photosensitive resist (hereinafter referred to as a resist).
The drawing pattern is an arrangement pattern for one-time drawing of the circuit pattern in a plurality of times, and the wiring pattern is an arrangement pattern of one wiring or the like in the drawing pattern.

In a semiconductor manufacturing process, in order to form a circuit pattern of an integrated circuit on a wafer on which a semiconductor chip is manufactured, a step of applying a photosensitive agent to the wafer, a step of exposing the wafer, a step of exposing the wafer, The integrated circuit is formed on the wafer through a developing process, an etching process for etching the wafer, and a thin film forming process for forming a thin film on the wafer. Exposure techniques used in the process of exposing a wafer include a photolithography technique and an electron beam lithography technique. The photolithography technique is a technique in which a photosensitive material called a photoresist is applied to the surface of a wafer, and a thin film on which a circuit pattern of an integrated circuit called a mask is printed is exposed to the photoresist on the wafer.

The electron beam lithography technology (electron beam drawing technology) is a technology for exposing a predetermined semiconductor integrated circuit pattern by directly irradiating an electron beam emitted from an electron gun onto a resist applied on a wafer. is there. Electron beam lithography can transfer finer patterns than photolithography.

Since the circuit pattern of a semiconductor integrated circuit exposed by using the electron beam lithography technique is fine, when exposing a circuit pattern for one integrated circuit to an object, the exposure is divided into a plurality of times. Do. Conventionally, in the vicinity of a field-to-field boundary, which is a range of a drawing pattern in which a circuit pattern can be drawn at a time by an electron beam exposure apparatus, a position shift of the drawn drawing pattern occurs.
The width of the wiring pattern becomes narrower (hereinafter referred to as pattern line thinning) or becomes thicker (hereinafter referred to as pattern line thickening)
There was a case.

As a method for solving this problem, there is a multiple exposure method. The multiple exposure method is a method of exposing a drawing pattern at the boundary between fields with high accuracy by exposing the drawing pattern a plurality of times at a boundary portion of the field with an exposure amount smaller than usual. Is a way to improve

However, when such an exposure method is employed, the drawing pattern must be drawn a plurality of times at one portion where the connection between the drawing patterns occurs, so that the entire circuit pattern is exposed. To do so, the number of exposure times becomes a considerable number. Therefore, the throughput of the semiconductor manufacturing apparatus is significantly reduced. In order to solve such a problem, it is required to reduce the number of exposures near the boundary between fields and to improve the pattern connection accuracy even with a small number of exposures.

As a method for satisfying such a demand, there is a method as disclosed in JP-A-8-330216. This corresponds to a position where the position of the drawing patterns needs to be adjusted, such as a field boundary 51f which is a boundary between the field A and the field B as shown in FIG.
In this method, an auxiliary pattern 151e for adjusting the positions of the drawing patterns is added as shown in FIG. Thereby, pattern line thinning, disconnection, and the like can be prevented. In this method, the number of exposures can be increased by one exposure of the auxiliary pattern as compared with the multiple exposure method, which is an effective method in that the throughput is improved in the semiconductor manufacturing process.

However, this method also has the following disadvantages. When the field A and the field B are overlapped and drawn as shown in FIG. 15A, a pattern line thickening due to the double exposure of the overlapped portion occurs. When the exposure is additionally performed, the pattern line becomes thicker. As a result, adjacent wiring patterns 51 are short-circuited as shown in FIG.

[0010] As a method of preventing such a drawback,
There is a method such as Japanese Patent Publication No. 8-15138. This is a method of preventing a short circuit between adjacent wiring patterns due to a pattern line thickening by drawing a seam 51g of the wiring patterns 51 where the drawing patterns are adjacent to each other as being shifted for each wiring pattern 51 as shown in FIG. It is.

[0011]

However, in this method, it is necessary to shift the joint of the wiring patterns for each wiring pattern, and to extend the wiring pattern to a further shifted position before drawing. Further, this method does not prevent the pattern line from becoming thicker or thinner in the wiring pattern, and thus cannot be said to be an effective method for making the pattern line thicker or the pattern line thinner. Therefore, the present invention solves the above-mentioned problems, and an electron beam exposure method capable of securing a wiring width within a predetermined allowable range even when a drawing pattern is misaligned when irradiating an object with an electron beam and drawing. It is an object to provide an apparatus and an electron beam exposure method.

[0012]

According to the present invention, there is provided an electron beam exposure apparatus for drawing a pattern on an object by irradiating the object with an electron beam. A drawing device body, a drawing device control unit for controlling the drawing device body, and a control computer that generates drawing data based on the drawing pattern,
The control computer provides a predetermined blank area including the boundary with respect to the boundary drawing pattern that straddles the boundary between the ranges that can be drawn at once, and processes the drawing basic data so that the drawing patterns are separated by a predetermined amount, and removes and draws. This is achieved by an electron beam exposure apparatus comprising: a removal operation processing unit that generates data; and an additional operation processing unit that adds additional drawing data of an auxiliary pattern for supplementing a blank area to the removed drawing data. . In addition, the object of the present invention is to provide a method for drawing a pattern on an object by irradiating an electron beam with an electron beam exposure method. By providing a predetermined blank area including a boundary, processing the drawing basic data so that the drawing patterns are separated by a predetermined amount, generating removal drawing data and drawing, and generating an auxiliary pattern for supplementing the blank area. This is achieved by an electron beam exposure method characterized by drawing.

In the present invention, a predetermined blank area is provided at the boundary between the drawing patterns by the removal operation processing unit, and the drawing is performed.
Further, by adding an auxiliary pattern to this blank area and drawing, even if the position of the drawn pattern is shifted in the separating direction and the overlapping direction due to an error of the electron beam exposure, a wiring having a wiring width within an allowable range can be obtained. Can be molded. For this reason, for example, it can be expected to improve the yield in the manufacturing process of semiconductors and the like.

[0014]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Although the embodiments described below are preferred specific examples of the present invention, various technically preferable limitations are given. However, the scope of the present invention is not limited to the following description. It is not limited to these forms unless otherwise stated.

In the following description, terms such as a circuit pattern, a drawing pattern, and a wiring pattern are used, and their meanings are the same as the terms used in the prior art.
FIG. 1 is a functional block diagram showing a preferred embodiment of the electron beam exposure apparatus of the present invention. Electron beam exposure equipment 1
1 includes a control computer 10 (control computer), a drawing apparatus control unit 20, a drawing apparatus main body 30, and the like as shown in FIG.

The control computer 10 operates as shown in FIG.
It comprises a PU 11, a memory 12, a hard disk 13, a keyboard 14, a display 15, a controller 16, an external device interface 17, a bus BS, and the like. The CPU 11 is, for example, a central processing unit (CP
U: Central Processing Uni
t). The CPU 11 not only controls the entire control computer 10, but also operates the drawing apparatus main body 30 by giving a control command to the drawing apparatus control unit 20. The CPU 11 performs processing while accessing data and programs read into the memory 12.

The memory 12 is a work area when the CPU 11 performs arithmetic processing, and is also a storage area for data and the like. As shown in FIG. 2, the memory 12 includes drawing data 12c, a removal calculation processing unit 12a, an addition calculation processing unit 12b, and an exposure control unit 12.
d and the like exist. Although the drawing data 12c, the removal operation processing unit 12a, the additional operation processing unit 12b, and the exposure control unit 12d are expressed as existing in the memory 12, the program for processing them is actually, for example, a hard disk 13 Is read into the memory 12 by the CPU 11 so that the CPU 11 performs processing such as a program while accessing the memory 12.

The drawing data 12c is stored in the hard disk 13
Drawing data 1 as drawing data read from
2e, removed drawing data 12f obtained by removing drawing data of a predetermined area from the drawing basic data 12e, and the auxiliary pattern 51.
The additional drawing data 12g, which is the drawing data of e.
These data do not always exist, but are read from the hard disk 13 or the like as necessary,
The data is processed at 11 and exists on the memory 12.

The exposure control section 12d is software for controlling the drawing apparatus main body 30. Exposure controller 12d
Operates the drawing apparatus main body 30 by giving a predetermined control command to the drawing apparatus control unit 20.

The hard disk 13 is an information storage medium for recording and holding information, and is, for example, a hard disk. The hard disk 13 stores, for example, basic drawing data 12e which is subjected to predetermined processing on CAD data 17a, which is a circuit pattern of a designed integrated circuit, and is digitized for drawing by an electron beam exposure apparatus. The keyboard 14 is input means (for example, a keyboard) for inputting data to the control computer 10.

The display 15 is connected to the control computer 1
0, for example, a plasma display or a liquid crystal display. The controller 16 controls devices such as the hard disk 13, keyboard 14, display 15, and external device interface 17. Since the external device interface 17 is a connector (connection unit) for exchanging the control computer 10 with an external device, various devices (for example, the drawing device control unit 20, the FD, and the CD-ROM) are used. It is a connection part connected to. The external device interface 17 is a CA
It is also connected to a device for loading the D data 17a into the control computer 10.

The bus BS is a kind of signal line through which commands and data pass. The bus BS is, for example, a CPU 11,
The memory 12, the hard disk 13, the keyboard 14, the display 15, the controller 16, and the external device interface 17 are electrically connected.

As shown in FIG. 1, the drawing apparatus controller 20 includes a data controller 21, a first deflection controller 22, a second deflection controller 23, a third deflection controller 24, and an electron optical system controller 2.
7 and a stage control unit 25. The data control unit 21 receives a control command from the control computer 10 and controls the entire drawing device control unit 20. The first deflection control unit 22, the second deflection control unit 23, and the third deflection control unit 24 include a first deflection unit 37, a second deflection unit 38, and a third This is a control unit for controlling each of the deflection units 39.

The electronics control section 27 is provided with the drawing apparatus main body 3.
0, for example, the first lens 3
1, the second lens 32, the third lens 33, the fourth lens 34, and the like are controlled. The stage controller 25 controls the object 4
It is a control unit for adjusting the position of the electron beam 4 in two directions orthogonal to each other in order to irradiate the electron beam to a predetermined place.

As shown in FIG. 1, the drawing apparatus main body 30 includes an electron gun 41, a slit 40, a first aperture 35, a second aperture 36, an XY stage 42, a stage drive system 43, a first deflection section 37, and a second deflection section. 38, the third deflecting unit 39, the first
It comprises a lens 31, a second lens 32, a third lens 33, a fourth lens 34 and the like.

The electron gun 41 is an electron gun that emits an electron beam. The slit 40 shapes the shape of the electron beam irradiated by the electron gun 41. The first aperture 35 and the second aperture 36 are forming apertures for forming an electron beam,
The forming aperture has an opening in the shape of the auxiliary pattern 51e. The shape of the opening is, for example, a rectangle as shown in FIG. 9 or a substantially cross shape as shown in FIG. The electron beam is an electron gun 41
And is shaped according to the shape of the opening.
The width of the auxiliary pattern 51e in the wiring width direction (W2 in FIG. 9)
12 and W5) in FIG. 12, the wiring width when the wiring pattern is exposed has an error of ± 10% with respect to the original wiring width at the time of design.
A predetermined width is set so as to be 10%.

The XY stage 42 is a stage on which an object 44 is placed, and is moved together with the object 44 in two directions orthogonal to each other on a plane by a stage driving system 43. The stage drive system 43 is an actuator for moving the XY stage 42. Stage drive system 43
Are controlled by the stage control 25 of the drawing apparatus control unit 20. The stage drive system 43 includes the XY stage 42
The amount of movement of the stage is controlled by the laser
5 is read by the CPU 11 and compared with the position of the drawing pattern, and the correction amount is determined by the deflection system (the first deflection unit 37, the second deflection unit 37).
Feedback is made to the deflecting unit 38 and the third deflecting unit 39) to connect the drawing areas with high accuracy.

The first deflecting unit 37, the second deflecting unit 38, and the third deflecting unit 39 deflect the electron beam emitted by the electron gun 41 in a predetermined direction. Has, for example, three deflection units as shown in FIG.

The first lens 31, the second lens 32, the third lens 33, and the fourth lens 34 are lenses of an optical system for reducing, for example, the electron beam emitted by the electron gun 41. The first lens 31, the second lens 32, the third lens 33, and the fourth lens 34 are
7 is controlled. These lenses are, for example, 4
One is provided.

The operation of the drawing apparatus main body 30 is performed by two apertures arranged vertically as shown in FIG.
5. Using the second aperture 36, the three deflecting portions, that is, the first deflecting portion 37, the second deflecting portion 38, and the third deflecting portion 39, which are square forming electrodes, are arranged so as to sandwich the respective apertures. The drawing apparatus main body 30 deflects an electron beam (electron beam) emitted from an electron gun 41 to an object 44 which is a substrate 44b (wafer) on which a resist 44a is applied, by each deflecting unit, and forms an image and each aperture. By changing the overlap, the auxiliary pattern 51e having a required size, for example, a rectangular auxiliary pattern 51e or a substantially cross-shaped auxiliary pattern 51e is formed. In the following description, a rectangular auxiliary pattern is used unless otherwise specified. The obtained rectangular beam is reduced, and is further projected to a desired position by a deflection electrode at the lower stage to expose a required pattern.

The deflection area of the electron beam is usually as small as about several mm square, and XY to expose the entire surface of the resist 44a.
It is necessary to move the stage 42. The moving amount of the XY stage 42 is read into the signal processor 26 by the laser interference system 43, is compared with the position of the circuit pattern of the combined drawing data 12h, and the correction amount is fed back to the deflecting unit to accurately connect the drawing regions. . According to this method, a pattern can be drawn on an integrated circuit having a large exposure area.

The configuration of the preferred embodiment of the electron beam exposure apparatus of the present invention has been described above. Next, the operation will be described with reference to FIGS.
FIG. 3 is a flowchart showing the processing of the preferred embodiment of the electron beam exposure apparatus of the present invention. FIG. 4 is a plan view showing an object irradiated with an electron beam by the electron beam exposure apparatus. FIG. 5 is a diagram showing a procedure for drawing a wiring pattern by the electron beam exposure apparatus. C in FIG.
The AD data 17a corresponds to the circuit pattern 5 of the integrated circuit 44c.
4 is the wiring data. The CAD data 17a is
(Computer Aided Design) device, and basic drawing data 12e of the circuit pattern 52
Is taken into the control computer 10 of the electron beam exposure apparatus 1. Specifically, the CAD data 17a is converted into a predetermined format by the electron beam exposure apparatus 1 after data editing such as pattern reduction, enlargement, division, and the like, and is stored on the hard disk 13, for example, as drawing basic data 12c.

Step ST1 Crossover wiring pattern extraction processing
The processing wafer 44 has integrated circuits 44c arranged vertically and horizontally as shown in FIG. One of the integrated circuits 44
For c, the drawing pattern is drawn 36 times, for example, divided into six columns and six columns, and the circuit pattern 54 is formed. FIG. 5A shows the fields A and B in FIG.
FIG. The removal operation processing unit 12a extracts all the wiring patterns 51 straddling the field A and the field B on the field boundary 51f as shown in FIG. 5A in the drawing basic data 12e of FIG.

Step ST2 Boundary drawing pattern removal processing
In addition, the removal operation processing unit 12a determines the boundary portion of the wiring pattern 51 extracted in step ST1 as shown in FIG.
FIG. 5B shows the boundary drawing pattern 51a shown in FIG.
(A wiring pattern of the boundary area 51g is removed from the basic drawing data 12c). The blank area 51b has a drawing pattern of the field boundary 51f.
This process is performed on the entire boundary region 51g including the boundary where the field A and the field B are adjacent to each other so as to be separated by α / 2 from the basic drawing data 12 to generate the removed drawing data 12f.

Step ST3 Exposure processing The exposure control section 12d issues an instruction to expose the electron beam to the drawing apparatus control section 20 based on the removal drawing data 12f generated in step ST2, and
4a to draw a drawing pattern.

Step ST4 Auxiliary pattern generation processing The additional calculation processing section 12b converts the auxiliary pattern 51e connecting the wiring pattern 51c and the wiring pattern 51d into the removal drawing data 12f generated in step ST2 as shown in FIG. The additional drawing data 12g is generated so as to be arranged in all the blank areas 51b on the boundary 51f between the field A and the field B so as to be arranged in the blank area 51b. Here, the auxiliary pattern 51e must be added to only one of the field A and the field B. This is because if the pattern is added to both drawing pattern fields, the auxiliary pattern 51e will be formed twice. These processes are performed on all the circuit patterns 54.

Step ST5 Exposure Processing The exposure control section 12d determines whether or not the wafer 44 (resist 44) based on the additional drawing data 12g created in step 4.
The drawing apparatus control unit 2 issues a command for exposing an electron beam to a).
0, and the auxiliary pattern 51e is added to the resist 44a.
Is drawn. The method of exposing the electron beam (electron beam) is as described above.

The processing of the preferred embodiment of the electron beam exposure apparatus according to the present invention has been described above. Next, in order to confirm the effect of the embodiment, a predetermined circuit pattern is drawn by the electron beam exposure apparatus. A wiring width of the wiring pattern is measured, and a simulation for measuring a wiring width error is performed.

The electron beam exposure apparatus used in the following simulation has an acceleration voltage of 50 KeV, and EID conditions (exposure conditions) for irradiating an electron beam are as follows. Forward scattering radius: 0.070 μm Back scattering radius: 9.5 μm Back scattering coefficient: 0.8

First Simulation In the first simulation, reference data for examining and comparing with the effect of the preferred embodiment of the electron beam exposure apparatus of the present invention is obtained. In the first simulation, a circuit pattern is drawn by an electron beam exposure apparatus without adding an auxiliary pattern 51e.

The circuit pattern 54 to be evaluated is shown in FIG.
This is a drawing pattern 52 as shown in FIG. The drawing pattern 52 is formed in a substantially square area of 20 μm on each side as shown in FIG.
(B) L / S patterns having a wiring width W1 = 0.20 μm are arranged at a ratio of 1: 1. Here, the L / S pattern (Lin
The term “e and Space” refers to both a wiring pattern and a blank pattern between the wiring patterns.

FIG. 6B is an enlarged view of a portion 52a of the drawing pattern 52 of FIG. 6A. Drawing pattern 52a
Is a drawing pattern of a portion bounded by a field boundary 51f which is a boundary between the field A and the field B, for example.

In the first simulation, the drawing pattern 51 straddles the field boundary 51f,
The wiring pattern 51c and the wiring pattern 51d are separated or overlapped by a distance β [μm] about the field boundary 51f as shown in FIG.
Is varied), and the line width error γ [%] of the wiring width, which is the width of the wiring pattern 51 near the field boundary 51 f when the wiring pattern 51 is formed on the resist 44 a, is simulated.

When the distance β is positive, the wiring pattern 51c and the wiring pattern 51d overlap by the distance β, and when the distance β is negative, the wiring pattern 51c and the wiring pattern 51d are separated by the distance β. Shall be The line width error γ is calculated by the following equation (1). Line width error γ [%] = ((wiring width after drawing−wiring width at design) / wiring width at design) × 100 (1) The above definition is the same in the following simulation. .

FIG. 7 shows the overlap amount (pattern overlap amount) β [μm] between the wiring pattern 51c and the wiring pattern 51d in the first simulation on the horizontal axis, and the line width error γ [%] of the wiring pattern 51 in the vertical direction. The axis indicates how much error occurs in the wiring width due to the amount of overlap β between the wiring patterns 51. The reference in this graph is when the pattern overlap amount β = 0 and the point where the line width error γ = 0. In FIG. 7, a line width error γ simulation was performed while shifting the pattern overlap amount β by 0.01 μm.

Referring to FIG. 7, it can be seen that a line width error is remarkably observed due to a change in the pattern overlap amount β. The pattern position shift amount β in which the line width error γ on the field boundary 51f satisfies ± 10% is 0.017 μm in the away direction,
The overlapping direction is 0.022 μm. The margin which is the sum of the pattern displacement amount β satisfying the line width error γ of ± 10% on the field boundary 51f in the separating direction and the overlapping direction is 0.039 μm.

With reference to the data obtained by the first simulation, the following simulation is performed when drawing is performed using the preferred embodiment of the electron beam exposure apparatus of the present invention. Second Simulation Next, using the preferred embodiment of the electron beam exposure apparatus of the present invention, a simulation substantially similar to the first simulation is performed. The electron beam exposure conditions of the electron beam exposure apparatus 1 are substantially the same as in the first simulation.

FIG. 8A shows a drawing pattern 52 for performing the second simulation. In the second simulation, the wiring pattern 51c and the wiring pattern 51 straddling the field boundary 51f as in the first simulation.
The position of the auxiliary pattern 51e is fixed in the arrangement relationship with the pattern d, and the pattern overlap amount β = −0.05 to β = + 0.05 between the wiring pattern 51c and the wiring pattern 51d.
The simulation is performed by changing the distance β by 0.01 μm at a time so that the wiring pattern 51c and the wiring pattern 51d are equidistant from the field boundary 51f so as to be equal to μm (the blank area 51b is provided). Note that the auxiliary pattern 51e in FIG.
And the shape of the auxiliary pattern 51e is, for example, a vertical width W2 = 0.1 as shown in FIG.
It is a rectangle having a width of 4 μm and a width W3 = 0.12 μm.

FIG. 10 shows the result of the second simulation. In FIG. 10, the first simulation result is also shown so that the effect of the second simulation can be easily understood. In the following description, the first simulation result not including the effect of the present invention is referred to as “before correction”, and the simulation result including the effect according to the preferred embodiment of the electron beam exposure apparatus of the present invention is referred to as “after correction”. . Referring to FIG. 10, the pattern position shift amount β satisfying ± 10% of the line width error γ on the field boundary is 0.017 μm in the separation direction before correction, 0.022 μm in the overlap direction, and 0.039 μm in total. On the other hand, after the correction, the separation direction is 0.037 μm, the overlapping direction is 0.021 μm, and the total is 0.058 μm. The margin is increased by 0.019 μm as compared with the value before the correction. We were able to.

Third Simulation Next, using the preferred embodiment of the electron beam exposure apparatus of the present invention, a simulation substantially similar to the second simulation is performed. The electron beam exposure conditions of the electron beam exposure apparatus 1 are the same as in the second simulation. Third
In the simulation, in the second simulation, the auxiliary pattern 51e has a cross shape as shown in FIG. 11B. The auxiliary pattern 51e in FIG. 12 has the same orientation as the auxiliary pattern 51e in FIG. The shape of the auxiliary pattern 51e is as shown in FIG. 12, for example, the first horizontal width W6 = 0.08 μm, the second horizontal width W7 = 0.20 μm, the first vertical width W4 = 0.10 μm,
The second vertical width W5 is 0.12 μm. Correction pattern 5
Conditions other than the shape of 1e are substantially the same as those in the second simulation.

FIG. 13 shows the result of the third simulation. FIG. 13 also shows the first simulation result so that the effect of the third simulation can be easily understood. Referring to FIG. 13, field boundary 5
The pattern position shift amount β in which the line width error γ on 1f satisfies ± 10% is 0.039 μm before correction, whereas after correction 0.030 μm in the away direction and 0.1 μm in the overlap direction. 029 μm and 0.059 μm in total, so that the margin can be increased by 0.020 μm as compared with the case of the first simulation to which the present invention is not applied, and the field boundary 5 of the second simulation is
Since the pattern position shift amount β that satisfies the line width error γ on 1f of ± 10% is 0.058 μm, it is possible to obtain more effects than the second simulation.

According to the embodiment of the present invention, even if the drawing pattern is misaligned due to the exposure error of the electron beam exposure apparatus, the wiring width of the drawing pattern near the drawing pattern boundary can be kept within the allowable range. .

The present invention is not limited to the above embodiment. In the above description, the present invention is limited to a semiconductor manufacturing apparatus, but can be applied to any apparatus that irradiates an electron beam. Various shapes can be adopted as the shape of the auxiliary pattern (opening of the aperture). The number of apertures and deflection parts
It is not limited to the above.

[0054]

As described above, according to the present invention, a wiring width within a predetermined allowable range is ensured even when the drawing patterns are misaligned when drawing by irradiating an object with an electron beam. Therefore, the yield of products can be improved in, for example, a semiconductor manufacturing process.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram showing a preferred embodiment of an electron beam exposure apparatus of the present invention.

FIG. 2 is a configuration diagram showing data read into a memory of FIG. 1, an arithmetic processing unit, and the like.

FIG. 3 is a flowchart showing processing in the electron beam exposure apparatus of FIG.

FIG. 4 is a plan view showing an object irradiated with an electron beam by the electron beam exposure apparatus of FIG.

FIG. 5 is a plan view showing a procedure in which a wiring pattern is drawn by the electron beam exposure apparatus of FIG.

FIG. 6 is a plan view showing a state of a first simulation for comparison for confirming the effect of the electron beam exposure apparatus of FIG. 1;

FIG. 7 is a graph showing a result of a first simulation.

FIG. 8 is a plan view showing a state of drawing an electron beam in a second simulation.

FIG. 9 is a plan view showing dimensions of the auxiliary pattern of FIG. 8;

FIG. 10 is a graph showing the results of a second simulation.

FIG. 11 is a plan view showing how electron beams are drawn in a third simulation.

FIG. 12 is a plan view showing dimensions of the auxiliary pattern of FIG. 11;

FIG. 13 is a graph showing a result of a third simulation.

FIG. 14 is a plan view showing how writing is performed by a conventional electron beam exposure apparatus.

FIG. 15 is a plan view illustrating a state in which adjacent wiring patterns are in contact with each other when drawn by a conventional electron beam exposure apparatus.

FIG. 16 is a plan view showing a state drawn by the method disclosed in Japanese Patent Publication No. Hei 8-15138.

[Explanation of symbols]

1 ... Electron beam exposure apparatus (electron beam exposure apparatus), 10
... Control computer, 12 ... Drawing data, 12
a: Removal calculation processing unit, 12b: Additional calculation processing unit, 12e: Drawing basic data, 12f: Removal drawing data, 12g: Additional drawing data, 20: Drawing device control unit , 30: Drawing apparatus body, 44: Object (wafer, semiconductor wafer), A: Field,
B: field, 51: wiring pattern, 51b
... blank area, 51e ... auxiliary pattern, 51f
..Field boundaries, 52... Wiring patterns, 54.
..Circuit patterns

Claims (4)

[Claims] 1. An electron beam exposure apparatus for drawing a pattern on an object by irradiating an electron beam, comprising: a drawing apparatus main body for irradiating the object with an electron beam for drawing; and a drawing apparatus for controlling the drawing apparatus main body. A control unit for generating drawing data based on the drawing pattern, the control computer comprising: a predetermined calculation including a boundary with respect to a boundary drawing pattern extending over a boundary between ranges that can be drawn at a time. A removal operation processing unit for processing the basic drawing data so as to provide a blank area so that the drawing patterns are separated from each other by a predetermined amount to generate removed drawing data; and removing the additional drawing data of an auxiliary pattern to supplement the blank area. An electron beam exposure apparatus, comprising: an additional operation processing unit added to the apparatus. 2. The electron beam exposure apparatus according to claim 1, wherein the drawing apparatus main body has an aperture in which an opening having a shape of the auxiliary pattern is formed. 3. The object according to claim 1, wherein the object is a semiconductor wafer.
3. The electron beam exposure apparatus according to claim 1. 4. An electron beam exposure method for drawing a pattern on a target object by irradiating an electron beam, wherein a predetermined blank area including a boundary is provided for a boundary drawing pattern extending over a boundary between ranges that can be drawn at once. And processing the basic drawing data so that the drawing patterns are separated from each other by a predetermined amount to generate and draw the removed drawing data, and to generate and draw an auxiliary pattern for supplementing a blank area. Beam exposure method.