JPH118158A - Chip capacitor array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive an increase in the high-accuracy electrostatic capacities of a chip capacitor array with a good yield in a single production process, and to make it possible to correspond also to the freedom of a combination of the electrostatic capacitors of the array, by a method wherein the single elements of chip capacitors produced with good accuracy in all of electrical characteristics, dimension and form are arbitrarily fixed on a base substrate according to the need. SOLUTION: Four chip capacitors 2, which are previously made a selection of their electrical characteristics and their visual appearances, are arranged and fixed on an alumina substrate 1 formed to conform to the external diameter of a chip capacitor array as a base substrate in parallel to each other. These chip capacitors 2 may be constituted of the same electrostatic capacity only and ones constituted of different electrostatic capacitors may be used as the capacitors 2 according to the need. The chip capacitor array having an excellent performance of diverse combinations can be provided at low cost by a simple means for arranging and fixing the previously selected capacitors 2 on the base substrate with the bonding agent 4 to conform to a required performance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip capacitor array for forming a plurality of capacitors in one block.

[0002]

2. Description of the Related Art FIGS. 6 and 7 show an embodiment of the structure of a conventional chip capacitor array.

FIG. 6 shows a rectangular parallelepiped chip capacitor array fired body 10 in which external electrodes 11 for extracting individual internal electrodes are formed on both sides, and FIG. 7 shows comb-shaped irregularities formed on both sides. Chip capacitor array fired body 12
The external electrodes 13 for extracting the internal electrodes are formed on the convex portions of the above.

In the chip capacitor array having the conventional structure, a green laminate in which a predetermined number of ceramic green sheets on which internal electrodes are printed is cut into a plurality of capacitors in the same manner as in the method for manufacturing a single chip capacitor. Thereafter, a baking step is performed, and thereafter, the external electrodes 11 or 13 for leading out the internal electrodes are formed on the individual capacitance components. Next, the electrical characteristics were measured and sorted, and the appearance was sorted to obtain a finished chip capacitor array.

[0005]

In the conventional chip capacitor array, it is necessary to change the print pattern shape of the internal electrodes so that a plurality of capacitances are formed in a predetermined shape block in the laminating step. It is necessary to significantly change the method of forming the external electrodes 11 or 13 and the method of selecting characteristics from the single chip capacitor process in the manufacturing process of All of them have the same capacitance, and there is no flexibility in combining the capacitances. Further, if a failure occurs even in one place in the formed block, there is a problem that the entire block becomes defective.

The chip capacitor array of the present invention can achieve a high-yield, high-accuracy capacitance in a simple production process without significantly changing the conventional production process, and furthermore, a combination of capacitance values. It is an object of the present invention to provide a chip capacitor array that can respond to a degree of freedom.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for manufacturing a single chip capacitor, which has been produced with high accuracy in both electrical characteristics and dimensions and shape, by a conventional manufacturing method on a base substrate as required. And an excellent capacitor array having a high degree of freedom can be economically provided.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a chip capacitor array in which a plurality of chip capacitors are fixed on an upper surface of a base substrate. Since the required number is fixed on the base substrate as required, an excellent chip capacitor array having a high degree of freedom can be produced by a simple process.

According to a second aspect of the present invention, there is provided a chip capacitor array for fixing a plurality of chip capacitors having the same capacitance value on the upper surface of a base substrate, wherein the same capacitance is produced with high precision in advance. Since the required number of single chip capacitors are fixed on the base substrate as required, an excellent chip capacitor array with small variations in individual capacitances can be produced in a simple process.

According to a third aspect of the present invention, there is provided a chip capacitor array in which a plurality of chip capacitors having the same capacitance value are arranged substantially in parallel on the upper surface of a base substrate. As the required number of single chip capacitors with capacitance are arranged in parallel on the top surface of the base substrate as required, an excellent chip capacitor array with small variations in individual capacitance can be produced in a simple process. It is.

According to a fourth aspect of the present invention, a plurality of chip capacitors having the same capacitance value are substantially parallel to the upper surface of the base substrate, and at least one of the chip capacitors has another chip capacitor in a linear shape. Chip capacitor array to be arranged in a single capacitor with the same capacitance,
An excellent chip capacitor array in which various capacitor circuits can be formed can be produced by a simple process.

According to a fifth aspect of the present invention, there is provided the chip capacitor array according to the first aspect, wherein a plurality of chip capacitors having different capacitance values are arranged on the upper surface of the base substrate. In order to arrange the required number of single chip capacitors with different capacitances on the top surface of the base substrate as required, a simple process of chip capacitor arrays of various capacitances with various combinations of capacitance values with high flexibility It can be produced at

According to a sixth aspect of the present invention, there is provided a chip capacitor array in which a plurality of chip capacitors having different capacitance values are arranged substantially in parallel on an upper surface of a base substrate,
A chip capacitor array of various capacitances with a high degree of freedom in combination of capacitance values to arrange the required number of single chip capacitors of different capacitances produced in advance with high precision on the base substrate as required. Can be produced by a simple process.

According to a seventh aspect of the present invention, there is provided a chip capacitor array in which a base substrate is mounted inside external electrodes formed on both ends of a single chip capacitor. Regardless of the thickness variation of the formed external electrodes, an excellent chip capacitor array capable of correctly and electrically mounting and connecting the chip capacitor array to the circuit board can be produced by a simple manufacturing process.

The invention according to claim 8 of the present invention is a chip capacitor array in which an insulating plate is interposed between adjacent chip capacitors on a base substrate, whereby the chip capacitor array is mounted on a circuit board by soldering. ,
A short circuit between adjacent single chip capacitors due to a solder bridge or the like can be prevented, and the chip capacitor array can be reduced in size.

According to a ninth aspect of the present invention, a capacitance value is displayed on a lower surface of a base substrate of a chip capacitor array in which a plurality of chip capacitors are fixedly arranged on an upper surface of a base substrate, In particular, the entire or individual capacitance value is displayed on the lower surface of the base substrate opposite to the upper surface where the chip capacitor is fixed, so that it can be used without trouble when mounting the circuit board, and the lower surface of the base substrate is Since there is no external electrode or the like on a flat surface, display marking or the like can be easily performed.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (Embodiment 1) FIG. 1 shows a base substrate having a thickness of 0.3 m.
m, width and length of four chip capacitors 2 whose electric characteristics and appearance were previously selected were arranged and fixed substantially in parallel with an adhesive 4 on an alumina substrate 1 prepared according to the outer shape of the chip capacitor array to be constituted. This shows a capacitor array, and the chip capacitors 2 may be constituted only by the same capacitance value, or may be different in capacitance as required.

FIG. 2 shows that the chip capacitors 2 whose electrical characteristics and appearance have been selected in advance are bonded on an alumina substrate 5 having a thickness of 0.3 mm, a width and a length corresponding to the outer shape of the chip capacitor array to be constituted. Group of chip capacitors 6 in a straight line and electrically connected in series
Are arranged and fixed in substantially parallel to each other, and this chip capacitor 2 can be constituted by only the same capacitance value, or by using a capacitor having a different capacitance as necessary. Is also good. Further, the number of components of the chip capacitor group 6 may be increased or decreased as required.

FIG. 3 shows a side view of a side portion of a single chip capacitor 2 on which both external electrodes 3 are not formed, the thickness of which is 0.3 mm and the length is adjusted to the outer shape of the chip capacitor array to be formed. This shows a capacitor array in which four chip capacitors 2, whose electrical characteristics and appearance have been selected in advance, are arranged and fixed substantially in parallel with an adhesive on an alumina substrate 7 manufactured according to the width. The thickness variation of the chip capacitor array is absorbed irrespective of the thickness of the external electrode 3 formed on the end face, so that proper electrical connection can be made when mounted on the circuit board.

FIG. 4 shows a chip capacitor 2 having a thickness of 0.3 mm, a width and a length which are determined according to the outer shape of the chip capacitor array to be formed, on an alumina substrate 1 which has been subjected to electrical characteristics and appearance selection in advance. 4 shows a capacitor array that is arranged and fixed via an insulating plate 8 between adjacent chip capacitors 2 when they are arranged and fixed substantially in parallel with each other. This shows the external shape of the chip capacitor array. When soldering on a circuit board,
The purpose is to prevent the external electrodes 3 of adjacent chip capacitors 2 from being electrically short-circuited by a solder bridge or the like.

FIG. 5 shows the capacitance value of the chip capacitor 2 stamped and displayed 9 on the lower surface of the alumina substrate 1. In this example, since the chip capacitors 2 having the same capacitance were used, the batch display was performed.
It is necessary to perform the marking display 9 in accordance with the capacitance of the stamp.

In the above description, an example is described in which the base substrate is formed of the alumina substrate 1. However, the present invention can be similarly applied to other resin plates.

As shown in the above examples, the present invention is a simple means for arranging and fixing the chip capacitors 2 selected in advance on the base substrate with the adhesive 4 according to the required performance, and is excellent in various combinations. It is possible to provide an inexpensive chip capacitor array having high performance.

[0024]

As described above, according to the present invention, it is possible to provide an excellent chip capacitor array in which a chip capacitor array can be easily produced with a simple means with a high yield, and the degree of freedom in combination of capacitance values is high. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a chip capacitor array according to an embodiment of the present invention.

FIGS. 2A and 2B are a top view and a front view showing a chip capacitor array according to another embodiment of the present invention;

FIGS. 3A and 3B are a top view and a front view showing a chip capacitor array according to still another embodiment of the present invention.

FIGS. 4A and 4B are a top view and a front view showing a chip capacitor array according to still another embodiment of the present invention.

FIG. 5 is a perspective view showing a chip capacitor array according to still another embodiment of the present invention.

FIG. 6 is a perspective view showing a conventional chip capacitor array.

FIG. 7 is a perspective view showing another conventional chip capacitor array.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Alumina substrate 2 Chip capacitor 3 External electrode 4 Adhesive 5 Alumina substrate 6 Chip capacitor group 7 Alumina substrate 8 Insulating plate 9 Marking display

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Yuki Kamada 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yoshihiro Yamaguchi 1006 Kadoma Kadoma City, Osaka Pref.

Claims (9)

[Claims] 1. A chip capacitor array in which a plurality of chip capacitors are fixed on an upper surface of a base substrate. 2. The chip capacitor array according to claim 1, wherein a plurality of chip capacitors having the same capacitance value are fixed. 3. The chip capacitor array according to claim 1, wherein a plurality of chip capacitors having the same capacitance value are arranged substantially in parallel. 4. The device according to claim 1, wherein a plurality of chip capacitors having the same capacitance value are arranged substantially in parallel, and at least one of the chip capacitors has another chip capacitor arranged linearly. Chip capacitor array. 5. The chip capacitor array according to claim 1, wherein a plurality of chip capacitors having different capacitance values are fixed. 6. The chip capacitor array according to claim 5, wherein a plurality of chip capacitors having different capacitance values are arranged substantially in parallel. 7. The chip capacitor array according to claim 1, wherein a base substrate is mounted inside external electrodes formed at both ends of the chip capacitor. 8. The chip capacitor array according to claim 1, wherein an insulating plate is interposed between adjacent chip capacitors on the base substrate. 9. The chip capacitor array according to claim 1, wherein a capacitance value is displayed on a lower surface of the base substrate.