JPH1174772A - Power supply voltage switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent power supply short circuit state and to correctly switch power supply voltage by providing a transistor control circuit which outputs a control signal that turns on the other transistor after one of two transistor is turned off. SOLUTION: There is no VPP input after VCC is thrown in, that is, a ground potential input becomes an initial state of the VPP, and in such a case, in a voltage detection circuit, since an N-channel MOS transistor N1 and a P- channel MOS transistor P4 do not have a drive capability and an N-channel MOS transistor N2 has a drive capability, a signal B that is an output of the voltage detection circuit is on the GND level. Then, an output signal C of an inverter, i.e., the gate of a P-channel MOS transistor P2 becomes the VCC level. On the other hand, since the gate of a P-channel MOS transistor P1 becomes the GND level, the P2 is in an off state, the P1 is in the on state and VCC is outputted to voltage output OUT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile memory,
Or a microcomputer with a built-in nonvolatile memory,
The present invention relates to a power supply voltage switching circuit in an integrated circuit having a circuit for selectively using two types of power supply voltages depending on the operation.

[0002]

2. Description of the Related Art As an example of a circuit for selectively using two kinds of power supply voltages according to operations, there is a write / erase circuit of a nonvolatile memory or a device with a built-in nonvolatile memory. Some of these circuits operate on a fixed power supply (VCC) of a predetermined voltage at the time of data reading, and operate at the time of writing / erasing.
Although a circuit that operates at a voltage higher than C (VPP) is included, a high-voltage power supply is not necessary except for writing / erasing, so circuits and devices that generate a high voltage are usually stopped. It is. High voltage generation circuit and equipment are VC
If the operation is stopped while C is generated, the
The erasing circuit can continue to operate by receiving the supply of the VCC voltage at the time of reading.
In many cases, for example, a ground voltage other than the C voltage is output. In such a case, as shown in FIG. 3, one end of the source (or drain) of the P-channel MOS transistor P8 transmitting VPP and one end of the P-channel MOS transistor P9 transmitting VCC is short-circuited. A point is set as a voltage output point OUT, and each of the MOS transistors is set to VPENB, VC in FIG.
By moving the gate signal indicated by ENB,
A method of switching the voltage by turning off the power is used. At this time, in addition to the two types of power supplies VPP and VCC, it is necessary to generate signals corresponding to the gate signals VPENB and VCENB by another circuit.

As a circuit that eliminates the necessity of generating the gate signal, a circuit shown in FIG. 4 is disclosed in Japanese Patent Publication No. 7-48651. In this circuit, there is no need to generate a special gate signal, and the power supply voltage is not required. In particular, in a device in which VPP power is input from an external terminal, the power supply of the internal circuit can be switched simply by switching the terminal input voltage, which is convenient. In the figure, P5 and P6 are P-channel enhancement MOS transistors for switching the power supply voltage, and a high voltage VP is applied to the gate input of the P-channel MOS transistor P5.
P is supplied through a CMOS inverter including a P-channel enhancement MOS transistor P7 and an N-channel enhancement MOS transistor N4, and a high voltage VPP is directly supplied to a gate input of the P-channel MOS transistor P6. Thus, when the potential of VPP is the ground potential, the P-channel MOS transistor P5 is turned off, the P-channel MOS transistor P6 is turned on, and VCC is output to the output OUT, while VPP is at a predetermined high voltage. If
The P-channel MOS transistor P5 is turned on, the P-channel MOS transistor P6 is turned off, and VPP is output to the output OUT.

[0004]

As in the prior art, 2
When the power supply is switched by controlling the on / off of the transistors, VPP, VC
Care must be taken not to short-circuit both power supplies of C, but the above-mentioned Japanese Patent Publication No. 7-4865 which is useful as a power supply switching circuit.
In the power supply switching circuit disclosed in Japanese Patent Publication No.
There is a possibility that both the power supplies VPP and VCC are short-circuited. If different power supplies are short-circuited, not only may the circuit operation not be performed properly, but also adverse effects on the entire system including the circuit, such as latch-up, may be inconvenient.

FIG. 5 shows the operation of the power supply switching circuit disclosed in Japanese Patent Publication No. 7-48651. VCC is supplied, and VPP is set to the GND potential as an initial state.
This is a circuit for switching the power supply according to the voltage of P. In the initial state, the output (point A) of the CMOS inverter which is composed of an N-channel MOS transistor N4 and a P-channel MOS transistor P7 and is powered by VCC is VCC.
Level, and P-channel MOS transistor P5 transmitting VPP is off. On the other hand, the P-channel MOS transistor P6 for transmitting VCC is in the ON state, and VCC is output to the output OUT. At time t1, VPP reaches the inverted voltage VT of the inverter,
Since the output of the inverter is inverted and the output potential goes to the GND level, the P-channel MOS transistor P5 turns on. On the other hand, the gate voltage of P-channel MOS transistor P6 transmitting VCC is VPP, and at time t1, VPP <VCC, so that P-channel MOS transistor P6 is also in the ON state. As a result, power supply VCC and power supply VPP is short-circuited through P-channel MOS transistors P5 and P6. In this state, the VPP potential further rises and P-channel MOS transistor P6 is completely turned off (VPP = VCC-V
thp) until time t2. Time t3
In this case, VPP exceeds the voltage of VCC. At this time, since the power supply switching operation has been completed, the output voltage becomes the voltage of VPP thereafter. It is apparent that the same operation is performed when the VPP drops from the high voltage to the low voltage.

As described above, in the prior art circuit shown in FIG. 4, during the process of changing the voltage of VPP,
Although short, VPP and VCC may be short-circuited.

[0007] The present invention has been made to solve the above problems.

[0008]

In order to solve the above-mentioned problems, for example, when the power supply switching operation is performed by increasing the VPP voltage, the P-channel MOS shown in FIG.
The P-channel MOS transistor P5, ie, the transistor transmitting VPP, need not be turned on until the transistor P6, ie, the transistor transmitting VCC, is turned off. In other words, the gate signal of the transistor P5 only needs to maintain the VCC level until the gate signal VPP of the transistor P6 exceeds VCC. As the gate signal of the transistor P5, when the VPP voltage exceeds VCC, instead of the inverter composed of the N-channel MOS transistor N4 and the P-channel MOS transistor P7 in FIG.
What is necessary is just to use the output signal of the voltage detection circuit whose output is inverted from the VCC level to the GND level. When the power supply is switched after the VPP voltage drops from the high voltage, conversely, the transistor P6 is turned off until the transistor P5 is turned off.
May be prevented from being turned on, and the output signal of the voltage detection circuit may be inverted from the GND level to the VCC level until the VPP voltage becomes VCC.

That is, the power supply voltage switching circuit of the present invention comprises:
A first fixed power supply voltage and a second variable power supply voltage that fluctuates between a reference voltage and a second fixed power supply voltage exceeding the first fixed power supply voltage are converted to a voltage value of the second variable power supply voltage. Two transistors which are selectively turned on / off in response to one of the transistors, one end of which is connected to the first fixed power supply voltage and the second variable power supply voltage, respectively, and the other end of which is commonly connected to a power supply voltage output terminal. A power supply voltage switching circuit for selectively outputting via two transistors connected to the first and second variable power supply voltages based on the first fixed power supply voltage and the second variable power supply voltage. A transistor control circuit for outputting a control signal for turning on one of the two transistors and then turning on the other transistor when the second variable power supply voltage changes. It is characterized in that comprising providing a control circuit.

Further, the power supply voltage switching circuit of the present invention has a first
And a second variable power supply voltage that fluctuates between a reference voltage and a second fixed power supply voltage exceeding the first fixed power supply voltage according to the voltage value of the second variable power supply voltage. First and second P-channel transistors selectively on / off, one end of which is connected to the first
A power supply voltage switching circuit that is connected to a fixed power supply voltage and a second variable power supply voltage, and has the other end connected in common and selectively outputs via first and second P-channel transistors connected to a power supply voltage output terminal. And the second variable power supply voltage is connected to the gate of the first P-channel transistor, and the first P-channel transistor is connected to the gate of the second P-channel transistor. A transistor control circuit for outputting an ON signal within a voltage range of the second variable power supply voltage at which the transistor is turned off is provided.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a power supply voltage switching circuit according to an embodiment of the present invention. FIG. 2 is a timing chart showing an operation when power supply is switched using the circuit in FIG.

In the circuit of FIG. 1, power supply inputs of different voltages are indicated by VPP and VCC, and a voltage value exceeding VCC may be input to VPP. P1 is a P-channel enhancement MOS transistor that transmits VCC, and P2 is a P-channel enhancement MOS transistor that transmits VPP, both of which have a large driving capability because they supply a power supply current. P1 and P2 have their drains short-circuited, and the short-circuited contacts are the well potentials of P1 and P2 and the voltage output OUT. Further, the gate signal of P1 is the VPP itself, and the gate signal of P2 is the output of the inverter formed by the P-channel enhancement MOS transistor P3 and the N-channel enhancement MOS transistor N3. The N-channel enhancement MOS transistors N1 and N2 and the P-channel enhancement MOS transistor P4 are connected to the VPP voltage and V
A voltage detection circuit for comparing with the CC voltage is formed.

The circuit operation of FIG. 1 will be described with reference to the timing chart of FIG. First, regarding the role of the power supply, in this circuit, since the main power supply and VCC of the whole system in which this circuit is incorporated are shared, the power supply sequence is such that VPP changes after VCC supply.

There is no VPP input after VCC is applied, that is, the ground potential input to VPP is in an initial state. At this time, in the voltage detection circuit, the N-channel MOS transistor N1 and the P-channel MOS transistor P4 have no driving capability, Since the N-channel MOS transistor N2 has a driving capability, the signal B, which is the output of this voltage detection circuit, is at the GND level. Therefore, the output signal C of the inverter, that is, the gate of the P-channel MOS transistor P2 is at the VCC level. On the other hand, since the gate of the P-channel MOS transistor P1 is at the GND level, P2 is off, P1 is on, and VCC is output to the voltage output OUT.

Next, the circuit operation in the process of turning on the VPP power and increasing the voltage will be described. After turning on the VPP power,
At time t1, the voltage of VPP is VCC-Vthp (Vth
p represents the threshold value of the P-channel MOS transistor), and thereafter, the P-channel MOS transistor P1 is turned off. At time t1, the output signal B of the voltage detection circuit is GND, and the output signal C of the inverter is C.
Is a P-channel MOS because it remains at the VCC level.
Transistor P2 maintains the off state.

Here, looking at the operation of the signal A in the voltage detection circuit, the signal A is the output of the N-channel MOS transistor N1 biased to operate in a saturated state, and the VPP voltage is Vthn (Vthn Is N-channel MO
(VP threshold of S transistor)
P-Vthn-substrate bias effect voltage ", and at time t2, the voltage of VPP becomes the VCC potential.
Signal A does not reach the VCC potential.

At time t3, the potential of VPP becomes VCC + Vt
hp. At this time, since the P-channel MOS transistor P1 is in the off state and the state of the voltage detection circuit output signal B does not change, the signal C is maintained at the VCC level, but the P-channel MOS transistor P2 has the gate voltage ( VCC level) to the drain voltage (VPP = VC
(C + Vthp) exceeds the threshold value, and is turned on. Here, the transistor driving the output OUT switches to the P-channel MOS transistor P2,
The power supply switching operation is started by switching the output voltage to VPP.

As can be seen from the lapse of time so far, from time t1 to time t3, both P-channel MOS transistors P1 and P2 are in the off state, whereby both power supplies, that is, VPP and VCC are disconnected. This prevents both power supplies from being short-circuited when the driving transistor is switched. Here, from time t2 to time t3, it is conceivable that a conductive state may be established between the drain P diffusion and the well N diffusion of the P-channel MOS transistor P2. Before the switching operation of P2, the VPP voltage of the drain P diffusion of the P2 appears as an output voltage via the well N diffusion. However, even in this case, the bias of the P-channel MOS transistor P1 is
Source = VCC, gate = VPP, drain = well =
Since VPP is attained and P1 is in the OFF state, both the VPP and VCC power sources are not short-circuited similarly to the above-described power supply switching.

At time t4 when the VPP voltage rises to VCC + Vthp or more, the P-channel MOS transistor P4 in the voltage detection circuit conducts, starts to invert the signal B, and further increases the VPP voltage. In the voltage detection circuit, an N-channel MOS transistor N1
And the drive capability of the P-channel MOS transistor P4 increases, and overcomes the drive capability of the N-channel MOS transistor N2, inverting the potential of the signal B. At time t5
Then, the potential of P-channel MOS transistor P3
And an N-channel MOS transistor N3.
The level changes from the VCC level to the GND level. By the inverting operation of the inverter, the P-channel MOS transistor P2
Becomes the state having the largest drive capability, and the power supply switching operation is completed.

Here, the operation of the voltage detection circuit will be described in detail. In this circuit, while the N-channel MOS transistor N2 is kept on, the voltage from the VPP to the N-channel
S transistor N1 and P channel MOS transistor P
4 forcibly inverts the potential of the signal B via the N channel MOS transistor N1 and the P channel MOS transistor P4.
If the drive capability of the S transistor N2 is considerably reduced, the potential of the signal B is easily inverted, and the time from time t4 to time t5 at which the inverter performs the inversion operation is shortened. As a result, the power supply switching operation is performed. Required time can be shortened. Further, after time t4, the current continues to flow from the VPP input terminal to GND via the voltage detection circuit, so that the through current can be reduced by reducing the drive capability of the N-channel MOS transistor N2. The value of the through current is at most several tens of μA
However, the through current occurs only when the VPP voltage is high, that is, when writing or erasing nonvolatile memory or the like. The current does not increase. Although VPP consumes a through current, VPP may consume a current on the order of mA in a write / erase circuit, and a current of about several tens μA consumed by a voltage detection circuit is:
It does not adversely affect the operation of the voltage switching circuit or the entire system.

Even if these advantages are not considered, if the drive capability of N-channel MOS transistor N2 is too large than the drive capabilities of N-channel MOS transistor N1 and P-channel MOS transistor P4, the potential inversion operation cannot be performed. Since the function as the voltage detection circuit cannot be performed, the drive capability of the transistor included in the voltage detection circuit needs to conform to the above conditions.

VPP reaches a predetermined voltage at time t6, and thereafter, this circuit operates as a circuit for generating VPP (predetermined high voltage). The potential of the signals A and B is VP
It rises to P-α, where α is the sum of Vthn and the voltage drop due to the substrate bias effect.

When the voltage of VPP changes from a high voltage to a low voltage, it is easy to guess that the operation described so far behaves in such a manner as to make a transition that is opposite in time. Detailed description is omitted.

[0025]

As described in detail above, according to the power supply voltage switching circuit of the present invention, no special control signal is required for the two types of power supplies, and only the voltage of the input power supply is detected. A power supply switching operation capable of executing a power supply switching operation, and preventing a short-circuit state of the two types of power supply at the time of power supply switching, and realizing power supply voltage switching correctly can be realized. Things.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment.

FIG. 3 is a configuration diagram of a conventional power supply voltage switching circuit.

FIG. 4 is a configuration diagram of a conventional power supply voltage switching circuit on which the present invention is based.

FIG. 5 is a timing chart showing the operation of the power supply voltage switching circuit.

[Explanation of symbols]

P1,..., P4 P-channel enhancement MOS transistor N1, N2, N3 N-channel enhancement MOS transistor

Claims (2)

[Claims] A first fixed power supply voltage and a second variable power supply voltage that fluctuates between a reference voltage and a second fixed power supply voltage exceeding the first fixed power supply voltage; Selectively turn on / off according to the voltage value of the voltage
Two transistors that are turned off, one ends of which are respectively connected to the first fixed power supply voltage and the second variable power supply voltage, and the other ends of which are commonly connected and connected to a power supply voltage output terminal. In a power supply voltage switching circuit that selectively outputs via a transistor, a transistor control circuit that outputs an on / off control signal of the transistor based on the first fixed power supply voltage and the second variable power supply voltage. And a transistor control circuit for outputting a control signal for turning on the other transistor after one of the two transistors is turned off when the second variable power supply voltage changes. Power supply voltage switching circuit. 2. A method according to claim 1, wherein the first variable power supply voltage and a second variable power supply voltage that fluctuates between a reference voltage and a second fixed power supply voltage exceeding the first fixed power supply voltage. Selectively turn on / off according to the voltage value of the voltage
First and second P-channel transistors that are turned off, one ends of which are connected to the first fixed power supply voltage and the second variable power supply voltage, respectively, and the other ends of which are commonly connected to a power supply voltage output terminal. In a power supply voltage switching circuit for selectively outputting via a connected first and second P-channel transistor, a gate of the first P-channel transistor is supplied with the second variable power supply voltage. A transistor control circuit that outputs an ON signal to a gate of the second P-channel transistor within a voltage range of the second variable power supply voltage at which the first P-channel transistor is turned off. A power supply voltage switching circuit, which is provided.