JPH116852A - Test data impressing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce necessary memory size by providing a buffer memory receiving and buffering information with no redundancy and a redundancy memory storing redundant memory with the redundancy information as information having a certain degree of redundancy. SOLUTION: A decompression circuit 200 of a signal generation circuit is connected to device under testing(DUT) via a line 70 and to a signal analyzer via a line 90. This decompression circuit 200 is provided with a buffer memory 210 and a redundant memory 230. The buffer memory 210 has an input signal in a line 170 and its output is connected to a processor 220 via a line 240. The processor 220 is connected to the redundant memory 230 via a line 250 to the DUT via the line 70 and to a signal analyzer via the line 90. The buffer memory 210 receives and buffers information without redundancy, and the redundant memory 230 stores redundancy information as information having a certain degree of redundancy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to applying test data to a device to test the device.

[0002]

BACKGROUND OF THE INVENTION In most applications, integrated circuits (ICs) or other electronic devices are tested after production and before use. FIG. 1 shows a schematic diagram of a normal test apparatus 10. The test apparatus 10 is a tester (IC tester) 20
And a device under test (DUT) 30, which is an IC or some other electronic device. The tester 20 includes a signal generator 40, a signal receiver 50, and a signal analyzer 60.

[0003] The DUT 30 is a signal generator 40 of the tester 20.
Receives a DUT input signal on line 70 from the processor and processes this signal to generate a DUT output signal. This output signal is received by the signal receiving device 50 of the tester 20 via the line 80. The signal analyzer 60 converts the DUT input signal or the corresponding signal derived therefrom into the signal generator 40.
The DUT output signal or a corresponding signal derived therefrom is received on line 95 from the signal receiver 50. The signal analyzer 60 analyzes the signal, for example, by comparing the signal.
Accordingly, tester 20 can draw conclusions about the properties and quality of DUT 30.

[0004] For simplicity, it is to be understood that the term "line" as used herein refers to any kind of physical connection. In some applications, the lines are implemented by more or less complex data buses.

[0005] DUT input and output signals, also referred to as vector data, comprise one or more single individual vectors. Each individual vector is a signal state, or DU, applied to the input of DUT 30 at a given time.
T30 represents the state of the signal applied to the output.

[0006] Several test methods for applying test data to the DUT 30 are well known to those skilled in the art. In the case of a so-called "parallel test", DUT input data is applied to the input of DUT 30, and the DUT output is observed. During the scan test,
The internal state of the DUT 30 can be directly changed or directly monitored. DUT enabling scan test
30 requires a special storage device that can be written in a serial manner. This storage device is also serial readable. This special storage device requires a larger silicon area than a normal storage device (flip-flop). Boundary scans are often performed to reduce the additionally required area. The boundary scan device only has flip-flops that can write to the input and output of the device. Boundary scan tests are often used during board testing to directly change or monitor certain conditions at the boundaries of the DUT 30 on the board.

In some applications, signal analyzer 60 receives the expected DUT output signal from signal generator 40 and compares this signal to the actual DUT output signal received by signal receiver 50. If the DUT 30 is operating in the expected manner, the expected DUT output signal will represent the expected signal as the DUT output signal. During the test, the actually received DUT output signal is compared, for example, with the subsequently expected DUT output signal. If the signals do not match, the DUT is considered to have a functional failure and the test will fail.

FIG. 2 shows a typical circuit for generating a DUT input signal as is well known to those skilled in the art. The DUT input signal is generated under the control of the vector processor 100.
As with the processing of the program by the microprocessor,
The vector processor 100 processes a series of instructions, and the data stored in the vector memory 110 is retrieved via lines 120 on demand, but may need to be formatted appropriately. Finally, the DUT input signal is applied on line 70 to DUT 30. DU
T input signal or expected DU derived therefrom
A signal comprising or representing the T output signal is also applied on line 90.

[0009] Vector memory 110 stores vector data comprising one or more vector sequences that can be any type of data applied to DUT 30. In most cases, the vector memory 110 is implemented by a semiconductor memory, such as a random access memory (RAM), which allows its contents to be changed flexibly and quickly. The vector data is stored at a predefined address in the vector memory 110. When the vector processor 100 applies each address word on line 120 to the vector memory 110, the vector data corresponding to this address is available at the output of the vector memory 110 on line 120. This vector data is further processed by the vector processor 100 to provide a DUT input signal for testing the DUT 30 or an expected DUT.
Provided as UT output signal.

[0010] The price of the tester 20 is greatly affected by the size of the memory required to store test data for the DUT 30. In particular, when an expensive semiconductor memory is used, it is highly desirable to reduce the required memory size.

It is known to those skilled in the art that the size of vector memory 110 can be reduced by implementing appropriate commands or instructions for vector processor 100. It is used that one stream of vector data for testing the DUT 30 consists of one or more sequences of the same data. Each sequence of the same data is stored separately in the vector memory 110 and can be recalled on demand by applying the appropriate command. Therefore, the vector memory 110
Can be reduced corresponding to the frequency of repeated sequences of the same data.

[0012]

However, it has been found that this approach to reducing the required size of the vector memory 110 also has several disadvantages, such as:

1. A certain amount of memory space is needed to store the appropriate commands or instructions.

2. Some instructions are in vector memory 1
When reserving ten physically identical parts, the number of vector sequences that can be stored in the vector memory 110 is limited by the number of instructions.

3. Also, if some instructions reserve the same physical portion of vector memory 110, the instructions and vector sequences use the same memory, and thus use the same lines, or the same bus, or the same data path. There must be. Thus, the instruction and vector sequence cannot be read from memory at the same time (reading a vector sequence from memory by vector processor 100 is commonly referred to as vector generation), and a new vector is read while a new instruction is being read. No data can be generated. Therefore, if the vector stream stops, DUT3
Since zeros may behave differently, interrupts occur in the vector data stream that must be avoided. Stops in the vector stream have the effect of temperature. In some cases (e.g., phase locked loop-PLL-circuit, dynamic logic), the current state of DUT 30 changes, and a stopped DUT 30 may change its state.

4. If an instruction occupies another physical memory, additional costs are incurred for the additional memory.

5. To achieve significant improvements in memory size, a certain amount of repetitive data sequences is required.

It is an object of the present invention to provide an improved test device that requires less memory size.

[0019]

According to the present invention, a DUT is provided.
The circuit for applying test data to the DUT to test the DUT has little redundancy, but receives and buffers non-redundant information as information containing some redundant information. A buffer memory, a redundancy memory for storing the redundancy information as information having a certain amount of redundancy, and a test memory for generating test data by processing non-redundancy information related to the redundancy information. And a processing device.

The present invention preferably comprises a signal generator for generating a DUT input signal for testing a DUT;
A signal receiving device for receiving a DUT output signal from the DUT in response to the input signal; and a signal analyzer for analyzing the DUT output signal associated with the DUT input signal. Generator is DU
A circuit for applying test data to T is provided.

The present invention also provides a DUT for testing a DUT.
It can be applied as a method of applying test data to the UT. The method comprises the steps of receiving and buffering non-redundant information, retrieving the redundancy information stored in the redundancy memory by the received non-redundant information, Generating test data by processing the missing information.

According to one embodiment, the redundancy information includes information about the content of the test data that is generated several times equally without change, and the information without redundancy is the test data that is not generated several times equally. And information on the application of redundancy information.

According to another embodiment, the redundancy information includes information about the content of the test data that is generated several times without substantial change, and the information without redundancy is not generated several times. It contains information about the contents of the test data and information about the application of the redundancy information.

According to yet another embodiment, the redundancy information includes information about an access protocol used to access each DUT.

According to yet another embodiment, the information without redundancy includes information about an execution test that is substantially independent of the DUT under test, and the redundancy information includes information about a unique DUT to be tested. , Which contains specific DUT specific data.

The present invention relates to an IC for testing integrated circuits.
It is preferably used for a tester.

[0027] Other objects and many of the attendant advantages of this invention will be readily appreciated and better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0028]

FIG. 3 shows a schematic diagram of an embodiment of a signal generator 40 according to the invention. The signal generator 40 is
It comprises a vector processor 100 connected to a vector memory 110 via a line 120. Further, the vector processor 100 is connected to the decompression circuit 200 via a line 170. Decompression circuit 2
00 is connected to the DUT 30 via a line 70 and to a signal analyzer 60 not shown in FIG.

The vector processor 100 and the vector memory 11 used in the embodiment according to the present invention.
0 is the vector processor 1 used by FIG.
It should be understood that the data is physically identical to 00 and vector memory 110, but performs different functions and is loaded with different data.

FIG. 4 shows a preferred embodiment of the decompression circuit 200. The decompression circuit 200 includes a buffer
The memory 210, the processing device 220, and the redundancy memory 23
0. Buffer memory 210 has an input signal on line 170, the output of which is connected to processing unit 220 via line 240. Processing device 220
Again, via line 250, with the redundancy memory 230,
The DUT 30 is connected via a line 70 and the signal analyzer 60 via a line 90. The decompression circuit 200 according to the present invention comprises:
It should be understood that an input signal is received on line 170, which may be from any type of signal source that emits a signal suitable for decompression circuit 200. Accordingly, the present invention is not limited to the use of vector processor 100 and vector memory 110 to apply an input signal on line 170. Line 170
Any signal source that applies a suitable input signal above serves the purpose of the present invention.

The present invention provides that any information needed to test the DUT 30 is redundancy information that is information with a certain amount of redundancy and information that has little redundancy, but some redundancy. It utilizes the fact that it contains information without redundancy that also has certain information. The separation into redundancy information and non-redundancy information depends on the actual application and in some cases may not be completely implemented.

The redundancy in the information needed to generate the vector data needed to test the DUT 30 can be, for example, from repeating certain sequences of vector data without modification, or Resulting from repeating a sequence of vector data with some amount of change, such as varying, and / or distributing information among test-specific data and DUT-specific data, or a combination thereof. In each case, it may be unique to one or more sequences of vector data, or represent only changes between one or more successive sequences of vector data, or represent only test-specific data or DUT-specific data. Information can be separated as information without redundancy. Not specific to that sequence of vector data,
Alternatively, information that does not change significantly during successive sequences of vector data, or that does not represent only test-specific data or DUT-specific data, can be separated as redundancy information.

Separating the information needed to test the DUT 30 into redundant and non-redundant information can be done, for example, by analyzing a sequence of prepared vector data applied to the DUT 30, or It can be implemented by distributing information in advance during data generation. In the former case, the prepared vector
The sequence of data is analyzed, for example, by comparing the sequence of successive vector data, the redundancy information in the sequence is extracted as redundancy information, and the remaining data for the redundancy information in the sequence of vector data is And additional data is defined as information without redundancy. In the latter case, information about the sequence of continuous vector data, or access protocol, or test-specific data or DUT-specific data, or a combination thereof, must already be present during the generation of vector data. In either case, the separation can be performed manually or automatically, using a suitable tool such as a software program. Separation may be performed "on-line", i.e., just before applying the sequence of vector data to the DUT 30, or may be prepared prior to application, for example, as a stored data file.

According to the present invention, the redundancy information is stored in the redundancy memory 230, while the non-redundant information is provided as an input signal on line 170 for the decompression circuit 200. Non-redundant information may be stored, for example, in vector memory 110 or in other suitable memory.

In one embodiment, the redundancy information includes information about the contents of a sequence of vector data that occurs several times without change. Non-redundant information includes information about the contents of a sequence of vector data that is not equally generated several times. Non-redundant information further includes information about the application of redundancy information in the sequence of vector data applied to the DUT 30, such as when and how many times a sequence of vector data must be repeated. Contains.

In another embodiment, the redundancy information includes information about the contents of a sequence of vector data that occurs several times without significant changes. Non-redundant information includes information about the contents of a sequence of vector data that does not occur several times. Information without redundancy is
Further information about the application of redundancy information in the sequence of vector data applied to the DUT 30, such as information on when and how many times a sequence of vector data must be repeated, and several times, Vector with some changes
It contains information representing changes between sequences of data.

Still another embodiment takes advantage of the fact that in most test applications a more or less complex access protocol is used to access the DUT 30. In this embodiment, the redundancy information includes information about the access protocol used. The access protocol, eg, read or write, is specific to each DUT 30 and is always the same. D
For each access on the UT 30, a sequence of vector data is required. Access protocols typically require a control signal applied to the DUT 30 over a certain number of tester cycles, an address signal, and a defined sequence of signals, such as data signals. In most cases, the tester period is defined by the clock signal used to test DUT 30.

A unique access on the DUT 30 that requires a unique sequence of one or more vector data is called a unique device cycle. During a unique device cycle, the control, address, and data signals are
It generally varies only slightly from the previous vector data or sequence to the next vector data or sequence.

FIG. 5 shows an example of a unique device cycle. Signal CONTROL1 and signal CONTROL
2 follow a certain scheme determined by the respective access protocol. The signals DATA and ADDRESS that can be set at time T0 are first changed at time T0 + 6T. From T0 to T shown in FIG.
Device cycles up to 0 + 6T have a length of 6T. During this device cycle, signals CONTROL1 and C
The shape of ONCONTROL2 is independent of the respective signals DATA and ADDRESS. Within this unique device cycle, only the DATA and ADDRESS signals contain non-redundant information, in other words, information not covered by the access protocol.

In yet another embodiment, the separation of the vector data is such that the actual DU under test is
Achieved by providing information about running tests independent of T30. In contrast, the redundancy information is information about the unique DUT 30 to be tested.
Contains UT specific data. This allows the same test-specific data to be used for multiple different DUTs 30, or the same DUT-specific data can be used for multiple different tests accordingly. Non-redundant information providing test-specific data is stored in vector memory 110 and redundancy information providing DUT-specific data is stored in redundancy memory 230. DU
The redundancy memory 230 storing the T-specific data is a DUT
Processor 2 for "translating" the test-specific information into the required vector data to actually test 30
It behaves like a “dictionary” specific to the DUT used by 20.

It should be understood that the possibilities of allocating information to redundant and non-redundant information can be combined and are not limited to certain embodiments.

According to the present invention, the size of the vector memory 110 can be reduced according to a ratio determined by the ratio of information having no redundancy to information having redundancy in vector data. The amount of additional memory required for the redundancy memory 230 also depends on the amount of redundancy information determined, for example, by the access protocol used. In most cases, the total memory size for vector memory 110 and redundancy memory 230 will be much smaller than the memory size required in the art for vector memory.

The buffer memory 210 has a line 170
At the upper input terminal, information having no redundancy is received, for example, from the vector processor 100. Information without redundancy is
It contains information about the sequence of vector data applied to the DUT 30 and the signal analyzer 60 as a vector data stream. The processing unit 220 reads the non-redundant information buffered in the buffer memory 210 and generates a corresponding sequence of vector data. The processing device 220 combines the non-redundant information with the redundancy information stored in the redundancy memory 230 corresponding to each of the non-redundant information.
The processing unit 220 further assembles the read sequence of vector data into a vector data stream. The vector data stream is applied by the processing unit 220 to the DUT 30 as a DUT input signal on line 70. The processor 220 also applies the vector data stream on line 90 to the signal analyzer 60 either directly as a DUT input signal or as a signal corresponding to the DUT input signal, for example, an expected DUT output signal.

If the redundancy information comprises information about the access protocol, the information without information is information about the sequence of vector data applied to the DUT 30 and the signal analyzer 60 as a vector data stream. So-called device cycle
May contain code. The processing device 220
Devices buffered in buffer memory 210
Read the cycle code and generate a sequence of vector data. For each device cycle code, processing unit 220 combines the non-redundant information in the device cycle code with the redundancy information stored in redundancy memory 230 and reads the read vector Assembles a sequence of data into a vector data stream.

The redundancy memory 230 contains a certain number of entries. Each entry includes at least a description of the respective vector sequence and the encoded length of the vector sequence. The entry is redundancy memory 2
30 can be stored dynamically, so that the entries can be changed during the overall driving test. Redundant memory 230 is preferably implemented as a semiconductor memory such as a RAM.

Because of the separation into redundancy information and information without redundancy, the data rate, ie, the number of information per unit time, differs between line 170 and lines 70 and 90. Only non-redundant information is applied on line 170, but on lines 70 and 90
0 applies vector data that also contains non-redundant information and redundancy information.

D on line 70 applied to DUT 30
The UT input signal must be at a constant data rate. The vector stream must be free of interruptions and "hiccups, or minor inconveniences," because the DUT 30 may behave unusually (eg, thermally or dynamically). PLL state change). "Different" means that there may be differences between the simulation and the test. The simulation constitutes the source from which the vector data is applied to the DUT 30. Because testing involves very complex processes and events, it is generally attempted to minimize unknown effects that can occur. The length and number of the sequence of vector data read from the redundancy memory 230 is different from the length and number from one non-redundant information to the next information applied to the buffer memory 210, and thus the line 70
And the data rates on 90 may also be different.

It is preferred that the processing unit 220 read the buffer memory 210 when new and valid non-redundant information emerges and generates the corresponding vector data. The content and length of the generated vector data must be unambiguously determined by their non-redundant information.

To control the data rate of the vector data on lines 70 and 90, the processing unit 220
The data rate on line 240, or in other words,
The speed for reading the buffer memory 210 is controlled. This control is preferably accomplished by a control signal applied to buffer memory 210 from processing unit 220 on line 240. Therefore, the buffer memory 2
10 buffers different data rates between line 170, line 70 and line 90 in conjunction with processing unit 220. In some cases, buffer memory 210 may also be incorporated into processing unit 220.

According to the present invention, the memory size required for applying the vector data can be reduced.
That is, in other words, substantially more vectors can be stored using a given memory size.

The present invention also allows the redundancy memory 230 to decode the data vector received on line 170 into a different data vector applied to lines 70 and / or 90. Thereby, the redundancy memory 230 serves as a decoding dictionary.

FIG. 6 shows a preferred embodiment of the decompression circuit 200. The decompression circuit 200 is a CMOS VLS
I (Complementary Metal Oxide Semiconductor Very Large Scale Integrated Circuit) circuit, in which buffer memory 210 is implemented.
Is implemented as a FIFO (first in first out) memory, and the redundancy memory 230 is implemented as a RAM. The decompression circuit 200 is clocked, and each code word used in or applied to the decompression circuit 200 is represented by a 6-bit word.

Line 17 implemented as a data bus
0, the buffer memory 210 outputs the data signal DATA.
_IN, a validity check signal VALID_IN, and a control signal CTRL_IN. Line 240, 250
Is implemented as a combined data bus and comprises a data line DATA, a validation line VALID and a control line CTRL. A valid data word in the buffer memory 210 is indicated by the validity check signal VALID. When the processing unit 220 finds a valid data word in the buffer memory 210, the processing unit 220 transmits the buffer data via the data line DATA.
Read the last stored data word in memory 210. In response to the contents of the read data word, the processor 220 retrieves the respective data vector stored in the redundancy memory 230 using the control line CTRL and the data line DATA. This is indicated by the arrow between the processing unit 220 and the redundancy memory 230, indicating the information exchange between the processing unit 220 and the redundancy memory 230. The processing device 220 includes the redundant memory 23
The address signal ADDRESS and the read / write control signal RW_CTRL are signaled to 0, and the data DATA1 and the length LENGTH requested from the redundancy memory 230 are received correspondingly.

The processing unit 220 includes the buffer memory 21
Assemble one or more data vectors based on the non-redundant information provided by the current data word read from zero and the data retrieved from redundancy memory 230 by the current data word.
One or more data vectors have signals DATA_ on lines 70 and 90 embodied as a junction data bus.
Added as OUT. The data words read from the buffer memory 210 simply include the address of each data vector stored in the redundancy memory 230, causing the redundancy memory 230 to behave like a dictionary. However, the data words read from buffer memory 210 also comprise additional data. The processing unit 220 assembles the data vectors into a substantially continuous vector data stream.

When the current data word in buffer memory 210 has been processed, and if the successive data words are valid in buffer memory 210, processing unit 220 reads the successive data words, Assemble each data vector with the newly read data word. Further, a STOP signal, a RESET signal, a CLOCK signal, and a VALID
The signal lines shown in FIG. 6 such as the _OUT signal and the CTRL_OUT signal control the decompression circuit 200.
And used to communicate with other devices.

FIG. 7 shows the embodiment of FIG. 6 in more detail. To increase the processing speed, the redundancy memory 230 includes two RAM memories RAM1 and RAM2. The two data words stored in buffer memory 210 are processed together in parallel. The processing unit 220 is embodied by a state controller for controlling reading from the buffer memory 210 and retrieving data stored in the RAM1 and RAM2 of the redundancy memory 230. An assembler in the processing unit 220 receives the data read from the buffer memory 210, receives the data retrieved from the redundancy memory 230, and assembles the corresponding data vector. A shifter in the processing unit 220 matches possible delays of the data vectors applied on lines 70 and 90 with other external devices.

This state control device is a buffer memory 21
When a valid data word is found in 0, the state controller controls the retrieval of data from RAM1 and RAM2 by the read data word. Redundancy memory 230 provided as length information to state controller
The state controller controls the assembly of the data vectors by the assembler, depending on the length of the data retrieved from. Depending on the total length of the sequence of data vectors generated by the read data words from buffer memory 210, the state controller will stop or recall successive data words stored in buffer memory 210.

The embodiments of the present invention have been described in detail above. Hereinafter, examples of each embodiment of the present invention will be described.

(Embodiment 1) Although there is almost no redundancy,
As information that also contains information with some redundancy,
A buffer memory (210) for receiving and buffering information without redundancy, a redundancy memory (230) for storing redundancy information as information with a certain amount of redundancy, and a redundancy associated with the redundancy information A circuit (200) for applying test data to the DUT 30 for testing the DUT (30) comprising a processing unit (220) for processing test-less information to generate test data.

(Embodiment 2) A signal generator (40) for generating a DUT input signal for testing the DUT (30), and a DUT (3) in response to the DUT input signal.
0) and a DUT associated with the DUT input signal.
A signal analyzing device (60) for analyzing the output signal, wherein the signal generating device (40) has little redundancy, but includes information having some redundancy; A buffer memory (210) for receiving and buffering missing information, and a redundancy memory (23) for storing redundancy information as information containing a certain amount of redundancy.
0) and a processing device (22) for generating test data by processing information having no redundancy related to the redundancy information.
0) for testing the DUT (30).

(Embodiment 3) Although there is almost no redundancy,
As information that also contains information with some redundancy,
Receiving and buffering information without redundancy;
Retrieving the redundancy information stored in the redundancy memory (230) as information with a certain amount of redundancy according to the received non-redundancy information; Generating test data by processing the DUT 30 to apply the test data to the DUT 30 to test the DUT 30.

(Embodiment 4) The test in which the redundancy information includes information about the contents of test data that occurs several times equally without change, and the information that does not have redundancy occurs several times equally Embodiment 1 including information about data content and information about application of redundancy information
(200).

(Embodiment 5) The redundancy information includes information on the contents of test data that occurs several times without significant change, and the test in which the information without redundancy occurs several times. The circuit (200) of embodiment 1 including information about the content of the data and information about applying the redundancy information.

(Embodiment 6) The redundancy information is a DUT
The circuit (200) of embodiment 1, including information about an access protocol used to access (30).

(Embodiment 7) The information without redundancy is
3. The circuit of claim 1 including information about an execution test that is not significantly dependent on the DUT under test (30), and wherein the redundancy information includes DUT-specific data, ie, information about a specific DUT to be tested. (200).

(Embodiment 8) A test in which the redundancy information includes information on the contents of test data that occurs several times equally without any change, and the information that does not have redundancy is generated several times equally Embodiment 2 including information about the content of data and information about the application of redundancy information
(20).

(Embodiment 9) The redundancy information includes information on the contents of test data that occurs several times without significant change, and the test without the redundancy occurs several times. A tester (20) according to embodiment 2, including information about the content of the data and information about the application of the redundancy information.

(Embodiment 10) The redundancy information is a DU
Access used to access T (30)
The tester (20) according to embodiment 2, including information about the protocol.

(Embodiment 11) The information without redundancy includes information on an execution test that is not greatly affected by the DUT under test (30), and the redundancy information is a DU.
3. The tester (2) according to embodiment 2, which includes T-specific data, ie, information about the specific DUT to be tested.
0).

(Embodiment 12) A test in which the redundancy information includes information on the contents of test data that occurs several times equally without change, and the information without redundancy has the same number of times. 4. The method of embodiment 3 including information about the content of the data and information about applying the redundancy information.

(Embodiment 13) The redundancy information includes information on the contents of test data that occurs several times without any significant change, and the test without the redundancy information occurs several times. 4. The method of embodiment 3 including information about the content of the data and information about applying the redundancy information.

(Embodiment 14) The redundancy information is DU
Access used to access T (30)
4. The method of embodiment 3 including information about the protocol.

(Embodiment 15) The information without redundancy includes information on an execution test which is not largely influenced by the DUT under test (30), and the redundancy information is a DU.
4. The method of embodiment 3, including T-specific data, ie, information about the specific DUT to be tested.

(Embodiment 16) Use of the circuit (200) according to Embodiment 1 in an IC tester (20).

(Embodiment 17) A buffer memory (210) for receiving and buffering information having no redundancy as information information which has little redundancy but also includes information having a certain degree of redundancy. Redundancy memory (230) for storing redundancy information as information with an amount of redundancy
A circuit (200) for applying test data to the DUT (30) for testing the DUT (30), comprising: a processor (220) for generating test data by processing non-redundant information related to the redundancy information; IC tester (20) comprising:

[0076]

As described above, according to the present invention, it is possible to provide an improved test apparatus requiring a small memory size.

Further, according to the present invention, the memory size required for applying vector data can be reduced. That is, in other words, substantially more vectors can be stored using a given memory size.

Further, according to the present invention, the redundancy memory 23
A zero can be used to decode the data vector received on line 170 into a different data vector applied to lines 70 and / or 90. Thereby, the redundancy memory 230 can be used as a decoding dictionary.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a normal test apparatus 10.

FIG. 2 shows a conventional circuit for generating a DUT input signal, which is well known to those skilled in the art.

FIG. 3 is a schematic diagram of an embodiment of a signal generator 40 according to the present invention.

FIG. 4 illustrates a preferred embodiment of the decompression circuit 200.

FIG. 5 shows an example of a specific device cycle.

FIG. 6 illustrates a preferred embodiment of the decompression circuit 200.

FIG. 7 shows the embodiment of FIG. 6 in more detail.

[Explanation of symbols]

 Reference Signs List 10: test equipment 20: tester 30: DUT 40: signal generator 50: signal receiver 60: signal analyzer 70, 80, 90: line 100: vector processor 110: vector memory 120, 170: line 200: compression Release circuit 210: Buffer memory 220: Processing unit 230: Redundancy memory 240, 250: Line

Claims (1)

[Claims] 1. A buffer memory for receiving and buffering information having no redundancy as information containing little redundancy but having some degree of redundancy, and information having a certain amount of redundancy. Comprising: a redundancy memory for storing redundancy information; and a processing device for generating test data by processing information having no redundancy related to the redundancy information.
Circuit that applies test data to the DUT to test