JPH1166022A - Cluster system - Google Patents

Abstract

(57) [Problem] To provide a technique capable of reducing the latency of inter-processor communication and routing inter-processor access. An instruction using an access address having a routing field indicating whether to access a local system or a remote system, and a real address field for accessing a normal address space in a computer of the system. And a routing adapter for transmitting a processing request for an instruction to access the remote system to the remote system indicated by the routing field of the access address of the instruction, and a routing field for the instruction issued by the processor to the remote system. And a system connection mechanism for passing a processing request for an instruction issued by the processor to the routing adapter when access to the routing adapter is indicated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cluster system for performing data access and inter-processor communication between a plurality of processors, and more particularly to a cluster system that suppresses latency when performing data access and inter-processor communication between a plurality of processors. The present invention relates to a technology that is effective when applied to a cluster system that can have a large-scale configuration.

[0002]

2. Description of the Related Art In a cluster system in which a plurality of processors are connected, processing contents are distributed to a plurality of processors, and communication between processors and data access to input / output devices such as a plurality of magnetic disk devices are performed in accordance with the processing contents. To perform parallel processing.

In communication between processors in a conventional cluster system, data is created as a message,
Message passing is used to transmit and receive messages between processors by transmitting to a destination processor using a communication function, or directly accesses an address where data of a partner processor is stored by using a load / store instruction, and transmits to another processor. There is a way to read and write data.

In a conventional cluster system, when data is accessed between a processor and an input / output device such as a magnetic disk device, a DMA (Direct) is used.
Data access is performed via a memory using Memory Access.

[0005]

In the message passing of the conventional cluster system, since messages are transmitted and received between processors, access between processors can be routed by changing the destination of the message, so that a large-scale configuration is adopted. However, there is a problem that the latency increases.

In the conventional cluster system, when inter-processor communication is performed using a load / store instruction, direct access is made to an address at which data of a partner processor is stored, so that the latency is small but a large-scale configuration cannot be obtained. There is a problem.

Further, in the above-mentioned conventional cluster system, when data is accessed between a processor and an input / output device such as a magnetic disk device, the data is accessed via a memory using DMA, and the data is input from the processor. There is a problem that the access to the output device cannot be directly performed by the load / store instruction.

An object of the present invention is to solve the above problems and to provide a technique capable of reducing the latency of inter-processor communication and routing access between processors.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a cluster system for executing parallel processing by communicating between a plurality of computers connected via a network, and to a device in a computer of a local system or a remote system. Access is performed by load / store instructions.

In the cluster system according to the present invention, when an access is made to a device or a normal address space in a computer of a local system which is a local system or a remote system which is a system other than the local system, the processor is controlled by the local system or the local system. An instruction is issued using an access address having a routing field indicating which system of the remote system is to be accessed and a real address field for accessing a normal address space in a computer of the system.

The system connection mechanism receives the instruction issued by the processor, checks the routing field of the access address, and, if the routing field is not valid, the local system indicated in the real address field of the access address. Access to the normal address space within

Further, as a result of checking the routing field of the access address of the instruction issued by the processor, the system connection mechanism finds that the routing field is valid, and the routing field is used for input / output of a magnetic disk device or the like in the local system. When the device is indicated, access is made to the input / output device in the local system indicated in the real address field of the access address.

Further, as a result of examining the routing field of the access address of the instruction issued by the processor, if the routing field is valid and indicates the address to the computer of the remote system, the system connection mechanism determines that the processor has the address. Pass the processing request of the instruction issued by the to the routing adapter.

The routing adapter receives, from the system connection mechanism, a processing request for an instruction for accessing the computer of the remote system, and transmits the processing request for the instruction to the computer of the remote system indicated by the routing field of the access address of the instruction. I do.

The routing adapter of the remote system that has received the processing request for the command executes the processing request for the command in the remote system, and transmits the response if the command requires a response. Send to the original routing adapter.

As described above, according to the cluster system of the present invention, since the instruction using the access address having the routing field and the real address field is used, the latency of the inter-processor communication is reduced and the inter-processor access is reduced. It is possible to do routing.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A cluster system according to an embodiment for accessing an input / output device in a computer of a local system or a computer of a remote system using an access address having a routing field and a real address field will be described below. .

FIG. 1 is a diagram showing a schematic configuration of a cluster system according to the present embodiment. As shown in FIG. 1, the computer 100 includes a system connection mechanism 101, a local memory 102, a monitoring processor 103, a processor bus 110, processors 111 and 112, a system bus 120, a core I / O adapter 130, , Serial I
/ F 131, a parallel I / F 132, a bus adapter 140, an I / O bus 150, a routing adapter 160, a SCSI adapter 170, and magnetic disk devices 180 to 182.

The system connection mechanism 101 is a processor 11
1 and 112, the local memory 102, the monitoring processor 103, and the system bus 120 are connected. If the routing field of the instruction issued by the processor 111 or 112 indicates that the remote system is to be accessed, A processing device that passes a processing request for the command to the routing adapter 160. The local memory 102 is a memory in the computer 100. The monitoring processor 103 is a processing device that monitors the operation state of the entire system.

The processor bus 110 includes a processor 111
And a bus connecting the processor 112 and the processor 112. The processors 111 and 112 use an access address having a routing field indicating whether to access a local system or a remote system, and a real address field for accessing a normal address space in the computer 100 of the system. The processing unit issues the instruction. System bus 12
0 is a core I / O adapter 130 and a bus adapter 140
And a bus connecting the routing adapter 160 to the bus.

The core I / O adapter 130 is a serial I / O
An adapter for connecting a standard input / output interface such as F131 or parallel I / F132. Serial I / F1
Reference numeral 31 denotes an interface for connecting peripheral devices via a serial cable. The parallel I / F 132 is an interface for connecting peripheral devices with a parallel cable.

The bus adapter 140 is an adapter for connecting the I / O bus 150 to the system. I / O bus 150
Is a SCSI adapter 170 (Sm
all Computer System Inter
face adapter). The routing adapter 160 connects the computer 100, the computer 200, and the computer 300, and transmits a processing request and a response of an instruction for accessing the remote system to the remote computer 2 shown in the routing field of the access address of the instruction.
00 or an adapter for transmitting and receiving to and from the computer 300.

The SCSI adapter 170 is connected to the I / O bus 15
0 The adapter is connected. Magnetic disk drive 1
Reference numerals 80 to 182 denote storage devices for storing data of the computer 100.

The network 500 includes the computer 10
This is a communication line connecting 0, 200 and 300.

In the cluster system of this embodiment, the routing adapter 160 is connected to the system bus 120.
, But may be connected to the I / O bus 150. The configuration of the computer 200 and the computer 300 connected to the computer 100 via the network 500 is the same as that of the computer 100.

FIG. 2 shows load / stor of the present embodiment.
It is a figure showing the example of a format of access address of e instruction. As shown in FIG. 2, the access address 800 has a routing field 810 and a real address field 860.

The routing field 810 is a field for storing routing information for accessing an input / output device of the local system or a remote system. The real address field 860 is a field for storing address information for accessing a normal address space in a computer of the system.

In the cluster system of the present embodiment, 6
When accessing using a 4-bit address,
For example, as shown in FIG. 2, the upper 24 bits are used as the routing field 810, and the lower 40 bits are used as the real address field 860.

FIG. 3 is a diagram showing a format example of the routing field 810 of the present embodiment. As shown in FIG. 3, the routing field 810 includes a control field 820, a system ID 830, and a layer ID 84.
0 and a sublayer ID 850.

The control field 820 is a field for storing control information such as whether the routing field 810 is valid. The system ID 830 is an ID for identifying the computers 100, 200, and 300.
The layer ID 840 is an ID for identifying a group that realizes a specific function in each computer. Sublayer ID
850 is an ID for identifying an individual device in the group indicated by the layer ID 840.

Bit 6 of routing field 810
0 to 63 are control fields 820. Bit 6
3 is a bit indicating whether the routing field 810 is valid. If the bit 63 is “1”, it indicates that the routing field 810 is valid. If the bit 63 is “0”, the routing field 81 is valid.
0 represents invalid.

Bit 62 is a bit indicating whether or not access to access address 800 is an access to the local system which is its own system.
Is '0', indicating an access to the local system, and when bit 62 is '1', it indicates an access to a local system other than the own system.

Bits 60 and 61 indicate the form of data transfer for access to access address 800,
When bits 60 and 61 are '00'B, it indicates unicast, and when bits 60 and 61 are'11'B, it indicates broadcast. Here, '00'B
And '11'B represent a binary number. Hereinafter, when indicating binary data, it is described as'' B.

Bits 52 to 59 are the system ID 830
In the cluster system of the present embodiment, one system ID 830 is assigned to each of the computers 100, 200, and 300, but a plurality of system IDs 830 may be assigned to one. However, duplication of the value of the system ID 830 is not allowed.

Bits 48 to 51 represent a layer ID 840, which indicates an ID for identifying a subsystem that realizes a specific function in each computer. Bit 47
To 40 represent a sublayer ID 850, which is a SCSI adapter 170, a magnetic disk device 180 to 182, or a LAN (L
4 shows an ID for identifying an adapter (local area network) or the like.

FIG. 4 is a diagram showing an example of assignment of the layer ID 840 and the sublayer ID 850 in the present embodiment.
FIG. 4 illustrates an example of assignment of the layer ID 840 and the sublayer ID 850 of the local memory 102, the bus adapter 140, and the core I / O adapter 130 of the cluster system according to the present embodiment, and the layer ID 840 of the local memory 102 is “00” H. , The sublayer ID 850 is “00” H. Here, '00'H represents a hexadecimal number. Hereinafter, when indicating hexadecimal data, it is described as'' H ''.

The layer ID 8 of the bus adapter 140
40 is '01'H, sublayer ID 850 is'00'H
And the layer ID 840 of the core I / O adapter 130
Is '0F'H, and the sublayer ID 850 is'00'H.

FIG. 5 is a diagram showing an example of assignment of the routing field 810 according to this embodiment. FIG. 5 shows the computer 100, the system ID 830 of the computer 200 and the computer 300, and the computer 100
ID 840 and sub-layer ID 85 of each device within
The example of the allocation of 0 is shown.

As shown in FIG. 5, the system ID 830 of the computer 100 is "01" H, the system ID 830 of the computer 200 is "02" H, and the system ID 830 of the computer 300 is "03" H.

The local memory 10 of the computer 100
2. Core I / O adapter 130 and bus adapter 140
The layer ID 840 and the sub-layer ID 850 of FIG.
As shown in FIG. The layer ID 840 of the routing adapter 160 is “02” H, and the sublayer ID 850 is “00” H.

SC connected to bus adapter 140
The layer ID 840 of the SI adapter 170 is'01'H, which is the same as that of the bus adapter 140. SCSI adapter 1
Since 70 is connected to the I / O bus 150 of the bus adapter 140, it has the same layer ID 840. Also, S
The sublayer ID 850 of the CSI adapter 170 is' 0
1′H.

FIG. 6 is a diagram showing an example of an address map of the entire access address according to the present embodiment. As shown in FIG. 6, the address map is a real address space 900.
, Access space 910 and SCSI adapter space 92
0, a local broadcast space 930, an access space 940, and a broadcast space 950.

The real address space 900 is a space where the computer 100 normally accesses. The access space 910 is a space for performing access using the routing information in the computer 100. The SCSI adapter space 920 is the SCSI adapter 17 of the computer 100.
This is a space for accessing an input / output device connected to the “0”.

The local broadcast space 930 is a space used when broadcasting is performed in the computer 100. The access space 940 is the computer 20
0 or a space for accessing the computer 300 using the routing information. The broadcast space 950 is a space used when broadcasting the entire system.

FIG. 6 shows an example of an address map of the entire access address as viewed from inside the computer 100. In the cluster system of this embodiment, since the real address field 860 has 40 bits, it is changed from '0'H to' 0 '. The normal real address space 900 extends to 0ffffffffff'H.

The access to the real address space 900 is performed when the routing field 810 is invalid or a device having no routing function.

'8000000000000000'H
From 'bffffffffffffffffff'H to
Routing field 810 in computer 100
This is an access space 910 in the case where an access is made using a. The access space 910 includes a SCSI adapter space 920 and a local broadcast space 930 in the computer 100.

'C0000000000000000000'H
The space from to is a space for accessing other than the computer 100. 'c000000000000000
0'H to 'effffffffffffff'H is an access space 940 to other than the computer 100.
The broadcast space 950 is from 'f000000000000000000'H to'ffffffffffffffffff'H.

FIG. 7 shows a SCSI adapter 1 according to this embodiment.
70 is a diagram illustrating an example of an address map of FIG. As shown in FIG. 7, the SCSI adapter space 920 has a SCSI adapter internal space 921 and access spaces 922 to 924.

The SCSI adapter internal space 921 is SCS
A space for accessing the controller of the I adapter 170. The access spaces 922 to 924 are spaces for accessing the magnetic disk devices 180 to 182.

FIG. 7 shows an example of an address map of the SCSI adapter 170 of the computer 100.
From 1101000000000000'H to '801101
00ffffffff'H is the SCSI adapter 170
A SCSI adapter internal space 921 for accessing an internal controller.

'801101010000000000'H
Access space 922 to the magnetic disk drive 180
Are assigned, and similarly, the magnetic disk drive 1
Access space 923 to the storage device 81 and the magnetic disk drive 18
2 is assigned an access space 924.

In the cluster system according to the present embodiment,
The case of a magnetic disk having a capacity of 4 GB is taken as an example,
The allocated space can be changed according to the capacities of the magnetic disk devices 180 to 182.

FIG. 8 is a diagram showing a schematic configuration of the routing adapter 160 of the present embodiment. As shown in FIG.
The routing adapter 160 is the DMA controller 1
61, a buffer memory 162, and a processor 163
, ROM 164, network controller 165
And a timer 166.

The DMA controller 161 is the processor 1
11 and a controller that transmits and receives data to and from the local memory 102. The buffer memory 162 is a storage device that buffers transmission / reception data and stores control tables and the like used by the processor 163. The processor 163 is a processing device that controls the operation of the entire routing adapter 160 and controls interrupts from the DMA controller 161 and the network controller 165 and data transmission and reception.

The ROM 164 stores the routing adapter 16
0 is a storage device for storing a control program for controlling the operation of “0”. The network controller 165 is a controller that transmits and receives data via the network 500. The timer 166 is a clock device built in the processor 163.

FIG. 9 shows a network 500 of this embodiment.
It is a figure showing the outline of the above-mentioned frame format. FIG.
As shown in FIG.
, A destination access address field 560, a source access address field 570, a transmission data field 580, and an error information field 590.

The command field 550 is a field for indicating the contents of a frame instruction. The destination access address field 560 is a field for storing the access address 800 of the transmission destination. The source access address field 570 is a field for storing the source access address 800.

The transmission data field 580 is a field for storing data to be transmitted. The error information field 590 contains a CRC (Cyclic Redundancy).
This field stores information for performing error detection and correction such as (yCheck).

The command field 550 of the frame transmitted over the network 500 is composed of one byte, bits 5 to 7 indicate the contents of the command, and bits 0 to 4 indicate the data length.

When the command content of bits 5 to 7 of the command field 550 is “111” B, it indicates an error notification, when the command content is “101” B, it indicates a response to a read request, and when the command content is “100” B, If there is, it indicates a read request, and if it is'010'B, it indicates a write request.

The data length of bits 0 to 4 of the command field 550 indicates n when the length of the transmission data field 580 is represented by 2 n, for example, when the length of the transmission data field 580 is In the case of 32 bytes, "5" is stored in the data length of bits 0 to 4 of the command field 550.

The destination access address 800 and the source access address 800 are stored in the destination access address field 560 and the source access address field 570, respectively.

The error information field 590 is 4 bytes, and stores an error detection / correction code such as CRC for the command field 550 to the transmission data field 580.

When the frame transmitted on the network 500 is a response to a read request or a write request, there is a transmission data field 580, but when the frame is a read request, there is no transmission data field 580.

FIG. 10 is a diagram showing an outline of a sequence when a store instruction is issued according to the present embodiment. FIG. 10 shows an operation sequence when data is transmitted from the computer 100 to the computer 200. The processor 111 of the computer 100 issues a store instruction for writing to the computer 200.

At this time, the access address 800 of the store instruction is “c02xxxxxxxxxxxxxxx” H
In xxxx, an address previously negotiated between applications performing communication on both computers is set.

In the computer 100, the processor 1
When 11 issues the store instruction, the system connection module 101 receives the store instruction issued by the processor 111 and determines the access address 800 of the store instruction.

First, the system connection mechanism 101
Referring to bit 63 in the routing field 810 of the access address 800 of the re instruction, it is determined whether the routing field 810 is valid. If the routing field 810 is invalid, 40
The store operation is performed on the address indicated in the bit real address field 860.

Also, the system connection mechanism 101
As a result of determining whether or not the routing field 810 of the access address 800 of the re instruction is valid, if the routing field 810 is valid, the bit 62 in the routing field 810 is referred to next to access the remote system. Is determined. Note that the determination of the bits 62 and 63 in the routing field 810 may be performed simultaneously.

The system connection mechanism 101 includes the processor 1
11, the routing field 810 of the store instruction issued by the processor 11 indicates that the remote system is to be accessed.
The processing request of the e instruction is passed to the routing adapter 160.

That is, when the routing field 810 indicates that the remote system is to be accessed, the system connection mechanism 101 passes the access address 800 of the store command and the data processed by the store command to the routing adapter 160.

The DMA controller 161 of the routing adapter 160 transmits the access address 800 of the store instruction passed from the system connection unit 101 and its data to the FIFO (First) of the DMA controller 161.
(In First Out) memory and notifies the processor 163 of an interrupt.

The processor 163 of the routing adapter 160 determines whether or not the page including the access address 800 of the store instruction (4 KB area located at the 4 KB boundary) hits the buffer memory 162.

Access address 800 of store instruction
Is hit in the buffer memory 162, the hit buffer address is instructed to the DMA controller 161 and the area is used as a transmission buffer for the data.

In this way, the data in the hit area can be purged. This function enables reading and writing to the same access address 800 in a hit area.

Further, the processor 163 of the routing adapter 160 determines the access address 8 of the store instruction.
As a result of determining whether or not the page including “00” hits the buffer memory 162, the page including the access address 800 of the “store” instruction becomes
If no hit is found, a new transmission buffer is allocated to the buffer memory 162, and the allocated buffer address is instructed to the DMA controller 161.

The DMA controller 161 having received the instruction of the buffer address of the transmission buffer from the processor 163 of the routing adapter 160 stores the data at the designated buffer address.

Further, the routing adapter 160
The DMA controller 161 compares the relationship between the access address 800 of the "store" instruction and the buffer address of the transmission buffer.
Access address 80 once accessed
As for 0, data may be read and written without generating an interrupt to the processor 163.

The DMA controller 161 of the routing adapter 160 notifies the end of the data to be processed by the store instruction to the DMA controller 161 of the routing adapter 160 transmitted from the processor 111 to the DMA controller 161 itself.
It is determined by an ore instruction.

That is, the access address 800 to the DMA controller 161 itself is' 801200xxx
xxxxxxxxx'H, and the processor 111 notifies the DMA controller 161 of the end of the data by writing the final address stored in the transmission buffer to this address, so that the DMA controller 16
1 detects the end of the data by a store instruction to the DMA controller 161 itself, and
Generates an interrupt.

The processor 163 that has received the interrupt indicating the end of the data from the DMA controller 161 creates a header for transmitting data to the network 500 as shown in FIG. 9, and sets the buffer address of the transmission buffer storing the data. Notify the network controller 165.

Network controller 1 having received the buffer address of the transmission buffer from processor 163
Reference numeral 65 reads data from the buffer memory 162 and transmits the data, and sends a processing request for a store instruction to the remote system.

FIG. 11 is a diagram showing an outline of a sequence at the time of receiving the store data according to the present embodiment. FIG.
4 illustrates an operation sequence when the computer 100 receives a processing request for a store instruction from the computer 200 or the computer 300.

First, the processor 1 of the computer 100
When the routing adapter 160 receives, from the processor 163 of the routing adapter 160, a reception notification indicating that the data has been received when the routing adapter 160 receives the data from the remote system, the processor 163 of the routing adapter 160 transmits the reception notification to the processor 163 of the routing adapter 160 in advance. Instruct transmission.

When the routing adapter 160 of the computer 100 receives a frame indicating a write request,
The network controller 165 of the routing adapter 160 determines the contents of the command field 550 and the other party access address field 560 in the received frame.

The destination access address field 560 contains the access address 8 of the transmission destination of the frame.
00, the network controller 16
5 indicates that the system ID 830 therein is the computer 10
It is determined whether it is equal to the system ID 830 of 0.

If the system ID 830 in the access address 800 of the other party access address field 560 is equal to the system ID 830 of the computer 100, the routing adapter 160 of the computer 100
The data in the frame is directly stored in the local memory 102 by the MA controller 161.

When the DMA controller 161 stores all data in the local memory 102 and completes the data reception, the network controller 165 notifies the processor 163 of an interrupt indicating that the data reception has been completed.

The processor 163 of the routing adapter 160 checks whether a reception notification instruction for the address has been received from the processor 111 in advance. If the instruction has been received, the processor 163 indicates the reception completion to the processor 111. An interrupt is notified, and if the instruction has not been received, the process ends without notifying the interrupt.

FIG. 12 is a diagram showing an outline of the execution of the load instruction and the sequence of its response according to the present embodiment. FIG.
00 shows an operation sequence when requesting transmission of data of 00, and the processor 111 of the computer 100
Lo to request the computer 200 to read data
Issue an ad instruction.

When the processor 111 of the computer 100 issues a load instruction, the system connection mechanism 101
Receives the load instruction issued by the processor 111 and determines the access address 800 of the load instruction in the same manner as in the sequence shown in FIG.

As a result of determining the access address 800 of the load instruction, the system connection mechanism 101 passes the load instruction to the routing adapter 160 when the access address 800 indicates an access to the remote system.

Upon receiving the load instruction, the routing adapter 160 of the computer 100 receives the load instruction.
A read request for the instruction access address 800 is transmitted to the routing adapter 160 of the computer 200.

Subsequently, the routing adapter 160 of the computer 100 issues a read request for the entire page including the access address 800 of the load instruction to the routing adapter 160 of the computer 200.
This is because the pre-reading is performed on the assumption that the address area continuous to the access address 800 of the load instruction is highly likely to be continuously read.

When the read data returns from the routing adapter 160 of the computer 200, the routing adapter 160 of the computer 100 transmits the data sent from the computer 200 to the processor 111.
To return.

When the load instruction is continuously issued from the processor 111 of the computer 100, since the entire page is read ahead, the access address 800 of the load instruction is set to the routing adapter 16 this time.
The buffer memory 162 in 0 is hit, and the data is read from the buffer memory 162.

FIG. 13 is a diagram showing an outline of a sequence when a frame error occurs according to the present embodiment. When issuing a read request from the routing adapter 160, the routing adapter 160 of the computer 100
Set 66. If the read request frame is lost in the network 500, the timer 166 times out.
The 0 routing adapter 160 resends the read request.

The routing adapter 160 of the computer 200 that has received the retransmitted read request reads the data from the local memory 102 of the computer 200 and returns the data. It is assumed that the number of retries when a timeout occurs is variable by setting from the processor 111.

FIG. 14 is a diagram showing an outline of a mechanism for preventing the processor 111 from stalling for a long time due to the load instruction of the present embodiment. When the data of the computer 200 or the computer 300 is read from the computer 100 in the cluster system of the present embodiment, the processor 111 of the computer 100 usually sets the bit 62 to the remote system and sets the system ID 830 of the computer 200 or the computer 300.
Is issued at the access address 800 in which is set.

On the other hand, in order to prevent the processor 111 from being stalled for a long time by the load instruction, before issuing the load instruction (hereinafter referred to as a load instruction b) to the remote system, the bit 6 of the access address 800 is read.
Only two different (leaving as local system) loa
Issue a d instruction (hereinafter, referred to as a load instruction b '). The fields other than the bit 62 of the access address 800 of the load instruction b and the load instruction b ′ are all the same.

In the system connection mechanism 101, the bit 62 in the routing field 810 of the access address 800 of the load instruction b 'indicates access to the local system, and its system ID 830 indicates a remote system other than the computer 100. In this case, the load instruction b ′ is passed to the routing adapter 160.

Upon receiving the load instruction b ', the routing adapter 160 determines whether or not the data indicated by the access address 800 has hit the buffer memory 162. Returns 0'H.

Processor 111 determines the data returned from routing adapter 160 and stores the data indicated by access address 800 in buffer memory 162.
, The load instruction b is continuously issued, and the data is read.

If the data is not hit, the routing adapter 1 sends a reception interrupt notification for generating an interrupt when the data of the access address 800 is received.
60, the process that issued the load instruction b 'is put to sleep and put into a reception interrupt waiting state.

Upon receiving the data from the remote system, the routing adapter 160 notifies the processor 111 of the interruption and restarts the process of the process, and the process restarted issues the load instruction b.

As described above, in the cluster system of this embodiment, the data of the remote system is stored in the buffer memory 1.
If the hit has not been hit in 62, the process that issued the load instruction is put to sleep and put into a reception interrupt waiting state, so that the processor 111 can execute another process.

Note that the routing of frames on the network in the cluster system of this embodiment is performed using the system ID 830. In the cluster system according to the present embodiment, since the system corresponding to the system ID 830 is uniquely determined, it is possible to perform routing using the system ID 830, and a general LAN
Like a switch, the system ID 830 stored in a passing frame may be stored for each communication port connected to the network 500.

Accordingly, the network 500 of the cluster system according to the present embodiment can be configured in a multistage connection as shown in FIG.

FIG. 15 is a diagram showing an example of the multi-stage network configuration of the present embodiment. As shown in FIG. 15, the cluster system having a multi-stage network configuration includes a magnetic disk device 280, a magnetic disk device 380, a disk subsystem 400, and magnetic disk devices 480 and 481.
, Networks 600 and 601, and a router 700.

The magnetic disk device 280 is a computer 2
00 is a storage device for storing 00 data. The magnetic disk device 380 is a storage device for storing data of the computer 300. The disk subsystem 400 is a system that manages the magnetic disk devices 480 and 481.

The magnetic disk devices 480 and 481 are storage devices for storing data of the disk subsystem 400. Networks 600 and 601 are computers 1
00 and a computer 200, and a communication line for connecting the computer 300 and the disk subsystem 400. The router 700 is an internetwork device that connects the network 600 and the network 601.

FIG. 15 shows the network 50 shown in FIG.
1 shows an example of a system configuration in a case where the number of stages is 0, a magnetic disk device 180 is connected to the computer 100, and the magnetic disk device 2 is connected to the computer 200.
80, the magnetic disk drive 380 is connected to the computer 300, and the disk subsystem 4
00 and the magnetic disk drives 480 and 48
1 for each computer 100, computers 200 and 3
It is accessible from 00.

The magnetic disk devices 180, 280, and 380 connected to the respective computers 100, 200, and 300 also have the magnetic disk devices 480, 481 connected to the disk subsystem 400. Can be accessed by a load / store instruction.

As described above, according to the cluster system of the present embodiment, since the instruction using the access address having the routing field and the real address field is used, the latency of the inter-processor communication is reduced and the inter-processor communication is performed. It is possible to route access.

[0116]

According to the present invention, since an instruction using an access address having a routing field and a real address field is used, it is possible to reduce the latency of inter-processor communication and to route inter-processor access. It is.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of a cluster system according to an embodiment.

FIG. 2 is a diagram illustrating a format example of an access address of a load / store instruction according to the embodiment;

FIG. 3 is a diagram illustrating a format example of a routing field 810 according to the embodiment.

FIG. 4 is a diagram illustrating an example of assignment of a layer ID 840 and a sublayer ID 850 according to the present embodiment.

FIG. 5 is a diagram illustrating an example of assignment of a routing field 810 according to the present embodiment.

FIG. 6 is a diagram illustrating an example of an address map of an entire access address according to the embodiment;

FIG. 7 is a diagram illustrating an example of an address map of the SCSI adapter 170 according to the embodiment.

FIG. 8 is a diagram showing a schematic configuration of a routing adapter 160 of the present embodiment.

FIG. 9 is a diagram illustrating an outline of a frame format on a network 500 according to the present embodiment.

FIG. 10 is a diagram illustrating an outline of a sequence when a store instruction is issued according to the embodiment.

FIG. 11 is a diagram illustrating an outline of a sequence at the time of receiving store data according to the present embodiment.

FIG. 12 is a diagram illustrating an outline of a sequence of execution of a load instruction and a response thereof according to the embodiment;

FIG. 13 is a diagram illustrating an outline of a sequence when a frame error occurs according to the present embodiment.

FIG. 14 illustrates a processor 11 using a load instruction according to the present embodiment.
FIG. 2 is a diagram showing an outline of a mechanism for preventing the stall 1 from stalling for a long time.

FIG. 15 is a diagram illustrating an example of a multi-stage network configuration according to the present embodiment.

[Explanation of symbols]

100, 200 and 300: Computer, 101: System connection mechanism, 102: Local memory, 103: Monitoring processor, 110: Processor bus, 111 and 1
12 processor, 120 system bus, 130 core I / O adapter, 131 serial I / F, 132
Parallel I / F, 140 ... Bus adapter, 150 ... I /
O bus, 160: routing adapter, 170: SC
SI adapter, 180-182 ... magnetic disk device, 5
00: network, 800: access address, 81
0: routing field, 860: real address field, 820: control field, 830: system ID, 840: layer ID, 850: sublayer I
D, 900: real address space, 910: access space, 920: SCSI adapter space, 930: local broadcast space, 940: access space, 950
... broadcast space, 921 ... SCSI adapter internal space, 922-924 ... access space, 161 ... DM
A controller, 162 buffer memory, 163 processor, 164 ROM, 165 network controller, 166 timer, 550 command field, 560 partner access address field, 570
... Sender access address field, 580 ... Transmission data field, 590 ... Error information field, 28
0: magnetic disk drive, 380: magnetic disk drive, 4
00: disk subsystem, 480 and 481: magnetic disk drive, 600 and 601: network, 70
0 ... Router.

Claims (3)

[Claims] In a cluster system that executes parallel processing by communicating between a plurality of computers connected via a network, a routing field indicating which of a local system and a remote system is to be accessed, A processor for issuing an instruction using an access address having a real address field for accessing a normal address space in a computer of the system; and a processing request for the instruction for accessing the computer of the remote system, the access address of the instruction. A routing adapter for transmitting to the computer of the remote system indicated by the routing field of the above, and a case where the routing field of the instruction issued by the processor indicates that the remote system is to be accessed. A system connection mechanism for passing a processing request for an instruction issued by the processor to the routing adapter. 2. The routing adapter according to claim 1, wherein the processing request for the command to be transmitted to the computer of the remote system is a command for reading a specific access address in the computer of the remote system, 2. The cluster system according to claim 1, wherein the cluster system transmits a read request for pre-reading a specific address area including the access address to the computer of the system. 3. The processor according to claim 1, wherein the processing request of the command transmitted to the computer of the remote system is a command for reading a specific access address in the computer of the remote system, and the data of the access address can be prepared in the routing adapter. If not,
3. The process according to claim 1, wherein a receiving interrupt for generating an interrupt when the data of the access address is received is instructed to the routing adapter, and the process which has issued the instruction is temporarily stopped. Cluster system described in.