JPH1154524A - Semiconductor device having transistor and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a high-performance junction field effect transistor(JFET), whose structure is simple and manufacture is easy. SOLUTION: JFET has a GaAs substrate 1, a p<+> impurity diffused region constituting gate region 15 of the JFET, an n-type channel forming impurity region 110, low-concentration n<+> -type diffused regions (n<+> regions) 111 and 121 having the LDD structure, whose ion concentration is low, and n-type impurity diffused regions (n<++> regions) 112 and 122 having the high ion concentration. The high-concentration n-type impurity regions 112 and 122 are made to function as the source region and the drain region of the JFET, respectively. This JFET is manufactured by using self-aligning technology and LDD technoloty. As a result, the short gate is achieved, the gate-drain width is expanded, the breakdown voltage is imported, and the short-channel effect can be improved. Furthermore, there is no junction capacitance at the side surface of the gate region 15. The capacitance between the gate region 15 and the source region 112 and the capacitance between the gate region 15 and the drain region 122 become very small values, and the high frequency characteristics of the JFET are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a transistor and a method for manufacturing the same, and more particularly, to a junction-gate field-effect transistor using a compound semiconductor such as Ga.As.
-Transistor: JFET) When manufacturing a semiconductor device having a transistor such as a transistor, a self-alignment (self-alignment) technique and a low-concentration doping (LDD) technique are used to shorten the gate to reduce the gate-drain width and reduce the breakdown voltage. The present invention relates to a method of manufacturing a transistor for improving the short channel effect.

[0002]

2. Description of the Related Art A method for manufacturing a conventional junction gate type field effect transistor (JFET) will be described with reference to FIGS. First step (FIG. 5A): semi-insulating GaAs substrate 1
A shallow and wide n-type channel forming impurity region 101
To form

Second step (FIG. 5B): A gate impurity region 102 of a JFET is formed in an n-type channel forming impurity region 101. Therefore, silicon nitride (S
iN) film is formed, and an aperture 103a is formed in the
An iN diffusion mask 103 is formed. A p-type impurity such as zinc (Zn) is diffused into the semi-insulating GaAs substrate 100 from above the SiN diffusion mask 103 to form the gate impurity region 10.
2 is formed.

Third step (FIG. 5C): Mask film 1 for SiN diffusion on gate impurity region 102 of JFET
The gate electrode 104 is formed so as to be buried in the opening 103a of No. 03. Next, at predetermined intervals on both sides of the gate electrode 104 in the channel direction, openings 103b and 103c are formed in the diffusion mask 103 by using a photolithography technique and an etching technique such as RIE (Reactive Ion Etching). . Ions are implanted by an ion implantation method or the like using a photoresist or the like at the time of forming the openings 103b and 103c as a mask to form high-concentration n-type source impurity regions 105a and n-type drain impurity regions 105b.

The fourth step (FIG. 5D): AuGe / N is applied to the surface of the semi-insulating GaAs substrate 100 exposed in the openings 103b and 103c of the diffusion mask 103.
A laminated metal film i is formed, and the metal film is heated and alloyed with GaAs of the semi-insulating GaAs substrate 100 to form ohmic electrodes 106, 106. After that, when a metal wiring layer is formed on the ohmic electrodes 106 to reduce the resistance, a basic JFET can be formed. In addition,
Source impurity region 105a and drain impurity region 1
05b is omitted, and the channel forming impurity region 101 is formed.
In some cases, an ohmic electrode is directly formed on the substrate.

In the above-described method for manufacturing a JFET,
After forming the gate region, in a third step (FIG. 5)
(C) The source impurity region 105a and the drain impurity region 105b are formed. Therefore, the region between the gate and the drain and between the gate and the source are determined by the overlay accuracy. However, the overlay accuracy is ± 0.1 depending on the photomask alignment accuracy.
There is a disadvantage that the breakdown voltage between the gate and the drain varies, that is, the breakdown voltage of the JFET varies. The degree (%) of the variation in the drain withstand voltage is J
Since the size of the FET becomes relatively large as the size of the FET is miniaturized, JFETs that do not satisfy the drain withstand voltage standard will occur considerably as the miniaturization of JFETs advances in the future.

In the JFET manufactured by the above-described manufacturing method, the gate impurity region 102 and the source impurity region 105a and the gate impurity region 102 and the drain impurity region 105b are both in contact with the surface in the semi-insulating GaAs substrate 100. Since they are formed, both parasitic capacitances (capacitance Cgs between the source and the gate and capacitance Cgd between the drain and the gate) are large, which hinders the improvement of the high-frequency characteristics (high-speed operation) of the JFET.

Contrary to the above-described example, a method of forming a source impurity region and a drain impurity region and then patterning the gate region with a marker used when forming the source impurity region and the drain impurity region can be considered. Also in this case, the same problem as described above is encountered because the region between the gate and the drain and between the gate and the source are determined by the overlay accuracy.

The applicant of the present application has proposed in Japanese Patent Application No. 9-105846 a junction gate type field effect transistor which overcomes the above disadvantages and a method of manufacturing the same. According to this method, it is possible to manufacture a junction gate type field effect transistor having a small variation in drain withstand voltage and excellent in high frequency characteristics. The outline will be described with reference to FIGS.

The junction gate type field effect transistor (JFET) illustrated in FIG. 6 has a projection (protrusion) 201a formed by etching on the surface of a semiconductor substrate 201 such as Si or GaAs. A channel impurity region (gate impurity region) 204 is formed. Projection 20 below channel impurity region 204
1a, a shallow and wide n-type channel forming impurity region 20 is formed.
2 extend. On the protrusion 201a (channel impurity region 204), for example, tungsten silicide (W
A gate electrode 205 made of a refractory metal material such as Si) is formed. High concentration n-type source impurity region 20
The source electrode on 3a and the drain electrode on high-concentration n-type drain impurity region 3b are not illustrated. In addition,
When the semiconductor substrate 201 is GaAs, the source impurity region 203a and the drain impurity region 203b may be omitted.

In the JFET illustrated in FIG. 6, since the bottom surface of the gate impurity region 204 is in contact with the channel forming impurity region 202, no junction capacitance exists on the side surface of the gate impurity region 204, and the gate impurity region 204 and the source impurity region 2
03a and the gate impurity region 204
And the drain impurity region 3b have a very small capacitance. That is, reduction of the gate-source capacitance Cgs and gate-drain capacitance C _gd of the JFET is reduced, thereby improving the high frequency characteristics of the JFET. In addition, most of the gate applied voltage is applied to the depletion layer below the gate impurity region 204, and the pinch-off characteristics of the channel are excellent.
The amount of change of the drain current with respect to the signal applied to the gate, that is, the transconductance gm is improved.

FIG. 7 shows a method of manufacturing the JFET illustrated in FIG.
This will be described with reference to FIGS. 7 (A) to 7 (E) show the JFET on the left side, and the right side shows the etching end point detection pattern prepared for the measurement element group (TEG) in the same substrate as the JFET. In this example, a case where an n-channel type JFET is formed on a GaAs substrate 201 will be described.

First step (FIG. 7A) : semi-insulating G
An aAs substrate 201 is prepared, and an n-type channel formation region 202 is formed on the front side of the GaAs substrate 201.

Second step (FIG. 7B) : The gate impurity region 204 of the JFET is changed to the channel forming impurity region 20.
It is formed on the surface side in the channel formation region 202 shallower than 2. At this time, the p-type impurity region 206 for etching monitoring is also formed simultaneously with the end point detection pattern in the TEG. The pattern size of the gate impurity region 204 may be larger than the gate size of the completed JFET (eg, in the channel direction, the gate length Lg of the gate impurity region 204 in FIG. 6). The gate impurity region 204 needs to be thinned at a high concentration in order to improve the performance of the JFET. In this case, as a suitable forming method, for example, DEZ (Zn (C
A gas phase diffusion method using ₂ H ₅ ) ₂ ) as a diffusion source can be used.

Third step (FIG. 7C) : After forming a high melting point metal film such as WSi by, for example, a sputtering method, a mask layer 207 made of, for example, a photoresist is formed on the high melting point metal film. . This mask layer 207
The gate electrode 205 is formed by etching the lower refractory metal film into a predetermined shape using an etching technique such as RIE using the as an etching mask. The formation position of the gate electrode layer 205 is preferably near the center of the channel forming impurity region 202 or the gate impurity region 204a. The length L in the channel direction is the gate length Lg and the source and drain of the completed JFET shown in FIG. The distance is determined in consideration of the distance LSD between them.

Fourth step (FIG. 7D) : mask layer 2
07 while isotropically etching (over-etching or side-etching) the lower gate electrode 205
Then, an eave by the mask layer 207 is formed by retreating the peripheral edge of the gate electrode 205. As the isotropic etching method, dry etching or wet etching using a predetermined etchant is used. The amount of isotropic etching (eave width d) is determined by the gate length Lg of the gate electrode 205 and affects the distance between the gate electrode 205 and a source impurity region or a drain impurity region formed later.

Fifth step (FIG. 7E ) : The surface of the semiconductor substrate 201 is etched using the gate electrode 205 and the mask layer 207 as an etching mask. The etching of GaAs is isotropically performed using a predetermined etchant such as phosphoric acid and hydrogen peroxide solution. At the time of GaAs etching, the end point detection is performed because the other gate impurity region 204 must be completely etched off except for the portion immediately below the gate electrode 205. Usually, the etching is slightly over-etched in consideration of the variation in the substrate surface of the gate impurity region 204 of the JFET.

Sixth step (FIG. 7F ) : mask layer 2
07 is used as an ion implantation mask, an n-type impurity is ion-implanted at a high concentration, activation annealing is performed after the mask layer 207 is removed, and the source impurity region 203a and the drain impurity region 203b separated on both sides of the gate impurity region 204 in the channel direction. To form

Seventh step (FIG. 7G ) : ohmic electrode 208a and ohmic electrode 208b are formed on source impurity region 203a and drain impurity region 203b.
To form When forming the ohmic electrode 208a and the ohmic electrode 208b, besides the usual method of separately performing mask alignment, a laminated metal film such as Au / GeNi may be formed by, for example, a lift-off method while leaving the mask layer 207. . In any case, after the formation of the laminated metal film, ohmic electrodes 208a and 208b for alloying the laminated metal film and GaAs by performing alloying annealing are obtained. Thus, the basic structure of the JFET is completed. Thereafter, although not shown, the ohmic electrodes 208a, 208b
A first wiring layer for lowering resistance or the like is formed thereon.

According to the above-described method of manufacturing the JFET, since the gate impurity region 204 protrudes from the surface of the semiconductor substrate and the mask layer 207 at the time of formation is left, the source impurity region 203a and the drain impurity region 203 are thereafter formed.
b, and ohmic electrodes 208a and 208b can be formed in a self-aligned manner with respect to the gate impurity region 204. Since the variation in the side etching is much smaller than the variation in the relative position due to the alignment accuracy of the photomask, the variation in the distance can be sufficiently suppressed,
The drain withstand voltage can be made uniform.

Further, the above-described manufacturing method uses the gate electrode 20
Since gate electrode 5 is made thinner by side etching, gate length Lg can be made smaller than the resolution limit width of photolithography. Shorter gate length improves the high frequency characteristics of JFET,
In addition, the uniformity of the drain breakdown voltage contributes to the miniaturization of the JFET.

[0022]

Problems to be Solved by the Invention Japanese Patent Application No. 9-10584
According to the method of manufacturing a JFET disclosed in No. 6, the positioning accuracy between the gate and the drain region is increased, and the JF
The breakdown voltage between the gate and the drain of the ET has been improved. According to the method of manufacturing a JFET disclosed in Japanese Patent Application No. 9-105846, the capacitance Cgs between the source and the gate and the capacitance Cgd between the drain and the gate are reduced.
The high frequency characteristics of the FET have been improved. However, as illustrated in FIG. 6, since the gate impurity region 204 is formed between the channel forming impurity region 202 on the surface of the semiconductor substrate 201 and the gate electrode 205, the height of the gate electrode 205 increases, Is considerably high.

Further, the above-described manufacturing method requires a step of etching off an unnecessary portion of the gate impurity region 204,
The manufacturing method is complicated because it is necessary to electrically monitor the end point detection of the etch-off. In addition, it is necessary to manufacture a circuit for detecting the etch-off.

The present invention is intended to improve the method proposed in Japanese Patent Application No. 9-105846. That is, the object of the present invention is to maintain the gate-drain withstand voltage high, maintain the gate-drain breakdown voltage high and maintain the source-gate capacitance Cgs, as in Japanese Patent Application No. 9-105846. Another object of the present invention is to provide a semiconductor device having a transistor whose structure is simple and easy to manufacture, while keeping the capacitance Cgd between the drain and the gate small and high frequency characteristics high, and a method of manufacturing the same.

[0025]

According to the present invention, Ga is used.
・ Junction-type Field-Effect-Transis using a compound semiconductor such as As
In a semiconductor device having a transistor such as a tor: JFET) and a method for manufacturing the same, the concept is based on a concept of shortening the gate by using a self-alignment (self-alignment) technique and a lightly doped (LDD) technique.

Therefore, according to the present invention, there is provided a method of manufacturing a semiconductor device having a transistor, comprising: (1) forming a first diffusion mask film having a predetermined thickness on a semiconductor substrate; Applying a first resist on the first diffusion mask film, patterning a gate formation region of the transistor, and leaving the first resist film by a predetermined width in the gate formation region of the transistor; (3) isotropically etching the remaining first resist film and the remaining first diffusion mask film so that the width of the first diffusion mask film is greater than the width of the remaining first resist film. (4) implanting ions of the first conductivity type into the semiconductor substrate using the first resist film as a mask, and performing the first diffusion mask; Said on both sides of the membrane Forming a first conductivity type ion implantation region in the semiconductor substrate; (5) removing the first resist film; and (6) using the first diffusion mask film as a dummy gate to form the semiconductor. Further implanting ions of the first conductivity type into the substrate to form a region having a low concentration of ions of the first conductivity type in the semiconductor substrate on both sides of the gate region of the transistor; Forming a second diffusion mask film on the first diffusion mask film used as a dummy gate, and forming the second diffusion mask film until the upper portion of the first diffusion mask film is exposed; (8) removing the first diffusion mask film by selective etching to expose a gate formation region on the surface of the semiconductor substrate; and (9) removing the second diffusion mask film. Using the mask film as a mask, the game And a step of forming a gate region do diffuse the second conductivity type ions in the formation region, a method of manufacturing a semiconductor device having a transistor is provided.

More specifically, the semiconductor substrate is a Group 3-5 compound semiconductor substrate, the transistor is a junction gate type field effect transistor, the first diffusion mask film is a silicon oxide film, The second diffusion mask film is a silicon nitride film, the first conductivity type ions are n ⁺ silicon ions, and the second conductivity type ions diffused into the gate region are p ⁺ silicon ions; A region having a low first conductivity type ion concentration formed from the gate region to the source region and the gate region to the drain region of the semiconductor substrate contains n ⁺ ions and has a high first conductivity type ion concentration. The region contains n ⁺⁺ ions.

According to the present invention, the third conductivity type compound semiconductor substrate is formed by diffusing the second conductivity type ion β ⁺ to a predetermined depth from the surface of the substrate and to a width corresponding to the gate of the transistor. A first conductive type region formed in the semiconductor substrate below the gate region, a first conductive type region deeper than the first conductive type region, A shallow region of the first conductivity type ion α ⁺ formed symmetrically at a predetermined distance from the gate region near both sides of the gate region of the transistor, and a shallow region of the first conductivity type ion α ⁺ There is provided a semiconductor device having a transistor which is formed successively and has a source region and a drain region in a deep region of the first conductivity type ion α ⁺⁺ .

Specifically, the group III-V compound semiconductor substrate includes GaAs, the gate region includes P ⁺ silicon, the first conductivity type region includes n-type silicon, and the first conductivity type region includes n-type silicon. The ion α ⁺ is n ⁺ silicon, and the first conductivity type ion α ⁺⁺ is n ⁺⁺ silicon.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As a preferred embodiment of the present invention, a semiconductor device having a junction gate type field effect transistor (JFET) using a compound semiconductor and a method of manufacturing the same will be described below with reference to the drawings. In the first embodiment of the present invention described with reference to FIG. 1, an n-channel type JFE
Although T is illustrated, it should be noted that the present invention is not limited to the conductivity type of the channel, since the present invention can be applied to a p-channel type JFET. Further, the present invention is not limited only to a junction gate type field effect transistor.

First Embodiment FIG. 1 is a sectional view showing a basic configuration example of a JFET as an embodiment of the present invention. The JFET of the present embodiment illustrated in FIG. 1 has a semiconductor substrate 1 of gallium arsenide (GaAs), which is a typical group III-V (III-V) compound semiconductor, and a p ⁺ constituting a gate region 15 of the JFET. An impurity diffusion region includes an n-type channel forming impurity region 110 located below the gate region 15 and formed inside the GaAs substrate 1. N-type channel forming impurity region 110
On both sides of the low concentration n of the LDD structure having a low ion concentration.
⁺ Type impurity diffusion regions (n ⁺ regions) 111 and 121;
These low-concentration n ⁺ -type impurity diffusion regions (n ⁺ regions) 1
11 and 121 and n-type impurity diffusion regions (n ⁺⁺ regions) 112 and 122 having a high ion concentration which are continuous with each other are formed. The high-concentration n-type impurity regions 112 and 122 function as a source region and a drain region of the JFET, respectively. On the surface of the GaAs substrate 1 on both sides of the gate region, SiN films 5 are provided.

The JFET illustrated in FIG.
5 has contact surfaces with low-concentration n ⁺ -type impurity diffusion regions (n ⁺ regions) 111 and 121 at the bottom surface, so that there is no junction capacitance on the side surface of gate region 15, so that gate region 15 and source region 1
12 and the capacitance between the gate region 15 and the drain region 122 have extremely small values.
That is, the capacitance Cgs between the gate and the source and the capacitance Cgd between the gate and the drain of the JFET are reduced.
The high frequency characteristics of the JFET are improved. Also, the gate region 15
Most of the gate applied voltage applied to the gate region 1
5 depletion layer (n-type channel forming impurity region 11)
0), the pinch-off characteristics of the channel are excellent, and the amount of change in the drain current with respect to the signal applied to the gate, that is, the mutual conductance gm is improved.

FIGS. 2A to 2D and 3E to 3H.
4 (I) to 4 (J) are diagrams illustrating a method of manufacturing the JFET illustrated in FIG.

First step : As illustrated in FIG. 2A, a silicon dioxide insulating film (SiO ₂ film) 2 is formed on the entire surface of the GaAs substrate 1 as a first insulating film for a mask, for example, by a plasma method. I do. The thickness of the plasma SiO ₂ film 2 is 0.6 μm in this embodiment. The reason why the SiO ₂ film 2 is used as the first mask insulating film is as follows.
In a step after forming the source region and the drain region of the FET, n ⁺ -type silicon is used as the first conductivity type ion by Ga.
This is because it is suitable as a selection mask when implanting into the As substrate 1 by the ion implantation method. When a method other than the ion implantation method is used for forming the source region and the drain region, for example, when an epitaxial growth method or a method combining the ion implantation method and the epitaxial growth method is used, an epitaxial growth method is used as a selective mask. In this case, an insulating film such as a silicon nitride (SiN) film is preferable, and a photoresist or the like can be used as another method.

Second step: As illustrated in FIG. 2A, a resist is applied on the SiO ₂ film 2 and further patterned to leave a resist film 3 in a portion to be a dummy gate in a subsequent process. . The thickness of the resist film 3 is
In this embodiment, it is 0.4 μm. The plane area of the resist film 3 left after patterning is set to be larger than the width of the gate of the JFET. The reason is to effectively form an LDD structure to be formed in a later step. The details will be described later.

Third step : As illustrated in FIG. 2B, the SiO ₂ film 2 is formed using an acid chemical (SO-1) or CF ₄ gas-based reactive ion etching (RIE) system. Etching in the direction. Due to the over-etching of the SiO ₂ film 2 by this isotropic etching,
The SiO ₂ film 2 around the lower part of the resist film 3 is
Etching is made narrower, and the dummy gate width becomes shorter. As a result, the etched SiO ₂ film 2 and the resist film 3 thereon have a shape like a “mushroom umbrella”. The dummy gate width defines the gate width of the transistor.

Fourth step : As illustrated in FIG. 2C, ions of the first conductivity type n ⁺ are implanted from above the GaAs substrate 1. The resist film 3 and the SiO ₂ film 2 serve as a mask for ion implantation. By the first ion implantation of the first conductivity type n ⁺ , impurity diffusion regions 11 and 12 are formed inside the GaAs substrate 1. The first in this embodiment
The conductivity type ions are n ⁺ silicon ions. Part of these impurity diffusion regions 11 and 12 (regions with high ion concentration (n ⁺⁺ regions) 112 and 122) will be JF
The source region and the drain region of the ET are formed. Note that the area of the resist film 3 is the same as that of the SiO ₂ film 2 left by the isotropic etching.
Since it is wider, the impurity diffusion region 11 of the first conductivity type n ⁺
(Low concentration n ⁺ -type impurity diffusion region (n ⁺ region) 11
1) and the planar distance between the end of the SiO ₂ film 2 opposed thereto and the first conductive type n ⁺ impurity diffusion region 11 (low-concentration n ⁺ impurity diffusion region (n ⁺ Area) 1
The planar distance between the end of 21) and the end of the SiO ₂ film 2 facing the end is, respectively, the resist film 3 and the S
It is separated by a distance Δd corresponding to the difference in length from the iO ₂ film 2. This distance Δd is equal to the distance between the resist film 3 and SiO _2.
It can be defined by the etching amount of the SiO ₂ film 2 by the isotropic etching condition of the film 2.

Fifth step : As illustrated in FIG. 2D, the resist film 3 on the SiO ₂ film 2 is removed. As a result, in a later step, the source region 11 of the JFET is
2 and impurity diffusion region 1 serving as drain region 122
SiO ₂ film 2 used as a dummy gate as a diffusion mask when impurities are further diffused into portions 1 and 12
Are exposed on the surface of the GaAs substrate 1.

Sixth step : As illustrated in FIG. 3E, ion implantation of the first conductivity type n ⁺ is performed on the entire surface of the GaAs substrate 1 using the SiO ₂ film 2 left by etching as a dummy gate. . The first conductivity type ions in the present embodiment are n ⁺ silicon ions. By the second ion implantation of the first conductivity type n ⁺ , impurity diffusion regions 11 and 1 are formed.
2 are separated from the low-concentration n ⁺ -type impurity diffusion regions (n ⁺ regions) 111 and 121 in accordance with the degree of ion implantation, respectively, as the distance from the dummy gate is increased, or in other words, regions with high ion concentration (n ^++). (Areas) 112 and 122. An n-type channel forming impurity region 110 is formed below the SiO ₂ film 2. Ion concentration thin region (n ⁺ region) 121, after the gate regions 15 are formed under the SiO ₂ film 2 at step, after the step ion-enriched region (n ⁺⁺ region to be a drain region ) 122 to form an LDD (lightly Doped Drain) structure. Regions with high ion concentration (n ⁺⁺ regions) 112, 122
Are the drain and source regions of the JFET, respectively.

Seventh step : As illustrated in FIG. 3F, an SiN film 4 is formed by depositing silicon nitride (SiN) over the SiO ₂ film 2 used as a dummy gate. In this embodiment, the thickness of the SiN film 4 is 0.4 μm. The reason for forming the SiN film 4 is that when a p-type impurity such as zinc (Zn) is diffused into the GaAs substrate 1 in a later step to form a gate impurity region, the SiN film 4 is used as a mask for the diffusion. It is. Therefore, when the diffusion method for forming the gate impurity region is different from the above, a film suitable for the diffusion method is used instead of the SiN film 4.

Eighth step : As illustrated in FIG. 3 (G), a resist is applied on the SiN film 4 and further heat-treated to flatten the resist, thereby forming a resist layer 5 having a flat upper portion. The thickness of the resist layer 5 is 0.6 in this embodiment.
μm.

Ninth step : As illustrated in FIG. 3H, an acid chemical (SO-1) or CF ₄ gas-based reactive ion etching (RIE) system is used.
The resist layer 5 is isotropically etched under the condition that the selectivity between the resist layer 5 and the SiN film 4 is 1. As a result, GaAs
SiN film 4 having substantially the same thickness as SiO ₂ film 2 on substrate 1
Remains.

Tenth step : As illustrated in FIG. 4I, an acid chemical (SO-
The wet etching is performed in 1) to remove the SiO ₂ film 2 used as the dummy gate, thereby exposing the surface portion 21 of the GaAs substrate 1 which will be the gate region below the SiO ₂ film 2.

Eleventh step : As illustrated in FIG. 4J, the GaAs substrate 1 exposed by removing the SiO ₂ film 2
The second conductivity type ions such as _Zn diffusion and p ⁺ silicon ions are diffused into the gate region 15 of the transistor inside the GaAs substrate 1 below the surface portion 21 to form the gate region 15 of the transistor. Gate region 15 is JF
In order to improve the performance of ET, it is necessary to reduce the concentration of the ET. DEZ (Zn (C ₂ H
₅ ) A gas phase diffusion method using ₂ ) as a diffusion source is preferred. Specifically, a gate region is formed by thermally diffusing a p-type impurity such as zinc (Zn) into the gate region 15 of the GaAs substrate 1 by a gas phase diffusion method.

Twelfth step : Thereafter, the gate region 15
Then, for example, a gate electrode made of a laminated metal film of Ti / Pt / Au is formed. Further, a laminated metal film of AuGe / Ni is formed on the surface of the GaAs substrate 1, and this metal film is heated and alloyed with GaAs of the GaAs substrate 1 to form an ohmic electrode (not shown). Thereafter, when a metal wiring layer is formed on the ohmic electrode to reduce the resistance, a basic JFET can be formed.

As described above, a basic JFET was formed. Formation of electrode connected to gate region, source region 1
The connection of the electrodes to the drain region 122 and the drain region 122, and the manufacture of the semiconductor device having this JFET are the same as those described in the prior art with reference to FIGS. is there.

Effects of the First Embodiment As described above, the method of manufacturing the JFET of the present embodiment is simpler than the method described with reference to FIGS. 5A to 5G. . For example, the work of etching off the GaAs substrate 1 is not required, and an inspection circuit therefor is not required. In the JFET of the present embodiment, the drain region 122 and the source region 112 near the gate region 15 are formed in a self-aligned manner (in a self-aligned manner). In particular, since the low impurity concentration region 121 having the LDD structure is formed between the gate region 15 and the drain region 122,
The withstand voltage is improved, and the short channel effect of the JFET can be prevented. In addition, the gate / drain width is increased by shortening the gate length, and the short channel effect is improved. Further, since the gate electrode of the JFET of the present embodiment does not have the protrusion of the gate electrode portion shown in FIG. 5, the side wall of the gate electrode does not increase.

Other Embodiments In the above-described first embodiment, an example was shown in which a typical GaAs substrate 1 was used as a compound semiconductor substrate as a group III-V compound semiconductor. The present invention can be applied to a Group 3-5 compound semiconductor or a compound semiconductor other than Group 3-5.

[0049]

According to the present invention, the structure is simple based on the concept of shortening the gate by using the self-alignment (self-alignment) technique and the low concentration doping (LDD) technique.
A semiconductor device having a transistor with an increased gate / drain width, improved withstand voltage, and improved short channel effect has been provided.

According to the manufacturing method of the present invention, a transistor having the above characteristics can be manufactured by a relatively simple method.

[Brief description of the drawings]

FIG. 1 shows a JF as a first embodiment of the present invention.
It is sectional drawing which shows the basic structure of ET.

FIGS. 2A to 2D are JFs illustrated in FIG.
It is a figure showing the manufacturing method (the 1st part) of ET.

3 (E) to 3 (G) show JF illustrated in FIG. 1;
It is a figure showing the manufacturing method (the 1st part) of ET.

4 (I) to 4 (J) are JFs illustrated in FIG.
It is a figure showing the manufacturing method (the 3rd part) of ET.

FIGS. 5A to 4D are views showing a conventional method for manufacturing a JFET.

FIG. 6 is a sectional view of a JFET as a prior art of the present invention.

7 (A) to 7 (D) show JF illustrated in FIG. 5;
It is a figure showing the manufacturing method of ET.

[Explanation of symbols]

1. GaAs substrate 11, 12 impurity diffusion region 110 n-type channel forming impurity region 111, 121 low concentration impurity diffusion region (n ⁺ region) 112, 122 high impurity concentration diffusion region (n ⁺⁺⁾ Region) 112 source region 122 drain region 15 gate region 2 SiO ₂ film (first diffusion mask film) 3 first resist film 4 SiN film (second diffusion) Mask film) 5. Second resist layer

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device having a transistor, comprising: forming a first diffusion mask film having a predetermined thickness on a semiconductor substrate; and forming a first diffusion mask film on the first diffusion mask film. Applying a first resist, patterning a gate formation region of the transistor, and leaving the first resist film by a predetermined width in the gate formation region of the transistor; The remaining first diffusion mask film is isotropically etched, and the width of the first diffusion mask film is smaller than that of the remaining first resist film,
And a step of narrowing the gate width to the same as the gate width of the transistor; and implanting ions of the first conductivity type into the semiconductor substrate using the first resist film as a mask. Forming a first conductivity type ion-implanted region in the semiconductor substrate; removing the first resist film; and using the first diffusion mask film as a dummy gate in the semiconductor substrate. Further forming a region from a region where the concentration of the first conductivity type ions is low to a high concentration in the semiconductor substrate on both sides of the gate region of the transistor; and forming the first region used as the dummy gate. Forming a second diffusion mask film on the diffusion mask film, and removing the second diffusion mask film until the upper portion of the first diffusion mask film is exposed; Removing the first diffusion mask film by selective etching to expose a gate formation region on the surface of the semiconductor substrate; and using the second diffusion mask film as a mask, forming a second gate formation region on the semiconductor substrate. Forming a gate region by diffusing conductive ions. 2. The semiconductor substrate is a group 3-5 compound semiconductor substrate; the transistor is a junction gate field effect transistor; the first diffusion mask film is a silicon oxide film; The diffusion mask film is a silicon nitride film, the first conductivity type ions are n ⁺ ions, and the second conductivity type ions diffused into the gate region are p ⁺ ions. From the source region and the gate region to the drain region, the region having a low ion concentration of the first conductivity type is n.
^{2. The} method for manufacturing a semiconductor device having a transistor according to claim 1, wherein the region containing the ⁺ ions and the region where the ion concentration of the first conductivity type is high contains n ⁺⁺ ions. 3. A group III-V compound semiconductor substrate, and a gate region formed by diffusing the second conductivity type ion β ⁺ to a predetermined depth from the surface of the substrate and to a width corresponding to the gate of the transistor. A region of a first conductivity type formed in the semiconductor substrate below the gate region; and a gate of the transistor in the substrate, the region being deeper than the region of the first conductivity type and continuing to the first conductivity type region. It is formed continuously on both sides of the gate region and the first conductivity type ions alpha ⁺ shallow region formed symmetrically at a predetermined distance, the first conductive type ion alpha ⁺ shallow region in the vicinity of the region first A semiconductor device having a transistor having a source region and a drain region in a deep region of one conductivity type ion α ⁺⁺ . 4. The semiconductor device according to claim 1, wherein said substrate is a GaAs compound semiconductor.
Wherein the second conductivity type ion β ⁺ diffused into the gate region is p
A ^+, the region of the first conductivity type is n-type, the first conductivity type ions alpha ⁺ is n ^+, the first conductive type ion alpha ⁺⁺ is claim 3 wherein the n ⁺⁺ Semiconductor device having the transistor of FIG.