JPH1154454A - Low temperature formation of low resistivity titanium silicide - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an improved method for forming a C54 phase titanium silicide without requiring a second high-temperature annealing. SOLUTION: A low resistivity titanium silicide and semiconductor devices incorporating the same are formed by a titanium alloy comprising titanium and 1-20 atom percent refractory metal deposited in a layer overlying a silicon substrate. The substrate is then heated to a temperature which is sufficient to practically form a C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, but more preferably be Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900 deg.C, and more preferably between about 600 to 700 deg.C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to a method for forming a titanium silicide layer on a silicon layer of an integrated circuit device whose phase transition temperature is reduced by using a refractory metal.

[0002]

BACKGROUND OF THE INVENTION Titanium silicide has become widely used in the VLSI industry for self-aligned silicide applications because of its combination of low resistance, self-aligned features, and relatively good thermal stability characteristics. I have. TiSi ₂
Although they have advantages over other silicides, they add to the problem of use because of their polymorphic nature. Specifically, TiSi ₂ typically has 12 atoms per unit cell and a resistance of about 60 microohm cm to 90 microohm cm.
Orthorhombic bottom core phase (called C49 phase), or 24 atoms per unit cell, with a resistance of about 12 microohm cm to 2
It exists in any of the thermodynamically stable orthorhombic core phases (called C54 phase) of 0 microohm cm. When forming titanium silicide, under generally accepted processing conditions, less desirable high resistance C4
Nine phases are formed first. To obtain a low-resistance C54 phase, a second high-temperature annealing process is required. This second process can have a negative effect on silicide and other integrated circuit elements, especially when the line width is relatively narrow. For example, increasing the use of a double-doped polysilicon gate structure in multiple devices will increase the response to the heating cycle required for the second anneal.
In addition, peeling and cracking of silicon nitride are related to the second annealing treatment.

A group of processing conditions generally accepted for forming titanium silicide includes (1) pre-cleaning,
(2) titanium deposition, (3) silicide formation below about 700 ° C., (4) selective etching, and (5) about 700
This is a phase transition annealing at a temperature of not less than ° C. C to dominant C49 phase
It is phase transition annealing that converts to 54 phases. Initial formation temperature is over-spacer br
It is kept below 700 ° C. to minimize idging).
The second transition anneal is performed after the unreacted titanium has been selectively removed, and is generally controlled to provide a complete transition to the C54 phase for optimal control of sheet resistance.
It is performed at a temperature of 50 ° C. to 200 ° C. higher than the forming temperature. However, since the line width of the element and the film thickness of the silicide continue to be reduced in scale, it is more required than before to eliminate the second annealing treatment as described later.

[0004] The C49 phase is initially formed because the surface energy is lower than the C54 phase. In other words, the high surface energy of the C54 phase increases the energy barrier that prevents its formation. The second transition anneal, used in the previous standard process, is necessary to overcome the nucleation barriers associated with the formation of new surfaces and to grow the crystal structure of the newly formed C54 phase. Heating energy is obtained. In the case of VLSI applications, if the phase transition is suppressed or does not occur uniformly, degradation of circuit performance is observed. For higher performance circuits, the RC delay associated with poor phase transition is typically about 5% to 1%.
0%.

[0005] A major constraint on the phase transition from C49 to C54 is a phenomenon called agglomeration. If the thermal energy used to cause the phase transition is excessive, morphological deterioration of titanium silicide occurs. This is generally called agglomeration. As the line width and silicide thickness decrease, the thermal energy required for the C49 to C54 phase transition increases, but the thermal energy level at which the silicide film agglomerates decreases.
Therefore, the margin of processing for causing this phase transition is being reduced.

[0006]

Accordingly, there is a need for an improved method of forming a C54 phase titanium silicide that does not require a second high temperature anneal as in the generally accepted process described above. Can be Eliminating the second anneal or lowering the temperature required to convert the C49 phase titanium silicide to the desired C54 phase titanium silicide reduces the problems associated with high temperature processing and during the phase transition anneal. In addition, restrictions caused by agglomeration of the silicide film are reduced.

[0007]

SUMMARY OF THE INVENTION This need is met, in accordance with the principles of the present invention, by a method of forming a metal silicide on a silicon layer on a semiconductor wafer, which overcomes the limitations of the prior art and further reduces the need. Is also realized. In this method, a titanium silicide layer is formed on a silicon substrate of a semiconductor device. The method includes the steps of (1) depositing a titanium alloy layer comprising a refractory metal at an atomic percentage of 1 to 20 on a silicon substrate; and (2) substantially depositing a C54 layer.
Heating the titanium alloy to a sufficient temperature to form a phase titanium silicide. The temperature is about 70
It is below 0 ° C.

In one embodiment of the above method, the titanium alloy comprises a refractory metal having an atomic percentage of 1 to 15, wherein the refractory metal comprises Ta, Nb, Mo, W, V, and Cr.
It contains one or more groups. Titanium alloys include those containing titanium, silicon, and metal, such as TiS
i ₂ and the refractory metal is considered. The semiconductor substrate is made of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium alloy, SO containing N-type dopant.
It can be selected from I (silicon-on-insulator) and SOI containing a P-type dopant. Titanium alloys can be deposited on silicon substrates by physical or chemical vapor deposition.

[0009] Another embodiment of the present invention is a semiconductor device having a C54 phase titanium silicide layer. This consists of (1) a silicon layer, and (2) a titanium layer on the silicon layer.
A silicide layer, wherein the titanium silicide layer substantially comprises a C54 phase titanium silicide and an atomic percentage of 1-2.
Contains 0 refractory metals. Other aspects of the semiconductor device of the present invention include monocrystalline silicon, polycrystalline silicon, and amorphous silicon.
Silicon, silicon-germanium alloy, SOI with N-type dopant, and SOI with P-type dopant
Is a silicon layer selected from the group of. The semiconductor element of the present invention can contain a refractory metal with an atomic percentage of 1 to 15 and can have a titanium silicide layer with a thickness of 10 to 200 nm.

[0010]

DETAILED DESCRIPTION OF THE INVENTION According to one embodiment of the present invention,
A refractory metal is deposited in close proximity to the surface of the silicon layer, and a layer of titanium metal (to be used later to form titanium silicide) is deposited over the refractory metal to form a titanium silicide. The wafer is heated to a sufficient temperature.

In a second embodiment, silicon can be introduced into the titanium metal layer, for example, as in a conventional polycide process. When introducing silicon into the titanium metal layer, the final titanium silicide heats the wafer to a temperature sufficient to obtain the desired solid phase following the deposition of a Ti silicon alloy (possibly in a chemical formula). Obtained by: In addition to Si, B,
C, N, O, Al, P, S, Zn, Ga, Ge, As,
Se, Cd, In, Sn, Sb, Te, Hg, Tl, P
b, and a group of the periodic table including Bi, IIB, IIIA,
Other elements can be added from IVA, VA, and VIA.

The refractory metal is preferably a metal capable of forming a metal silicide, and the concentration of the refractory metal at the surface of the silicon layer is preferably greater than about 10 ¹⁷ atoms / cm ³ . The refractory metal is Mo, W, Ta, Nb, V, Cr, or the like. The silicon layer is monocrystalline or polycrystalline, but is preferably polycrystalline. The heating step to form the silicide is performed at less than about 700C, preferably between about 600C and 700C.

There are several methods of treating refractory metals that can be used. Generally, such treatment methods add refractory metal atoms to surfaces of a few Angstroms, for example surfaces within about 2 Angstroms. A first method for treating refractory metals is from about 10 ¹² atoms / cm ^{2 to} 5 × 10 ¹⁴ atoms / cm ² ,
More preferably, about 10 ¹³ atoms / cm ^{2 to} 10 ⁴ atoms / cm
² is ion implantation. A preferred implantation energy is about 15
KeV to 90 KeV. In another method, the refractory metal is deposited on the surface of the silicon layer, for example, by vapor deposition of metal pellets. Further, the refractory metal is deposited on the surface of the silicon layer by sputtering or by immersing the surface of the silicon layer in a solution containing ions of the refractory metal. For example, the solution is a dilute acidic solution containing HCl or nitric acid. Except for implantation, in all of these treatment methods, the thickness of the refractory metal layer deposited on the silicon surface is preferably less than about 2.0 nm, more preferably about 0.01 nm.
To 1.5 nm.

[0014] Optionally, the wafer is annealed following the step of processing the refractory metal and before the step of processing the precursor metal layer. This anneal is preferably performed at a wafer temperature of at least about 900 ° C, more preferably between about 900 ° C and 1000 ° C. In one way,
This anneal is performed by rapid thermal anneal (RTA) for at least about 5 seconds. In the furnace at least about 1
Annealing treatment can be performed for 0 minutes.

In another method of the present invention, a titanium silicide layer is formed on a silicon layer on a semiconductor wafer.
According to this method, a refractory metal is deposited near the surface of the silicon layer, a titanium layer is deposited on the refractory metal, and the wafer is sufficient to form a titanium silicide layer, at least in part, from the titanium layer. Heated to a suitable temperature. Titanium silicide layer formed during this heating step is preferably shows a C54 phase substantially TiSi _2. The titanium layer is preferably deposited to a thickness of about 25 nm to 57.5 nm, and the TiSi ₂ layer is formed at less than about 700 ° C, more preferably at about 600 ° C to 700 ° C. The refractory metal is preferably Mo, W, Ta, Nb, V, or W, and is preferably deposited by ion implantation or metal deposition. For Mo, Ta, and Nb, it has been found that an optimum result is obtained even when compared to W. The ion implantation is preferably performed at a dose of about 10 ¹³ atoms / cm ^{2 to} 10 ¹⁴ atoms / cm ^2.
Done in Preferably, any of the above-described annealing treatments is performed.

In another embodiment according to the invention, a step of depositing a layer of titanium containing a small amount of refractory metal on a layer above the silicon layer on the semiconductor wafer and sufficient to form titanium silicide. A metal silicide is formed by a method including a step of heating a wafer to an appropriate temperature. The phase transition temperature of titanium silicide from C49 to C54 is
It is reduced by the presence of the refractory metal on the surface of the silicon layer. Titanium and the refractory metal are preferably deposited in the same process, with the atomic percentage of the source refractory metal layer being less than about 20, preferably 1 to 15.

In a preferred method according to another embodiment, the titanium layer is deposited from a source of titanium, which also contains a small amount of refractory metal. The wafer is then heated to a temperature sufficient to form substantially C54 phase titanium silicide. The temperature is preferably less than about 700 ° C and the atomic percentage of the refractory metal is less than about 20.

An advantage of the present invention is that the phase transition anneal is eliminated. For example, with respect to titanium silicide, the desired C54 phase is formed substantially directly during the titanium silicide formation step. TiSi ₂ to C49
A second phase transition anneal is not required to transform from to the C54 phase. Since the processing temperature of the titanium silicide film is low, agglomeration is substantially eliminated. Another advantage of the present invention is that the controllability of the microstructure of the final C54 phase silicide film is improved, and the small particle size of the C54 phase is smaller than the critical dimensions of the device to be fabricated.

One embodiment of the refractory metal is deposited near the surface of the silicon layer, and a titanium layer is deposited on the refractory metal and the silicon surface. Next, the wafer is heated at about 600 ° C. to
Heat to a temperature of 00 ° C. for a time sufficient to form C54 phase titanium silicide.

Referring specifically to FIG. 1, a silicon layer 10 is provided which is a single crystal silicon wafer (100) or polycrystalline silicon. The silicon layer 10 is, for example, a polycrystalline N-type or P-type line, or a single-crystal N-type or P-type region. The refractory metal is deposited on or near the upper surface 12 of the silicon layer 10, depending in part on the processing method. It is believed that the refractory metal acts to reduce the surface energy barrier because it forms C54 phase TiSi ₂ , and therefore the presence of the refractory metal on or near the surface promotes the formation of the C54 phase. It is considered that the alloy of the refractory metal and silicon is formed near the upper surface 12. It is not known for sure whether this is a metal-silicon composite or a metal-silicon compound. In general, some of the deposited refractory metal will be within the upper surface 12 or several Angstroms thereof. Of course, the exact placement of the refractory metal atoms depends on the method of deposition. However, for the purposes of this application, each of the deposition methods described herein is considered to treat refractory metal atoms near the silicon surface.

Referring now to FIG. The refractory metal 14 is shown near the surface of the silicon layer 10. First, it should be understood that FIG. 2 is shown only for convenience of explanation, and that the refractory metal 14 does not necessarily cover the entire top surface 12. Second, it should be noted that the distribution of the refractory metal 14 also depends on the method of deposition. For example, if the refractory metal 14 is deposited by ion implantation, most of the metal will be below the top surface 12. On the other hand, if the metal is deposited by evaporation, most of the metal will be deposited on top 12 rather than below.
For both ion implantation and vapor deposition, the surface energy of C54 phase
It is considered that the barrier is reduced by the concentration of the refractory metal near the upper surface 12. After the refractory metal 14 has been deposited, a titanium layer 16 is deposited on the refractory metal 14, for example by sputtering or vapor deposition. The thickness is, for example, 25 nm to 5
It is 7.5 nm, but thicknesses above and below it are also possible, as will be appreciated by those skilled in the art. Since the position of the upper surface 12 changes depending on the method of depositing the refractory metal used,
It is not explicitly shown in FIG.

The titanium layer 16 can be deposited on the refractory metal 14 by chemical vapor deposition in addition to sputtering and vapor deposition. Also, when deposited by one of these methods, a layer comprising an alloy of Ti and Si may be deposited substantially in place of the titanium layer. The alloy may be stoichiometric TiSi ₂ , but is not a requirement,
The alloy of i and Si has either a high or low silicon content. When an alloy of TiSi is deposited, the method according to the invention is substantially similar to the method described herein. Those skilled in the art will understand what modifications are required. Also, the deposition of a titanium layer, as referred to herein, may be referred to as the deposition of a titanium-silicon alloy layer.

Referring to FIG. A TiSi ₂ film 18 is formed on the silicon layer 10 by heating the silicon layer 10 from about 600 ° C. to 700 ° C. for a time sufficient to form C54 phase TiSi ₂ . This time is typically from about 20 seconds for RTA to about 20 minutes for annealing in a conventional furnace. According to the method of the present invention, T
It is considered that forming the iSi ₂ film does not substantially pass through the C49 phase, but basically reaches the C54 phase directly because the surface energy barrier is reduced.

An optional annealing treatment is performed by using TiS of C54 phase.
Furthermore the formation of i ₂ has been found to be beneficial in promoting. This is particularly beneficial when forming silicides at low temperatures, for example, around 650 ° C. This optional anneal is performed after the refractory metal 14 is deposited and before the Ti layer 16 is deposited. Generally, this anneal is performed at a wafer temperature of at least about 900 ° C, more preferably 900 ° C to 1000 ° C, and at least about 5
Seconds, typically about 10 to 30 minutes when using a conventional quartz furnace. A preferred anneal is performed in a furnace at about 900 ° C. for about 10 minutes in a N ₂ atmosphere. It is believed that this optional anneal may further promote the formation of an alloy of refractory metal and silicon at the surface of the silicon layer, but is not certain.

In general, the refractory metal according to the method of the present invention can be any metal capable of forming a metal silicide. "
"Refractory metal" means, for the purposes herein, Mo, V, W,
It is defined to include a suitable metal of Ta, Nb, or Cr. Ta and Nb are the most effective. These metals are generally considered to correspond to any of the deposition methods disclosed herein, but may include Mo, Ta, or N 2.
The ion implantation and deposition of b are preferred.

The above silicidation process will now be described in detail. There are several methods of depositing a refractory metal that can be used. Generally, these deposition methods place the refractory metal atoms on top surface 12 or within a few Angstroms. The refractory metal atom closest to the silicon interface is considered to be the most active, but other, more distant atoms are not excluded from the meaning of "close" here. For example, the activity of atoms within about 2 angstroms (ie, about 0.2 nm) of the surface will be greatest. The first method of depositing a refractory metal is from about 10 ¹² atoms / cm ^{2 to} 5 × 10 ¹⁴ atoms / cm ² , more preferably from about 10 ¹³ atoms / cm ^{2 to} 10 ^14.
This is ion implantation of atoms / cm ² . In that case, the preferred implantation energy is between about 15 KeV and 90 KeV.

One method of implanting a refractory metal uses an arc chamber of a commonly available ion implanter. Since arc chambers are typically made of refractory metals (molybdenum, niobium, tantalum, tungsten, etc.) or otherwise lined with refractory metals, one method of injecting these metals is By using an arc chamber as the source of The metal species to be implanted is changed appropriately in the arc chamber material and the magnetic analyzer is adjusted to select the desired atomic mass unit (AMU) of the metal species based on the known isotope of the desired species. Selected by you. For example, suitable settings are 98 AMU for Mo and 184 for W. W is also the source filament of the implanter, which is also a normal filament material, so that the analyzer magnet is
184 AMU for charged ion W and 92 for divalent ion W
By adjusting to the AMU, W can be implanted instead. The implant dose and energy chosen for a given metal species is limited by the capabilities of the ion implanter and the time spent in the implant.

In the case of specifically injecting Mo, a Mo arc chamber is installed in the injection device, and a boron trifluoride source gas (BF ₃ ) is introduced into the arc chamber. The ionized BF ₃ serves to volatilize the molybdenum from the arc chamber and provides a suitable Mo ion (98Mo +) beam current of about 200 mA and at least about 45K.
It is believed to provide an implant energy of eV. Since the arc chamber is often coated with other materials when used in other conventional applications, preferably a clean or new source chamber provides Mo ion beam current.

The above conditions (ie, energy of 45 KeV)
When implanting Mo atoms underneath, about 30n of the silicon layer
It has been confirmed that the Mo atom concentration becomes maximum at a depth of m. This corresponds to a peak Mo concentration of about 10 ¹⁹ atoms / cm ² . However, as described above, the Mo atom concentration, which is the biggest problem here, is that at the surface. In the case of the above-mentioned arbitrary annealing treatment, when looking at the SIMS data, the Mo atom concentration on the surface is about 5 × 10 ¹⁸ atoms / cm ² .
A surface concentration of the refractory metal at the silicon interface of about 10 ¹⁷ atoms / cm ² would be desirable.

In another method, the refractory metal is deposited on the surface of the silicon layer, for example, by vapor deposition of metal pellets. This may be by, for example, electron beam evaporation or resistance heating (eg, placing the pellet in a crucible heated by a large current). In the case of vapor deposition, it is important not to make the refractory metal too thick. For example, the thickness of the Mo layer deposited on the silicon layer is:
Preferably it is less than about 2.0 nm. This is not the maximum absolute thickness, and when the thickness of the Mo layer is larger than about 2.0 nm, peeling of the silicide film has been observed. More preferably, the thickness of Mo is between about 0.01 nm and 1.5 nm. The desired thickness of other metals may vary somewhat.

When depositing such a thin refractory metal on a silicon layer, it is often not easy to control the deposition rate. Thus, in some deposition methods, a shutter is placed over the chamber of the deposition metal source to hold the refractory metal until it is ready for deposition on the silicon layer. The opening and closing of the shutter is then performed very quickly (so-called "flash" deposition), and a thin refractory metal layer is formed on the silicon layer. Other vapor deposition methods are also used to improve control of the vapor deposition rate.

As another method of depositing the refractory metal, the refractory metal can be deposited to a certain thickness by sputtering on a silicon layer similar to that described above for deposition. Variations on the sputtering method will be understood by those skilled in the art.

In addition to the above, the refractory metal can be applied to the silicon layer by immersing the surface of the silicon layer in a solution containing ions of the refractory metal. In a preferred method, the solution is aqueous and contains a dilute acid such as HCl or nitric acid.

With respect to the TiSi ₂ method described above, the wafer is optionally annealed after the step of treating the refractory metal and before the step of depositing the titanium layer. This annealing treatment is preferably performed at a wafer temperature of at least 900 ° C.
More preferably, it is performed at about 900 ° C. to 1000 ° C.

FIGS. 4 to 9 show experimental data of a plurality of TiSi ₂ films formed according to the present invention. FIG. 4 is a diagram of the sheet resistance of the titanium silicide layer and the sputtered titanium thickness with and without the use of a refractory metal according to the present invention in a number of process examples. The data indicated as a standard film was formed without the use of a refractory metal and without a second phase transition anneal. According to the present invention, the TiSi ₂ film corresponding to the data point of W, and the data of Mo were formed on (100) single crystal silicon at 600 ° C.
It was formed by annealing for 30 minutes. Refractory metals (W and M
o used for both) at 1000 ° C for 5 seconds
TA annealing was performed. Optional annealing is performed on TiSi
₂ Necessary when the film is formed at about 600 ° C., but not when the formation temperature is about 700 ° C. The sheet resistance of each film is shown by the data points in the figure.

FIGS. 5 through 7 are in-situ scanned resistance diagrams for a plurality of process examples, with and without the use of a refractory metal deposited in accordance with the present invention.
4 shows the sheet resistance of the formed titanium silicide layer.
The measurement was performed by setting the four-point probe continuously in the furnace during the formation of the TiSi ₂ film. The refractory metals of FIGS. 5-7, when used, were deposited by the "flash" deposition described above. FIG. 8 is a diagram of the resistance of the TiSi ₂ film scanned in place. Here, an injected refractory metal was used instead of vapor deposition. 5 to 8 include the formation of a silicide film from an approximately 57.5 nm thick Ti layer previously deposited on an approximately 300 nm polysilicon layer. Each of the silicide films is
It was formed by gradually increasing the temperature at about 15 ° C. per minute.

Referring to FIG. Curve 30 shows the sheet resistance behavior for a titanium silicide film formed without using a refractory metal. It can be seen from curve 30 that there is a known and expected increase in resistance. This is about point 32
By mixing at Curve 30 peaks at about 500 ° C. Above about 500 ° C., the resistance decreases as indicated by arrow 34. When the temperature rises from about 500 ° C. to about 700 ° C., the formed TiSi ₂ film becomes substantially C49 phase. At about 700 ° C., the curve 30 flattens and at point 36 becomes a so-called “knee”. Here, the resistance becomes substantially constant with increasing temperature. This "knee" is due to the silicide film not transitioning from the C49 phase to the C54 phase until a higher temperature is reached. In contrast to curve 30, curve 4
0 indicates the resistance of the silicide film formed after approximately 0.015 nm of Mo has been deposited according to the present invention. The behavior is similar, but the "knee" observed for curve 30 is
It is virtually absent in curve 40 (see point 42). The absence of this knee is believed to indicate that during the silicidation, the C54 phase of TiSi ₂ was formed directly to a significant extent without passing through the C49 phase.

The curve 50 in FIG. 6 shows the behavior of the sheet resistance for forming the silicide film. Here, according to the invention,
A 0.015 nm Ta layer was processed by flash evaporation. Referring to curve 40 in FIG.
_No noticeable knee is observed when ₂ is formed. FIG.
Curve 60, according to the present invention, has a W of about 0.015 nm.
4 shows the sheet resistance and temperature of a TiSi ₂ film formed using the method shown in FIG. Curves 30 and 40 are shown for comparison with curve 60. Again, there is no significant knee in the case of curve 60, and the C54 phase is formed at temperatures substantially below about 700 ° C.

FIG. 8 is an in-situ scanned resistance diagram showing the sheet resistance of a titanium silicide layer formed using a refractory metal implanted in accordance with the present invention. Curve 70 is, for comparison, a control silicide film formed without using a refractory metal, and curve 80 is a film of TiSi ₂ , where Mo is implanted before Ti deposition. (10 ¹⁴ atoms / cm ² , implantation energy 45 KeV).
After the implantation of Mo, an annealing process was also performed at 900 ° C. for 10 minutes before the deposition of Ti. Similar to conventional curve 30, curve 70 has a knee at point 72, but does not appear in curve 80. The absence of a knee in curve 80 indicates that C54 phase TiSi ₂ is formed at a temperature substantially below about 700 ° C.

FIG. 9 is a graph showing titanium ions measured with and without Mo ion implantation according to the present invention.
It is a histogram of resistance of a silicide line.

In addition to the data previously shown in FIGS. 4 to 9,
Some further endorse that the silicidation according to the present invention substantially bypasses the C49 phase. Optical micrographs of the C54 phase titanium silicide layer formed according to the present invention show that the particle size is much smaller than in the prior art without refractory metal. This is C
Endorses that the 54 phase nucleation energy barrier is greatly reduced by the method of the present invention. This is VLSI
Most importantly in circuits, the line width is smaller than the particle size of the C54 phase formed by conventional methods.

Although the method according to the invention described here is considered to be fairly stable, there are some caveats to its use. First, when employing the present invention to avoid the problem of silicide instability,
Long thermal cycling above 0 ° C should be avoided. Second
If the thickness of the refractory metal layer is too large, the silicide may peel off.

Another advantage of the present invention is that no amorphous silicon layer is formed on top of the silicon layer. Specifically, when depositing a refractory metal by an ion implantation method, any annealing
The silicon is removed. An optional anneal is not required with other processing methods to avoid amorphous silicon. It is desirable to avoid the presence of amorphous silicon because this is related to junction leakage losses.

In another embodiment of the present invention, a step of depositing a layer of a titanium alloy containing a refractory metal on a layer on a silicon layer on a semiconductor wafer and substantially removing C5 from the titanium alloy layer.
Metal silicide can be formed by a method that includes heating the wafer to a temperature sufficient to form four-phase titanium silicide. Here, the phase transition temperature of the titanium alloy decreases due to the presence of the refractory metal. The temperature at which the C54 phase is formed is preferably below about 700 ° C.

Referring to FIG. 1 and FIG. The titanium alloy layer 30 can be deposited on the surface of the silicon substrate 10. Although the silicon substrate 10 itself may be on top of, or form part of, another electronic device, such aspects of a semiconductor device will clarify aspects of the present invention. Not shown for illustrative purposes. The term "electronic device", as used herein, refers to both active and passive electronic devices. The titanium alloy layer comprises titanium and a refractory metal having an atomic percentage of up to 20 such as Ta,
Nb, Mo, W, V, Cr, or a combination thereof. Preferred refractory metals are Ta and Nb. In addition to the refractory metal, Si can be added to the titanium alloy layer. Those skilled in the art will appreciate that embodiments in which silicon is added to the titanium alloy layer may not be able to employ a self-aligned silicide treatment method. In addition to refractory metals, from the groups of the periodic table, IIIA, IVA, VA, and VIA,
B, C, N, O, Al, P, In, Sb, As, etc.
Other elements can be added to the titanium alloy layer. Group VIIA, such as F, should be avoided but, if present, should be at levels well below the atomic percentage of the refractory metal.

The titanium alloy layer can be applied by any of a number of conventional techniques. Titanium and refractory metals
It can be deposited from a different source or from a source of titanium which also contains a small amount of refractory metal. Thereby, the atomic percentage of the refractory metal layer in the obtained layer is less than 20, preferably 1 to 1
5 is assumed. Titanium alloys can be deposited on silicon substrates by a physical vapor deposition (PVD) process of sputtering. For example, a sputtering target of an appropriate titanium alloy is prepared so that the refractory metal has a desired atomic percentage when formed on a silicon substrate. A titanium alloy can also be applied by a PVD process of vapor deposition. The titanium and the refractory metal are then deposited from two different sources at a rate suitable to obtain the desired atomic percentage of the refractory metal. Either of the above processes, as well as other conventional processes for depositing titanium silicide or metal silicide, can deposit a layer of titanium alloy on a silicon substrate. The titanium alloy layer has a thickness of 10
Layers of up to 200 nm, preferably 10 nm to 60 nm, can be deposited.

Referring to FIG. 10 and FIG. The titanium alloy layer 30 can then be heated to a temperature sufficient to form a layer 32 of substantially C54 phase titanium silicide. As used herein, "substantially C54 phase" means a titanium silicide layer whose resistance characteristics are dominated by the C54 phase and which includes at least 50% by weight of the C54 phase. As will be described in greater detail below, an advantage of the present invention is that the C54 phase can be formed directly in effect in the titanium silicide formation step, eliminating the need for a second phase "conversion anneal",
The point is that the phase transition annealing treatment can be eliminated.
In addition, because refractory metal exists in titanium silicide,
The thermal degradation temperature, ie, the temperature at which unwanted transitions such as agglomeration occur, substantially increase. Increasing the thermal degradation temperature has the advantage of increasing the margin of processing.

As shown in FIG. 12, the in-situ scanned resistance plot shows the decrease in temperature for forming titanium silicide containing refractory metal versus the temperature for forming pure titanium silicide. . This figure also shows that thermal stability is improved when refractory metals are used. The titanium layers shown in FIG.
Annealing was performed in an atmosphere to a temperature of 1050 ° C. (15 ° C./min).

FIG. 13 shows the resistance as a function of the atomic percentage of the refractory metal present in the titanium alloy used to form the titanium silicide. Titanium alloy is H
Annealing was performed at 900 ° C. (15 ° C./min) in an e atmosphere. Region of FIG surrounded by a broken line as a "C49 TiSi _2" and "C54 TiSi _2" shows a C49 phase and TiSi ₂ standard resistance range of C54 phase formed from pure TiSi _2. This figure shows that the refractory metal of the present invention is an annealed titanium alloy with an atomic percentage of 1 to 20 and the resistance is much lower than that of C49 phase TiSi ₂ . However, the titanium alloy formed with Mo shows a decrease in resistance at a concentration of about 5 atomic percent. FIG. 14 also shows resistance as a function of the atomic percentage of the refractory metal present in the titanium alloy used to form the titanium silicide. However, in FIG. 14, 30 n at 700 ° C. (35 ° C./s is maintained for 60 seconds) in an N ₂ atmosphere.
Annealing treatment was performed on the titanium alloy layer of m to 50 nm. FIGS. 13 and 14 show Ta, Nb, and M, respectively, whose resistances are much lower than titanium silicide in the C49 phase.
1 shows a titanium silicide formed from a titanium alloy containing o, W, and V. FIG. 15 further shows the formation temperature of C54 as a function of the atomic percentage of refractory metal added to the titanium alloy. FIGS. 14 and 15 both show that the resistance of the annealed titanium alloy of the present invention is pure Ti
It is comparable to TiSi ₂ of the C54 phase formed from Si _2, as well as such a low-resistance, indicating that it is accomplished at a much lower annealing temperature.

The process of the present invention can be easily incorporated into semiconductor manufacturing methods employing titanium silicide formed from pure titanium. For example, referring to FIG. 16, in the CMOS transistor shown in the figure, a titanium silicide layer 50 of the present invention includes a source 52, a drain 54,
And N-MOSFE as the gate contact 56
Used for both T and P-MOSFET devices. However, the titanium silicide of the present invention can be used with many other electronic device manufacturing methods.

The titanium alloy containing titanium and the refractory metal is as follows:
On the device including the polysilicon layer 58, and on the regions 52 and 54 of the highly doped silicon,
It can be deposited like pure titanium in self-aligned silicide applications. After deposition, the titanium alloy can be first heated to a low temperature in a "formation anneal" to form titanium silicide. Because the C54 phase titanium silicide can be formed from a titanium alloy at a much lower temperature than other silicides, the formation anneal substantially reduces the C5
A four-phase titanium silicide layer can be formed.
Thus, in many cases, the use of a titanium alloy can substantially form the C54 phase titanium silicide by the first low temperature anneal, thus completely eliminating the need for conversion anneal. However, depending on the formation annealing temperature and the shape of the element, conversion annealing may still be necessary depending on the application.

[0052] The titanium silicide, whether in the C49 phase, the C54 phase, or a mixture thereof, can then be selectively etched according to the processing method of the present invention, removing the unreacted portions of the titanium alloy layer. This process is commonly referred to as a "salicide" or self-aligned silicide process. This is because the region of the titanium alloy not located on the silicon substrate does not react to form silicide, and can be "self-aligned" by a process of selectively etching a metal with respect to silicide. After etching, C4
Nine-phase titanium silicide, or titanium silicide with a mixture of C49 and C54 layers, can be subjected to a second anneal or "conversion anneal." Here, the silicide transforms into the desired substantially C54 phase titanium silicide. However, even in such instances where a conversion anneal is necessary or desirable, the conversion anneal can be performed at a much lower temperature, thus saving available heat. After the low resistance titanium silicide layer of the present invention is formed, electronic components and desired interconnects can be defined by conventional semiconductor manufacturing methods.

When pure titanium silicide is present, the formation anneal forms a C49 phase titanium silicide. The formation anneal is always completed at low temperatures (at low temperatures no C54 phase is formed from pure TiSi ₂ ) to prevent silicide from forming over unnecessary areas of the device. This problem is commonly called a bridge. For example, the device of FIG. 16 selectively etches unwanted portions of the titanium layer after exposure to the temperature required to form a C54 phase titanium silicide from pure titanium, in which case the oxide Silicide may be formed on the spacer 62. When silicide is formed on the spacer 62, the gate 59 and the region of the source 52 or the drain 54 are electrically connected to each other, thereby causing a short circuit of the device. Therefore, the existing silicide processing method is the second method.
After removing the unreacted titanium portions by high temperature annealing, ie, conversion annealing, the C49 phase titanium silicide must be converted to the desired low resistance C54 phase.
Thus, a layer of low resistance titanium silicide, substantially in the C54 phase, is deposited with the titanium alloy in a single forming anneal,
Or with a conversion anneal whose temperature is significantly lower than 900 ° C.
What can be formed by heating the element is particularly important. As indicated above, forming the C54 phase from a titanium alloy has the advantage of less migration of the dopant material that makes up the predefined doped regions 58 and 60 of the individual electronic devices.

In summary, the following items are disclosed regarding the configuration of the present invention.

(1) A method for forming a titanium silicide layer on a silicon substrate of a semiconductor device, comprising: depositing a titanium alloy layer containing an atomic percentage of 1 to 20 on a silicon substrate on the silicon substrate; The above titanium alloy,
Heating to a temperature sufficient to form substantially C54 phase titanium silicide. (2) The method according to (1), wherein the temperature is less than about 700 ° C. (3) The method according to (1), wherein the substrate is heated to a temperature sufficient to completely transform the titanium alloy layer to C54 phase titanium silicide. (4) The method according to the above (1), wherein the refractory metal contains an element of the group consisting of Ta, Nb, W, V, and Cr. (5) The method according to (2), wherein the titanium alloy contains a refractory metal having an atomic percentage of 1 to 15. (6) The method according to (5), wherein the refractory metal includes a refractory metal selected from the group consisting of Ta and Nb. (7) The method according to (2), wherein the titanium alloy includes titanium, silicon, and a refractory metal. (8) The titanium alloy layer has a thickness of 10 on the silicon substrate.
The method according to (1) above, wherein the method is deposited to a thickness of 60 nm to 60 nm. (9) The method according to (1), wherein the silicon substrate is selected from the group consisting of single crystal silicon, polycrystalline silicon, amorphous silicon, and silicon-germanium alloy. (10) The silicon substrate is made of S containing an N-type dopant.
The method according to (1) above, wherein the method is selected from the group of silicon-on-insulator (OI) and SOI containing P-type dopant. (11) The method according to (1), wherein the titanium alloy is deposited on the silicon substrate by physical vapor deposition. (12) The method according to (1), wherein the titanium alloy is deposited on the silicon substrate by chemical vapor deposition. (13) The method according to (1), wherein the titanium alloy contains about 1 to about 5 atomic percent of Mo. (14) A method of forming a titanium silicide layer on a semiconductor element, comprising: incorporating a 10 to 200 nm titanium alloy layer containing an atomic percentage of 1 to 15 refractory metal into a plurality of electronic elements with exposed silicon surfaces. Depositing on the semiconductor device and heating the titanium alloy layer to a temperature below about 700 ° C. sufficient to form substantially C54 phase titanium silicide on the titanium alloy layer on the silicon surface; Etching a non-reactive portion of the titanium alloy layer. (15) A method of forming a titanium silicide layer on a semiconductor device, comprising: incorporating a 10 to 200 nm titanium alloy layer containing an atomic percentage of 1 to 15 refractory metal into a plurality of electronic devices with exposed silicon surfaces. Depositing on the semiconductor element, heating the titanium alloy layer to a temperature sufficient to form titanium silicide on the titanium alloy layer on the silicon surface, and etching a non-reactive portion of the titanium alloy layer Steps to
Heating said titanium silicide to a temperature less than about 700 ° C. sufficient to form substantially C54 phase titanium silicide. (16) a silicon layer, and substantially C54 phase titanium silicide and an atomic percentage of 1 to 20 on the silicon layer;
A layer of titanium silicide comprising a refractory metal of
A semiconductor device having a titanium silicide layer. (17) The silicon layer is made of single crystal silicon, polycrystal silicon, amorphous silicon, silicon germanium alloy, SOI (silicon-on
-insulator) and the semiconductor device according to (16), selected from the group of SOIs having a P-type dopant. (18) The refractory metal is Ta, Nb, W, V, and C
The semiconductor device according to (16), wherein the semiconductor device is selected from at least one group of r. (19) The semiconductor device according to (16), wherein the titanium silicide layer contains a refractory metal having an atomic percentage of 1 to 15. (20) The semiconductor element according to (17), wherein the refractory metal is selected from the group consisting of Ta and Nb. (21) The semiconductor device according to (16), wherein the titanium silicide layer contains Mo in an atomic percentage of 1 to 5. (22) The titanium silicide layer has a thickness of 10 nm to 2 nm.
The semiconductor device according to (16), having a thickness of 00 nm.

[Brief description of the drawings]

FIG. 1 shows a C54 phase titanium according to one embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating formation of silicide.

FIG. 2 shows a C54 phase titanium according to one embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating formation of silicide.

FIG. 3 shows a C54 phase titanium according to one embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating formation of silicide.

FIG. 4 is a graph showing the sheet resistance of a titanium silicide layer and the thickness of sputtered titanium for multiple processes with and without the use of a refractory metal according to the present invention.

FIG. 5 illustrates the sheet resistance of titanium silicide layers formed by multiple processes with and without the use of refractory metal deposited or implanted in accordance with the present invention.
FIG. 4 is a diagram showing a graph of resistance scanned in place.

FIG. 6 shows the sheet resistance of titanium silicide layers formed by multiple processes with and without the use of refractory metal deposited or implanted according to the present invention;
FIG. 4 is a diagram showing a graph of resistance scanned in place.

FIG. 7 shows the sheet resistance of titanium silicide layers formed by multiple processes with and without the use of refractory metal deposited or implanted in accordance with the present invention;
FIG. 4 is a diagram showing a graph of resistance scanned in place.

FIG. 8 shows the sheet resistance of titanium silicide layers formed by multiple processes with and without the use of refractory metal deposited or implanted in accordance with the present invention.
FIG. 4 is a diagram of a resistance scanned in place.

FIG. 9 is a diagram showing histograms of resistance of a titanium silicide line measured when Mo ions are implanted and not implanted according to the present invention.

FIG. 10 is a cross-sectional side view illustrating the formation of a C54 phase titanium silicide according to the present invention.

FIG. 11 is a cross-sectional side view illustrating the formation of a C54 phase titanium silicide according to the present invention.

FIG. 12: Pure Ti, Ti (tantalum) alloy, and T
It is a figure which shows the graph of normalized sheet resistance and temperature at the time of forming titanium silicide from an i (niobium) alloy.

FIG. 13 is a graph showing the resistance of a titanium silicide layer annealed at 900 ° C. and the atomic percentage of refractory metal.

FIG. 14 is a diagram depicting a graph of the resistance of the titanium silicide layer annealed at 700 ° C. and the atomic percentage of the refractory metal.

FIG. 15 is a graph showing the formation temperature of C54 titanium silicide and the atomic percentage of refractory metal.

FIG. 16 is a cross-sectional side view of a part of a semiconductor device incorporating the low-resistance titanium silicide of the present invention.

[Explanation of symbols]

Reference Signs List 10 silicon layer 12 top surface 14 refractory metal 16 titanium layer 18 TiSi ₂ film 30 titanium alloy layer 32, 50 titanium silicide layer 52 source 54 drain 56 gate contact 58 polysilicon layer 59 gate 60 doping region 62 oxide spacer

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Lawrence Alfred Clevenger United States 12540, Andrews Road, Lagrangeville, NY 377 (72) Inventor François Maxdore United States 10562, Ossining, NY Spring Valley Road (72) Inventor James McKell Edwin Harper United States 10598, Yorktown Heights, NY, Elizabeth Road 507 (72) Inventor Randy William Man United States 05465, Jericho, Vermont, Sunnyview Drive 23 (72) Inventor Glen Leicester Miles, United States 05452, Essex, Vermont Junction, 26 Brickyard Road 35 (72) Inventor James Spiros Nacos United States 05452, Essex, Vermont, Butternut Court 3 (72) Inventor Ronen Andrew Roy United States 15010, New York, Briarcliff Manoa, 3E, State Road 332N (72) Inventor Katherine El Saenger United States 10562, Underhill Road 115, Ossining, NY

Claims (22)

[Claims] 1. A method for forming a titanium silicide layer on a silicon substrate of a semiconductor device, the method comprising: depositing a titanium alloy layer containing an atomic percentage of 1 to 20 refractory metal on the silicon substrate; Heating the titanium alloy to a temperature sufficient to form substantially C54 phase titanium silicide. 2. The method of claim 1, wherein said temperature is less than about 700.degree. 3. The method of claim 1 wherein said substrate is heated to a temperature sufficient to completely transform said titanium alloy layer to C54 phase titanium silicide. 4. The method of claim 1, wherein said refractory metal comprises an element of the group consisting of Ta, Nb, W, V, and Cr. 5. The method of claim 2 wherein said titanium alloy comprises 1 to 15 atomic percent of refractory metal. 6. The method of claim 5, wherein said refractory metal comprises a refractory metal selected from the group consisting of Ta and Nb. 7. The method of claim 2, wherein said titanium alloy comprises titanium, silicon, and a refractory metal. 8. The method according to claim 1, wherein said titanium alloy layer is deposited on said silicon substrate to a thickness of 10 nm to 60 nm.
The described method. 9. The method of claim 1, wherein said silicon substrate is selected from the group consisting of single crystal silicon, polycrystalline silicon, amorphous silicon, and silicon-germanium alloy. 10. The method of claim 1, wherein said silicon substrate is selected from the group of a silicon-on-insulator (SOI) containing an N-type dopant and an SOI containing a P-type dopant. 11. The method of claim 1, wherein said titanium alloy is deposited on said silicon substrate by physical vapor deposition. 12. The method of claim 1, wherein said titanium alloy is deposited on said silicon substrate by chemical vapor deposition. 13. The method of claim 1, wherein said titanium alloy comprises about 1 to about 5 atomic percent of Mo. 14. A method for forming a titanium silicide layer on a semiconductor device, comprising: forming a titanium silicide layer on a semiconductor device, comprising:
Depositing a 00 nm titanium alloy layer on said semiconductor device incorporating a plurality of electronic devices with exposed silicon surface; and forming substantially C54 phase titanium silicide on said titanium alloy layer on said silicon surface. Heating the titanium alloy layer to a temperature less than about 700 ° C. sufficient to etch the non-reactive portion of the titanium alloy layer. 15. A method for forming a titanium silicide layer on a semiconductor device, comprising: forming a titanium silicide layer on a semiconductor device, comprising:
Depositing a 00 nm titanium alloy layer on said semiconductor device incorporating a plurality of electronic devices with exposed silicon surface; and increasing the temperature to a temperature sufficient to form titanium silicide in the titanium alloy layer on said silicon surface. Heating the titanium alloy layer; etching a non-reactive portion of the titanium alloy layer; and forming the titanium silicide to a temperature below about 700 ° C. sufficient to substantially form a C54 phase titanium silicide. Heating the method. 16. A titanium silicide layer comprising: a silicon layer; and a layer of titanium silicide on the silicon layer, the layer comprising substantially C54 phase titanium silicide and a refractory metal having an atomic percentage of 1 to 20. Semiconductor element. 17. The SOI (silicon) having single crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium alloy, and N-type dopant as the silicon layer.
SOI with con-on-insulator) and P-type dopant
17. The semiconductor device according to claim 16, which is selected from the group consisting of: 18. The refractory metal is Ta, Nb, W, V,
And at least one group of Cr.
The semiconductor device according to claim 16. 19. The semiconductor device according to claim 16, wherein said titanium silicide layer contains a refractory metal having an atomic percentage of 1 to 15. 20. The semiconductor device according to claim 17, wherein said refractory metal is selected from the group consisting of Ta and Nb. 21. The semiconductor device according to claim 16, wherein said titanium silicide layer contains 1 to 5 atomic percent of Mo. 22. The titanium silicide layer has a thickness of 10 nm.
17. The semiconductor device according to claim 16, having a thickness of from about 200 nm to about 200 nm.