JPH1153039A - Constant voltage generator - Google Patents

Abstract

(57) [Problem] To provide a constant voltage generating circuit that optimally sets an input voltage of a current mirror amplifier and does not increase a chip area. SOLUTION: In a level shift circuit 17, VRE is applied.
Since F is received only at the gate of the n-channel MOS transistor 3 and the flowing current is greatly reduced, it is not necessary to increase the current driving capability of the reference potential generating circuit 14 and the chip area can be reduced. Further, since the output voltage from the level shift circuit 17 can be set by the transistor ratio of the p-channel MOS transistor 1 and the n-channel MOS transistors 3 and 9, the current mirror amplifier 19 can be operated at an optimum operating point. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage generation circuit, and more particularly, to a constant voltage generation circuit for generating an internal step-down power supply voltage by lowering an external power supply voltage.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit such as a DRAM, it is necessary to reduce a power supply voltage in order to reduce power consumption and to secure reliability of a transistor as a result of higher integration.
For example, in a DRAM having an integration degree of 256 Mbits or more,
The external power supply voltage (VEXT) has become 2.5V and the internal step-down power supply voltage (VINT) has become about 2.0V. In the conventional constant voltage generating circuit, a reference power supply voltage (VREF) is internally generated from VEXT, and VINT is generated by differentially amplifying this VREF and negatively fed VINT by a current mirror amplifier. . But VE
When the potential difference between XT and VINT is small, there arises a problem that the gain of the current mirror amplifier decreases and the current supply capability decreases.

In the conventional constant voltage generating circuit, in order to solve this problem, VINT and VREF are stepped down by a level shift circuit and then differentially amplified by a current mirror amplifier as disclosed in Japanese Patent Application Laid-Open No. 7-212869. The method was used. FIG. 7 shows a circuit diagram of such a conventional constant voltage generating circuit. This conventional constant voltage generation circuit
Level shift circuits 107 and 108 and phase compensation capacitor 1
03, 104, a current mirror amplifier 109, a p-channel MOS transistor 11, and a reference potential generating circuit 1.
4, the reference potential drive circuit 105, and the phase compensation circuit 1
6 is comprised. This conventional constant voltage generation circuit generates VINT from VEXT and supplies it to the DRAM internal circuit 15.

A reference potential generation circuit 14 generates and outputs a reference potential. The reference potential drive circuit 55 increases the current capacity of the reference potential generated by the reference potential generation circuit 14 and outputs it as VREF. Level shift circuit 107
Is an n-channel MOS transistor 101 having a gate and a drain to which VREF is input and having a source voltage as an output voltage; a drain connected to the source of the n-channel MOS transistor 101; a source connected to the ground; , And an n-channel MOS transistor 30 which operates as a constant current source through which a constant current flows. The n-channel MOS transistor 30 is
The gate width is set to be very small as compared with 1.

The level shift circuit 108 has the same structure as that of the level shift circuit 107. The VINT is input to the gate and the drain, and the n-channel MOS transistor 102 whose source voltage is the output voltage.
An n-channel MOS transistor 31 is connected to the source of the channel MOS transistor 102, the source is connected to the ground, a constant voltage at the base is input, and the constant current source flows and operates as a constant current source. The source of the current mirror amplifier 109 is V
A p-channel MOS transistor 6 connected to EXT, having a gate and a drain connected, a p-channel MOS transistor having a source connected to VEXT, a gate connected to the gate of the p-channel MOS transistor 6, and having a drain voltage as an output voltage The output voltage from the level shift circuit 107 is input to the transistor 5 and the gate, and the drain is connected to the drain of the p-channel MOS transistor 5.
The output voltage from the level shift circuit 108 is input to the channel MOS transistor 7 and the gate, and the drain is p
An n-channel MOS transistor 8 connected to the drain of the channel MOS transistor 6, a drain commonly connected to the respective sources of the n-channel MOS transistors 7 and 8, a source connected to ground, and a fixed voltage at the base An n-channel MOS transistor 10 which is inputted and operates as a constant current source through which a constant current flows.

[0006] The phase compensation capacitor 103 is connected between VREF and the base of the n-channel MOS transistor 7. The phase compensation capacitor 104 is connected between VINT and the base of the n-channel MOS transistor 8. The phase compensation capacitors 103 and 104 are capacitors for compensating the delayed phase in the level shift circuits 107 and 108. When a phase delay of the level shift unit occurs in a high frequency band, VREF and VINT are converted to high frequency. To the input of the current mirror amplifier 19 directly. The P-channel MOS transistor 11 receives the output voltage of the current mirror amplifier 109 at its gate,
EXT is input to the drain, and VINT is output from the source.

[0007] The phase compensation circuit 16 is connected to VINT and comprises a resistor and a capacitor. As shown in Japanese Patent Application Laid-Open No. 4-6693, this phase compensating circuit 16 compensates the phase against the noise from the DRAM internal circuit 15, VEXT and the oscillation caused by the feedback loop of the constant voltage generating circuit itself. P-channel MOS transistor 1 which is a normal drive transistor
For a gate width W of 1 = several thousands of μm, several hundred pF to several thousand pF
And several Ω to several tens Ω of resistance. Next, the operation of the conventional constant voltage generating circuit will be described. The reference potential generated by the reference potential generation circuit 14 is input to the reference potential drive circuit 105 and output as VREF. VREF is an n-channel MOS transistor 1
01 is input to the gate, drain and phase compensation capacitor 103. Compared with the n-channel MOS transistor 101, the n-channel MOS transistor 30 has a very small gate width, so that the level shift circuit 10
The voltage output from 7 is determined by the threshold voltage Vt of the n-channel MOS transistor 101 and becomes VREF-Vt.

[0008] Similarly to VREF, VINT is also input to the level shift circuit 108 and output as a voltage of VINT-Vt. The voltages VREF-Vt and VINT-Vt output from the level shift circuits 107 and 108 are input to the current mirror amplifier 109, and are differentially amplified and then output to the gate of the P-channel MOS transistor 11. Here, when VINT becomes lower than VREF by △ V, the output voltage of the level shift circuit 107 becomes V
REF-Vt, the output voltage of the level shift circuit 108 is V
Since REF−Vt−ΔV, the potential difference between the inputs of the current mirror amplifier 109 becomes ΔV. Assuming that the gain of the current mirror amplifier 109 is A, the output voltage is multiplied by A and P
The gate voltage of the channel MOS transistor 11 is A × △
As a result, the P-channel MOS transistor 11 increases the current supply capability and recovers from the drop of ΔV. Therefore, in a stable state, VINT = VREF. For example,
If VREF = 2.0V is not set, VINT = 2.0V
become.

In this conventional constant voltage generating circuit, VEXT
Even if the potential difference between VINT and VINT becomes small, the input voltage of the current mirror amplifier 109 can be set low, so that the gain of the feedback loop of VINT can be increased, and as a result, the current drive capability of VINT is increased. And phase compensation of the level shift circuits 107 and 108 in a higher frequency band can be performed. However, in the conventional constant voltage generating circuit, the level shift circuits 107 and 108 use the diode connection type n-channel MOS transistors 101 and 102 whose gates and drains are connected as the voltage step-down means. The input voltage 109 is determined by the threshold values of the n-channel MOS transistors 101 and 102, making it difficult to set an optimal input voltage for the current mirror amplifier 109.

In order to solve this problem, there is a method in which the level shift circuits 107 and 108 are configured by resistance division. However, the resistance value requires several thousand Ω, and the output becomes unstable due to the variation in the resistance value. In addition, there is a problem that a phase delay occurs due to a time constant due to the capacitance and the resistance component of the resistance portion, and the oscillation becomes easy. Further, in a normal DRAM or the like, the reference potential generating circuit that is always operating has almost no current driving capability in order to reduce current consumption during standby. Therefore, in the conventional constant voltage generation circuit in which a large current flows from VREF to the ground level and in the constant voltage generation circuit using resistance division, a reference potential drive circuit having current driving capability is provided between the reference potential generation circuit and the level shift circuit. Must be added, which causes a problem such as an increase in chip area.

[0011]

The above-mentioned conventional constant voltage generating circuit has the following problems. (1) When a diode connection type n-channel MOS transistor is used for the level shift circuit, the input voltage of the current mirror amplifier is determined by the threshold value of the n-channel MOS transistor of the level shift circuit.
It is difficult to set the optimum input voltage of the current mirror amplifier. (2) When resistance division is used for the level shift circuit,
The output becomes unstable due to the variation in the resistance value, and a phase lag occurs to facilitate oscillation. (3) In order to increase the current driving capability, a reference potential driving circuit having current driving capability must be added between the reference potential generating circuit and the level shift circuit, and the chip area increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a constant voltage generating circuit which can set an input voltage of a current mirror amplifier optimally, does not easily oscillate, and does not increase the chip area.

[0013]

In order to achieve the above object, a constant voltage generating circuit according to the present invention is configured to generate an internal step-down power supply voltage which is lower than the external power supply voltage from an external power supply voltage. A reference potential generation circuit for generating a reference potential from the external power supply voltage; a first transistor having the reference potential input to a base;
A first constant current source connected between the source of the first transistor and the ground, and a first voltage provided between the drain of the first transistor and the external power supply voltage for reducing the external power supply voltage A first level shift circuit configured to include a step-down unit, the drain voltage of the first transistor being used as an output voltage, and the internal step-down power supply voltage being input to a base, and a source being connected to the first constant current source. A second transistor connected thereto, and second voltage step-down means provided between the drain of the second transistor and the external power supply voltage for stepping down the external power supply voltage,
A second level shift circuit that outputs a voltage of a drain of the second transistor as an output voltage; and a first and a second input terminal. The output voltage from the first level shift circuit is the first level shift circuit. Input to an input terminal, output voltage from the second level shift circuit to the second input terminal, and differentially amplify a voltage between the first input terminal and the second input terminal. A current mirror amplifier that outputs
A third transistor configured to receive an output voltage from the current mirror amplifier at a gate, input the external power supply voltage at a source, and output the internal step-down power supply voltage from a drain.

According to the present invention, in the first level shift circuit, the reference potential is received only by the gate of the first transistor, and the current flowing from the reference potential is greatly reduced. Therefore, since it is not necessary to increase the current driving capability of the reference potential generation circuit, the chip area can be reduced and a stable voltage supply can be performed. Further, according to the present invention, the output voltage from the first level shift circuit is determined by setting the first voltage step-down means, the first transistor, and the first constant current source, and the output voltage from the second level shift circuit is determined. The output voltage is determined by setting the second voltage step-down means, the second transistor, and the first constant current source.

Therefore, the output voltages from the first and second level shift circuits can be freely set, and the current mirror amplifier can be operated at an optimum operating point. The constant voltage generation circuit according to the present invention is a constant voltage generation circuit that generates an internal step-down power supply voltage that is lower than the external power supply voltage from an external power supply voltage, wherein the reference voltage generation circuit generates a reference potential from the external power supply voltage. A circuit, a first transistor having the base inputted with the reference potential, a first constant current source connected between a source of the first transistor and ground, and a drain of the first transistor. A first level shifter provided between the external power supply voltage and a first voltage step-down means for lowering the external power supply voltage, wherein the first level shift circuit uses a voltage at a drain of the first transistor as an output voltage; A second transistor having the base inputted with the internal step-down power supply voltage, a second constant current source connected between the source of the second transistor and ground, Is composed of a second voltage step-down means for stepping down the external supply voltage is provided between the drain and the external power supply voltage of the second transistor,
A second level shift circuit that outputs a voltage of a drain of the second transistor as an output voltage; and a first and a second input terminal. The output voltage from the first level shift circuit is the first level shift circuit. Input to an input terminal, output voltage from the second level shift circuit to the second input terminal, and differentially amplify a voltage between the first input terminal and the second input terminal. A current mirror amplifier that outputs
A third transistor configured to receive an output voltage from the current mirror amplifier at a gate, input the external power supply voltage at a source, and output the internal step-down power supply voltage from a drain.

According to the present invention, first and second constant current sources are provided in the first and second level shift circuits, respectively, and the output voltage from the first level shift circuit is reduced by first voltage step-down means.
The output voltage from the second level shift circuit is determined by the setting of the first transistor and the first constant current source, and the output voltage from the second level shift circuit is set by the setting of the second voltage step-down unit, the second transistor, and the second constant current source. The decision is made. Therefore, since the phase of the output voltage of the first level shift circuit in the high frequency band can be recovered, the phase margin of the feedback loop can be further improved. The constant voltage generation circuit according to the present invention is a constant voltage generation circuit that generates an internal step-down power supply voltage that is lower than the external power supply voltage from an external power supply voltage, wherein the reference voltage generation circuit generates a reference potential from the external power supply voltage. A circuit, a first transistor having the base inputted with the reference potential,
A first constant current source connected between the source of the first transistor and the ground, and a first voltage provided between the drain of the first transistor and the external power supply voltage for reducing the external power supply voltage And a step-down means for setting a voltage of a source of the first transistor as an output voltage.
A level shift circuit, a second transistor whose base is supplied with the internal step-down power supply voltage, a second constant current source connected between the source of the second transistor and ground, A second voltage step-down means provided between the drain of the transistor and the external power supply voltage for lowering the external power supply voltage, the second voltage step-down means having a source voltage of the second transistor as an output voltage. A level shift circuit, and a first and a second input terminal, wherein an output voltage from the first level shift circuit is input to the first input terminal, and an output voltage from the second level shift circuit To the second input terminal, and differentially amplifies and outputs a voltage between the first input terminal and the second input terminal, and an output from the current mirror amplifier. Pressure is input to the gate, the external power supply voltage is input to the source, characterized in that it is composed of a third transistor which outputs the internal step-down power supply voltages from the drain.

According to the present invention, the output voltage from the first level shift circuit is taken from the source of the first transistor, and the output voltage from the second level shift circuit is taken from the second level shift circuit.
From the source of the transistor. Therefore, the output voltage can be set to a lower voltage than when the output voltage is obtained from the drains of the first and second transistors, so that even when the optimal operating point of the current mirror amplifier becomes a low level, Can respond. According to an embodiment of the present invention, the current mirror amplifier includes a third transistor having a source connected to the external power supply voltage, a gate and a drain connected, a source connected to the external power supply voltage, and a gate connected to the external power supply voltage. A fourth transistor connected to the gate of the third transistor and having a drain voltage as an output voltage; and an output voltage from the first level shift circuit input to the gate and a drain connected to the third transistor. A fifth transistor connected to the drain, a sixth transistor having a gate to which an output voltage from the second level shift circuit is input, a drain connected to the drain of the fourth transistor, and one terminal Are commonly connected to the respective sources of the fifth transistor and the sixth transistor, and the other terminal is connected to the ground. And a third constant current source connected to the de.

According to another embodiment of the present invention, a first phase compensation capacitor provided between a gate of the second transistor and a first input terminal of the current mirror amplifier is provided. A second phase compensation capacitor provided between the gate of the first transistor and a second input terminal of the current mirror amplifier. According to the present invention, a signal having the same phase as the internal step-down power supply voltage is input to the first input terminal of the current mirror amplifier by the first phase compensation capacitor, and a signal having the same phase as the reference potential is inputted by the second phase compensation capacitor. The current is input to the second input terminal of the current mirror amplifier. Therefore, the first and second
In addition, it is possible to compensate for the phase delay caused by the level shift circuit and to suppress the decrease in the gain.

According to another embodiment of the present invention, the first and second voltage step-down means are transistors having a gate and a drain connected to each other. According to another embodiment of the present invention, the first and second voltage step-down means are resistance elements. According to another embodiment of the present invention, the first and second voltage step-down means are one or more diodes connected in series.

[0020]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. (First Embodiment) FIG. 1 shows a circuit diagram of a constant voltage generating circuit according to a first embodiment of the present invention. The same numbers as those in FIG. 7 indicate the same components. The constant voltage generation circuit according to the present embodiment includes a reference potential generation circuit 14, level shift circuits 17, 18, a current mirror amplifier 19, a p-channel MOS transistor 11, phase compensation capacitors 12, 13, and a phase compensation circuit. 16. Level shift circuit 17
Is a p-channel MOS transistor 1 whose source is supplied with VEXT, whose gate and drain are connected, and whose drain voltage is an output voltage, and whose gate is supplied with VREF and whose drain is connected to the drain of the p-channel MOS transistor 1 N-channel MOS transistor 3;
An n-channel MOS transistor 9 having a drain connected to the source of the n-channel MOS transistor 3, a source connected to the ground, a constant voltage at the base input, and operating as a constant current source through which a constant current flows. ing.

The level shift circuit 18 has VEX
T is input, the gate and the drain are connected, and a p-channel MOS transistor 2 having the drain voltage as an output voltage; VINT is input to the gate; the drain is connected to the drain of the p-channel MOS transistor 2; And an n-channel MOS transistor 4 connected to the drain of the channel MOS transistor 9. The source of the current mirror amplifier 19 is VEX
A p-channel MOS transistor 5 connected to T and having a gate and a drain connected; a p-channel MOS transistor having a source connected to VEXT, a gate connected to the gate of the p-channel MOS transistor 5, and having a drain voltage as an output voltage An output voltage from the level shift circuit 107 is input to the transistor 6, an n-channel MOS transistor 7 having a drain connected to the drain of the p-channel MOS transistor 5, and an output voltage from the level shift circuit 108 is input to the gate. An n-channel MOS transistor 8 having a drain connected to the drain of the p-channel MOS transistor 6 and a drain commonly connected to the sources of the n-channel MOS transistors 7 and 8, a source connected to ground, and a base A certain voltage is input It is, and a n-channel MOS transistor 10 for operating as a constant current source to flow a constant current.

The phase compensating capacitor 12 is connected between VINT and the base of the n-channel MOS transistor 7. The phase compensation capacitor 13 is composed of VREF and n-channel M
It is connected between the base of the OS transistor 8.
The phase compensating capacitors 12 and 13 are capacitors for compensating a delayed phase in the level shift circuits 17 and 18, respectively.
When a phase delay of 7, 18 occurs, VREF and VI
NT is transmitted directly to the input of the current mirror amplifier 19 in high frequency. Next, the operation of the present embodiment will be described with reference to FIGS. VREF generated by the reference potential generation circuit 14 is equal to the n-channel M of the level shift circuit 17.
The signal is input to the gate of the OS transistor 3 and the P channel M
The voltage is reduced to a voltage determined by the gate length and gate width of the OS transistor 1 and the n-channel MOS transistors 3 and 9 and output to the current mirror circuit 19.

In the level shift circuit 17, an n-channel M
VREF input to the gate of the OS transistor 3 is
Since the voltage is output from the drain of the n-channel MOS transistor 3, the input VREF is inverted by 180 degrees and output. Therefore, the phase of VREF output to the current mirror amplifier 19 is opposite to VREF in the case of the conventional constant voltage generation circuit of FIG. Also, VI
NT is input to the gate of the n-channel MOS transistor 4 of the level shift circuit 18 and is lowered to a voltage determined by the gate length and gate width of the P-channel MOS transistor 2 and the n-channel MOS transistors 4 and 9 and the phase shift is performed. The output shifted by 180 degrees is output to the current mirror circuit 19. Thereafter, the current mirror circuit 19
7, the operation of outputting VINT by differentially amplifying output voltages from the level shift circuits 17 and 18 and outputting the amplified voltage to the gate of the p-channel MOS transistor 11 and the operation of stabilizing VINT = VREF are shown in FIG.
The operation is the same as that of the conventional constant voltage generating circuit described above.

The phase compensating capacitor 12 outputs a signal in phase with VINT and the phase shift compensating capacitor 13 outputs a signal in phase with VREF to the current mirror amplifier 19. Compensate for delays from low to high frequencies. Therefore, the constant voltage generation circuit of the present embodiment can obtain the same phase characteristics as compared to a constant voltage generation circuit that does not use a level shift circuit. The gain and phase frequency characteristics in the VINT feedback loop of the constant voltage generation circuit of the present embodiment will be described with reference to the Bode diagram of FIG. The condition under which the feedback loop does not oscillate is that the phase margin, which is the minimum phase when the gain is 0 dB or more, is 45 degrees or more. In the present embodiment, the phase margin is 45 degrees, so that it is stable. You can see that.

In this embodiment, the output level of the level shift circuit 17 is the P-channel MOS transistor 1,
It can be set freely by adjusting the gate length and gate width of the n-channel MOS transistors 3 and 9. The output level of the level shift circuit 18 can be freely set by adjusting the gate length and the gate width of the P-channel MOS transistor 2 and the n-channel MOS transistors 4 and 9. Therefore, each output can be set freely according to the optimum operating point of the current mirror amplifier 19. Further, in the level shift circuit 17, VREF is input to only the gate of the n-channel MOS transistor 3, so that almost no current flows. Therefore, the reference potential drive circuit 105 as shown in FIG. 7 is not required.

(Second Embodiment) FIG. 3 is a circuit diagram of a constant voltage generating circuit according to a second embodiment of the present invention. The same numbers as those in FIG. 1 indicate the same components. This embodiment is the first embodiment of FIG.
In this embodiment, the level shift circuit section 18 is replaced with a level shift circuit 38. The level shift circuit 38 is different from the level shift circuit 18 in that a drain is connected to the source of the n-channel MOS transistor 4, a source is connected to the ground, a constant voltage is input to the base, and a constant current flows. It is provided with an n-channel MOS transistor 20 that operates as a current source. As a result, the level silt circuits 17, 38
The sources of the n-channel MOS transistors 3 and 4 as input transistors are not connected to a common constant current source, but are connected to n-channel MOS transistors 9 and 20 as separate constant current sources, respectively. .

The operation of this embodiment is the same as that of the first embodiment, except that the change in the current at the output section B of the level shift circuit 17 is different from that of the first embodiment. In the first embodiment, for example, when VINT rises, an n-channel MOS
The current flowing through the transistor 4 increases, and the n-channel MO
The source potentials of the S transistors 3 and 4 are increased. At the same time, the output potential of the level shift circuit 17 rises due to the phase compensation capacitor 12, and the source and drain of the n-channel MOS transistor 3 maintain the same phase. However, in this embodiment, since the sources of the n-channel MOS transistors 3 and 4 are not connected in common, the output B of the level shift circuit 17 is set to a constant voltage by the transistors 3 and 9 at a low frequency. Further, the phase of the voltage at point B is VR
Although it has a delay of 90 degrees with respect to the phase of the EF, the gain is very small at low frequencies, so that the overall characteristics are not affected. However, at higher frequencies, the effect of a 90-degree phase delay due to the P-channel MOS transistor 1 begins to appear due to an increase in gain, and the phase recovery in a high frequency band is performed by the 90-degree phase delay.

The frequency characteristics of the gain and phase in the feedback loop of VINT and the frequency characteristics of the gain (gain B) and the phase (phase B) between point B and VINT in the constant voltage generation circuit of the present embodiment are shown by the Bode lines in FIG. This will be described with reference to the drawings. Since there is almost no gain B in the low frequency band, the gain and phase of the feedback loop are hardly affected. However, when the frequency is around 1 MHz, the gain B is 0 dB.
, The phase of the feedback loop is recovered compared to the first embodiment. As a result, the first
The phase margin, which was about 45 degrees in the embodiment, has recovered to about 85 degrees in the present embodiment. (Third Embodiment) FIG. 5 is a circuit diagram of a constant voltage generating circuit according to a third embodiment of the present invention. The same numbers as those in FIG. 3 indicate the same components.

This embodiment is different from the second embodiment shown in FIG. 3 in that the level shift circuit 17 is replaced by a level shift circuit 57 and the level shift circuit 38 is replaced by the level shift circuit 5.
8 is replaced. The level shift circuit 57
For the level shift circuit 17, the place where the output voltage is taken out is set to n from the drain of the n-channel MOS transistor 3.
It is changed to the source of the channel MOS transistor 3. The level shift circuit 58 includes the level shift circuit 3
8, the output voltage is taken out from the n-channel MO
In this example, the drain of the S transistor 4 is changed to the source of the n-channel MOS transistor 4. In the present embodiment, the location where the output voltage is extracted is changed so that the output voltages of the level shift circuits 17 and 18 can be set lower. Therefore, even when the optimum point of the current mirror amplifier 19 becomes a low level, it is possible to cope with it. It becomes possible.

In the second embodiment, the phases between the input and output of the bell shift circuits 17 and 38 are opposite to each other with a phase difference of 180 degrees, but in this embodiment, the level silt circuits 57 and
The phase between the input and output 8 is the same. Therefore, the output voltage of the level shift circuit 57 is input to the gate of the n-channel MOS transistor 8, and the output voltage of the level shift circuit 58 is input to the gate of the n-channel MOS transistor 7. (Fourth Embodiment) FIG. 6 shows a circuit diagram of a constant voltage generation circuit according to a fourth embodiment of the present invention. The same numbers as those in FIG. 1 indicate the same components. In this embodiment, the level shift circuits 17 and 18 are replaced by level shift circuits 67 and 68 in the first embodiment of FIG.

The level shift circuit 67 is different from the level shift circuit 17 in that the P-channel MOS transistor 1 is replaced with a resistor 61. Level shift circuit 68
Is a P-channel MOS for the level shift circuit 18.
The transistor 2 is replaced with a resistor 62. In the present embodiment, the output voltages of the level shift circuits 67 and 68 are adjusted to the optimum operating point of the current mirror amplifier 19 by keeping the sizes of the n-channel MOS transistors 3 and 4 optimal and setting the values of the resistors 61 and 62 freely. Can be set. Similar effects can be obtained by using one or more diodes connected in series instead of the resistors 61 and 62. Further, instead of the resistors 61 and 62,
The same effect can be obtained by using an n-channel MOS transistor whose drain and gate are connected.

In this embodiment, p of the first embodiment is used.
Channel MOS transistors 1 and 2 are connected to resistors 61 and 6
2. Although one or more diodes connected in series and an n-channel MOS transistor having a drain and a gate connected are replaced, the same can be applied to the second and third embodiments. In the first to fourth embodiments, VREF is a positive voltage. However, the present invention is not limited to this.
By replacing the n-channel MOS transistor that inputs EF to the gate with a p-channel MOS transistor, a negative voltage VREF can be used.

[0033]

As described above, the present invention has the following effects. (1) In the first level shift circuit, it is necessary to increase the current drivability of the reference potential generation circuit by greatly reducing the current flowing from the reference potential by receiving the reference potential only at the gate of the first transistor. Because there is no
The chip area can be reduced, and stable voltage supply can be performed. (2) The output voltage from the first level shift circuit is
And the output voltage from the second level shift circuit is determined by the setting of the voltage step-down means, the first transistor, and the first constant current source.
By determining by setting the first or second constant current source, the output voltages from the first and second level shift circuits can be set freely, and the current mirror amplifier is operated at an optimum operating point. be able to.

(3) According to the third and fourth aspects of the present invention, the output voltage from the first level shift circuit is obtained from the source of the first transistor, and the output voltage from the second level shift circuit is obtained. , From the source of the second transistor. Therefore, the output voltage can be set lower than in the case where the output voltage is obtained from the drains of the first and second transistors,
Even if the optimum operating point of the current mirror amplifier becomes a low level, it can be handled. (4) In the invention according to claims 2 and 4, the first and second level shift circuits are provided with first and second constant current sources, respectively.
The output voltage from the first level shift circuit is determined by setting the first voltage step-down means, the first transistor, and the first constant current source, and the output voltage from the second level shift circuit is set to the second voltage shift circuit. Of the voltage step-down means, the second transistor, and the second constant current source.
Therefore, since the phase of the output voltage of the first level shift circuit in the high frequency band can be recovered, the phase margin of the feedback loop can be further improved.

(5) According to a sixth aspect of the present invention, a signal having the same phase as the internal step-down power supply voltage is input to the first input terminal of the current mirror amplifier by the first phase compensation capacitor, and the second phase compensation is performed. A signal having the same phase as the reference potential is input to a second input terminal of the current mirror amplifier by a capacity for use. Therefore, it is possible to compensate for a phase delay caused by the first and second level shift circuits and to suppress a decrease in gain.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a constant voltage generation circuit according to a first embodiment of the present invention.

FIG. 2 is a Bode diagram of the constant voltage generation circuit of FIG.

FIG. 3 is a circuit diagram of a constant voltage generation circuit according to a second embodiment of the present invention.

FIG. 4 is a Bode diagram of the constant voltage generation circuit of FIG. 3;

FIG. 5 is a circuit diagram of a constant voltage generation circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a constant voltage generation circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a conventional constant voltage generation circuit.

[Explanation of symbols]

 1, 2 p-channel MOS transistor 3, 4 n-channel MOS transistor 5, 6 p-channel MOS transistor 7, 8 n-channel MOS transistor 9, 10 n-channel MOS transistor 11, p-channel MOS transistor 12, 13 phase compensation capacitor 14 reference potential Generation circuit 15 DRAM internal circuit 16 Phase compensation circuit 17, 18 Level shift circuit 19 Current mirror amplifier 30, 31 N-channel MOS transistor 38, 57, 58, 67, 68 Level shift circuit 101, 102 N-channel MOS transistor 103, 104 Phase Compensation capacitor 105 Reference potential drive circuit 107, 108 Level shift circuit 109 Current mirror amplifier

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 27/088

Claims (9)

[Claims] 1. A constant voltage generating circuit that generates an internal step-down power supply voltage that is lower than the external power supply voltage from an external power supply voltage, wherein: a reference potential generation circuit that generates a reference potential from the external power supply voltage; A first transistor whose base is input, a first constant current source connected between the source of the first transistor and the ground, a drain of the first transistor and the external power supply voltage. A first level shifter provided between the first voltage shifter and a first voltage step-down means for stepping down the external power supply voltage, wherein the first level shift circuit uses a drain voltage of the first transistor as an output voltage; A second transistor input to the base and having a source connected to the first constant current source;
And a second voltage step-down unit provided between the drain of the second transistor and the external power supply voltage for stepping down the external power supply voltage. The voltage at the drain of the second transistor is used as an output voltage. A second level shift circuit; a first and a second input terminal; an output voltage from the first level shift circuit being input to the first input terminal; A current mirror amplifier that inputs the output voltage of the first input terminal to the second input terminal, differentially amplifies and outputs a voltage between the first input terminal and the second input terminal, And a third transistor having a gate supplied with the output voltage, a source supplied with the external power supply voltage, and a drain outputting the internal step-down power supply voltage. Generating circuit. 2. A constant voltage generation circuit for generating an internal step-down power supply voltage lower than the external power supply voltage from an external power supply voltage, wherein: a reference potential generation circuit for generating a reference potential from the external power supply voltage; A first transistor whose base is input, a first constant current source connected between the source of the first transistor and the ground, a drain of the first transistor and the external power supply voltage. A first level shifter provided between the first voltage shifter and a first voltage step-down means for stepping down the external power supply voltage, wherein the first level shift circuit uses a drain voltage of the first transistor as an output voltage; A second transistor input to a base, a second constant current source connected between a source of the second transistor and ground, and a second transistor A second voltage step-down means provided between the drain of the second transistor and the external power supply voltage for stepping down the external power supply voltage, the second level having a drain voltage of the second transistor as an output voltage. A shift circuit, and a first and a second input terminal. An output voltage from the first level shift circuit is input to the first input terminal, and an output voltage from the second level shift circuit is input to the first input terminal. A current mirror amplifier that inputs to the second input terminal, differentially amplifies and outputs a voltage between the first input terminal and the second input terminal, and an output voltage from the current mirror amplifier is A third transistor having a gate, a source receiving the external power supply voltage, and a drain outputting the internal step-down power supply voltage. 3. A constant voltage generation circuit for generating an internal step-down power supply voltage lower than the external power supply voltage from an external power supply voltage, wherein: a reference potential generation circuit for generating a reference potential from the external power supply voltage; A first transistor whose base is input, a first constant current source connected between the source of the first transistor and the ground, a drain of the first transistor and the external power supply voltage. A first voltage step-down means provided between the first voltage step-down means for stepping down the external power supply voltage, the first level shift circuit using a source voltage of the first transistor as an output voltage, and the internal step-down power supply voltage A second transistor input to the base and having a source connected to the first constant current source;
And a second voltage step-down means provided between the drain of the second transistor and the external power supply voltage for stepping down the external power supply voltage, wherein a voltage at a source of the second transistor is an output voltage. A second level shift circuit; a first and a second input terminal; an output voltage from the first level shift circuit being input to the first input terminal; A current mirror amplifier that inputs the output voltage of the first input terminal to the second input terminal, differentially amplifies and outputs a voltage between the first input terminal and the second input terminal, And a third transistor that receives the external power supply voltage at its source, inputs the external power supply voltage at its source, and outputs the internal step-down power supply voltage from its drain. Raw circuit. 4. A constant voltage generation circuit for generating an internal step-down power supply voltage lower than the external power supply voltage from an external power supply voltage, wherein: a reference potential generation circuit for generating a reference potential from the external power supply voltage; A first transistor whose base is input, a first constant current source connected between the source of the first transistor and the ground, a drain of the first transistor and the external power supply voltage. A first voltage step-down means provided between the first voltage step-down means for stepping down the external power supply voltage, the first level shift circuit using a source voltage of the first transistor as an output voltage, and the internal step-down power supply voltage A second transistor input to a base, a second constant current source connected between a source of the second transistor and ground, and the second transistor And a second voltage step-down means provided between the drain of the second transistor and the external power supply voltage for stepping down the external power supply voltage, wherein the second level shifter uses the source voltage of the second transistor as an output voltage. And a first and a second input terminal. An output voltage from the first level shift circuit is input to the first input terminal, and an output voltage from the second level shift circuit is input to the first input terminal. A current mirror amplifier that inputs a second input terminal and differentially amplifies and outputs a voltage between the first input terminal and the second input terminal; an output voltage from the current mirror amplifier is gated And a third transistor that inputs the external power supply voltage to a source and outputs the internal step-down power supply voltage from a drain. 5. The current mirror amplifier comprises: a third transistor having a source connected to the external power supply voltage and a gate and a drain connected; a source connected to the external power supply voltage; and a gate connected to the third power supply voltage. A fourth transistor connected to a gate of the transistor and having a drain voltage as an output voltage, an output voltage from the first level shift circuit being input to a gate, and a drain connected to a drain of the third transistor; A fifth transistor, a gate to which an output voltage from the second level shift circuit is input, a drain connected to the drain of the fourth transistor, and one terminal connected to the fifth transistor. And the source of the sixth transistor and the source of the sixth transistor in common,
And a third constant current source having the other terminal connected to the ground. 6. A first phase compensation capacitor provided between a gate of the second transistor, a first input terminal of the current mirror amplifier, a gate of the first transistor, 6. The constant voltage generation circuit according to claim 1, further comprising a second phase compensation capacitor provided between the current input terminal and the second input terminal of the current mirror amplifier. 7. The first and second voltage step-down means,
7. The constant voltage generating circuit according to claim 1, wherein the constant voltage generating circuit is a transistor having a gate and a drain connected to each other. 8. The first and second voltage step-down means,
7. The constant voltage generation circuit according to claim 1, wherein the constant voltage generation circuit is a resistance element. 9. The first and second voltage step-down means,
The constant voltage generating circuit according to claim 1, wherein the constant voltage generating circuit is one or more diodes connected in series.