JPH1146135A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the effect of output noise by logically outputting data of '0' and '1' alternately by each I/O before outputting normal data of output. SOLUTION: Although a WRB signal which is normal data is inputted to an output buffer circuit 100, in a pseudo output buffer circuit 200, a power supply in the case of an odd I/O and a GND in the case of an even I/O are fixed respectively. In the case of an output state (an output enable signal OE is on a Low level), a signal Q becomes High, and when the circuit 200 is selected, data '1' in the case of an odd I/O and data '0' in the case of an even I/O are outputted. Data of '1' or '0' are alternately outputted from each I/O before the normal data are outputted at the time of output. Thereby, the probability that output data change in each I/O in the same way is reduced, and output noise can be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device having a plurality of bits, and more particularly to a semiconductor integrated circuit device having reduced influence of output noise.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device,
At the time of I / O output (output from an external terminal), normal data from the inside is read as it is, and "0" or "1" data is output from each I / O. At this time, in some cases, the same data may be output from all I / Os, and the data may be all inverted in the next read.

[0003]

As described above, when data is inverted from "0" to "1" or "1" to "0" in all I / Os at the time of I / O output, the power supply And the fluctuation of GND may increase, and as a result, a malfunction may occur at the time of reading due to the influence of output noise.

Therefore, a semiconductor integrated circuit device of the present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor integrated circuit device that reduces the influence of output noise.

[0005]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention has a plurality of bits,
In a semiconductor integrated circuit device which logically outputs data of "0" or "1" at the time of / O output, data of "0" and "1" are alternately output at each I / O before output of normal data. Is logically issued.

[0006]

Embodiments of the present invention will be described below. At the time of I / O output, usually "0" or "1"
Is output directly from each I / O.
In this case, for example, the same data is output from all I / Os,
In the next read, all of them are inverted, and all I / O
Output data reverse to the previous one. As described above, when the output data is inverted in all the I / Os, the fluctuation of the power supply and the GND is the largest, and the influence of the output noise is also increased. Therefore, in the present invention,
After outputting data from the I / O and before outputting the next data, be sure to alternately output "0" or "1" at each I / O so that the output data is not simultaneously inverted in all I / Os. "
Of data. The reason why the data “0” or “1” is output alternately is to make the fluctuations of the power supply and the GND easily cancel each other.

In the embodiment of the present invention, two output buffer circuits are provided for each I / O, and normal data is supplied from one output buffer circuit (100 in FIG. 1) to another output buffer circuit (FIG. 1). 1 200), odd-numbered I / O outputs "1" and even-numbered I / O outputs "0", and either of these output buffer circuits is selected by an internal pulse (Q in FIG. 1). Is done.

For this reason, when the read data is updated, two output change points occur. However, all the I / Os simultaneously change from "0" to "1" (or "1" to "0"). There is no combination that maximizes the time change (di / dt) of the current.

For example, when the outputs of all I / Os are inverted,
Half of them must be "0" to "1", and the other half must be "1"
To "0", and the generation of output noise is greatly reduced.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of one embodiment of the present invention. Referring to FIG. 1, in one embodiment of the present invention, a normal output buffer circuit 100 and another output buffer circuit (referred to as "pseudo output buffer circuit") 200 are arranged in parallel with the output buffer circuit 100. And one of the output buffer circuits is selected by the signal Q.

The output buffer circuit 100 includes a push-pull output stage transistor composed of a PMOS transistor 8 and an NMOS transistor 10, a WRB signal, an inverted signal of the output enable signal OE by the inverter 1, and an inverted signal of the signal Q by the inverter 2. And a NAND circuit 4 for outputting the NAND of these to the gate terminal of the PMOS transistor 8, and a NOR gate for receiving the WRB signal, the output enable signal OE, and the signal Q and inputting the NOR of these to the gate terminal of the NMOS transistor 10. And a NOR circuit 6 for outputting. The pseudo output buffer circuit 200 includes a push-pull output stage transistor including a PMOS transistor 9 and an NMOS transistor 11, a fixed potential (power supply potential for odd I / O, ground potential for even I / O), and output enable. Signal OE
And a NAND circuit 5 which receives an inverted signal from the inverter 1 and the signal Q and outputs a NAND of these signals to the gate terminal of the PMOS transistor 9 and a fixed potential (odd I /
Power supply potential for O, ground potential for even I / O),
The output enable signal OE and the inverted signal of the signal Q by the inverter 3 are input and the NOR of these signals is output to the NMOS.
NOR circuit 7 for outputting to the gate terminal of transistor 11
And

The output buffer circuit 100 receives a WRB signal as normal data. In the pseudo output buffer circuit 200, in the case of an odd I / O, an even I / O is supplied to the power supply.
In the case of O, each is fixed to GND.

In the output state (output enable signal OE)
Is low level), the signal Q becomes High, and the pseudo output buffer circuit 200 is selected, data of "1" is output in odd I / O, and data of "0" is output in even I / O.

FIG. 2 is a timing chart showing changes in input / output signals in one embodiment of the present invention. The signal Q is an internal pulse signal, and an appropriate pulse is input before normal data is output.

When the signal Q is low, the output buffer circuit 100 is selected, and normal data to be read is output from each I / O. That is, when the signal Q is Low, in the pseudo output buffer circuit 200, the output of the NAND circuit 5 is High, the output of the NOR circuit 6 is Low, and P
The MOS transistor 9 and the NMOS transistor 11 are turned off, and the output of the pseudo output buffer circuit 200 becomes a high impedance state. On the other hand, in the output buffer circuit 100, when the output enable signal OE is Low, the NAND circuit 4 inverts the WRB signal. The signal NOR circuit 6 outputs an inverted signal of the WRB signal, and WRB is "1".
, The PMOS transistor 8 is turned on and the output terminal (O
UT1 / 2), when High and WRB are “0”, NM
The OS transistor 8 turns on, and Low is output to the output terminal.

On the other hand, when the signal Q is High, the pseudo output buffer circuit 200 is selected, regardless of the output data of the previous cycle, "1" data from odd I / O and "1" from even I / O. 0 "data is output. OUT1 and OUT2 show the output waveforms.
This is a waveform when OUT1 is an odd I / O and when OUT2 is an even I / O.

As described above, during output, data of "0" or "1" is alternately output at each I / O before outputting normal data, so that output data is the same at each I / O. The probability of change can be reduced, and output noise can be reduced.

FIG. 3 shows a circuit configuration of a second embodiment of the present invention. In FIG. 3, reference numeral 101 denotes an odd I / O output buffer circuit, and 201 denotes an even I / O output buffer circuit. Also in this embodiment, in terms of timing,
As shown in FIG. 2, the output data is controlled by the signal Q. When the signal Q is Low, read normal data coming from the WRB is output for each I / O,
When the signal Q is High, data of "1" is output at odd I / O and data of "0" at even I / O.

The odd I / O output buffer circuit 101
PMOS transistor 20 and NMOS transistor 25
A transfer gate which is turned on when the signal Q is low and transmits a WRB signal; and a PM which has an inverted signal of the signal Q by the inverter 12 as a gate input, a source connected to a power supply, and a drain commonly connected to an output of the transfer gate.
An input signal N is input to the OS transistor 21, the inverted signal of the output enable signal OE by the inverter 13, and the connection point between the transfer gate and the PMOS transistor 21.
An AND circuit 16, a NOR circuit 18 which receives an output enable signal OE and a connection point between the transfer gate and the PMOS transistor 21, and a NAND circuit 16, N
PMO using the output of the OR circuit 18 as the gate input
An output transistor including an S transistor 22 and an NMOS transistor 26 is provided.

The output buffer circuit 201 of the even I / O
Is a transfer gate composed of a PMOS transistor 23 and an NMOS transistor 27, which is turned on when the signal Q is Low and transmits a WRB signal, and which has the signal Q as a gate input, connects the source to the ground, and connects the drain to the output of the transfer gate. NMOS transistor 28
A NAND circuit 17 which receives an inverted signal of the output enable signal OE by the inverter 15 and a connection point of the transfer gate and the NMOS transistor 28; and an output enable signal OE, the transfer gate and N
A NOR circuit 19 having a connection point of the MOS transistor 28 as an input, a PMOS transistor 24 having an output of the NAND circuit 17 and the NOR circuit 19 as a gate input,
It is composed of an output stage transistor composed of an NMOS transistor 29.

In this embodiment, as compared with the first embodiment, since only one output buffer circuit is required for each I / O, the area is considerably reduced.

[0022]

As described above, according to the present invention, when outputting a semiconductor integrated circuit device having a plurality of bits,
By making it possible to reduce the probability that the output data changes in each I / O in the same manner, it is possible to reduce the output noise, and as a result, it is possible to avoid the occurrence of a malfunction.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention.

[Explanation of symbols]

 1-3, 12-15 Inverter 4, 5, 16, 17 NAND 6, 7, 18, 19 NOR 8, 9, 20-24 PMOS transistor 10, 11, 25-29 NMOS transistor

Claims (3)

[Claims] 1. A semiconductor integrated circuit device having a plurality of bits and outputting logical "0" or "1" data at the time of I / O output. I
A semiconductor integrated circuit device wherein data of "0" or "1" is alternately output by / O. 2. A semiconductor integrated circuit device having a plurality of data output terminals, wherein: an output buffer circuit that outputs data to the output terminals is:
Means for controlling transmission of normal data or a fixed logic level from an internal circuit to an output buffer according to a value of a control signal, wherein the fixed logic level is a first fixed logic level and an even-numbered output terminal for odd-numbered output terminals Is set to a second fixed logic level complementary to the first fixed logic level, and at the time of data output, the output buffer circuit outputs the fixed logic level before outputting normal data. , Followed by the output of regular data. 3. A semiconductor integrated circuit device having a plurality of data output terminals, wherein two first and second output buffer circuits are arranged in parallel for one output terminal, and Is input with normal data from an internal circuit. The second output buffer circuit has a first fixed logic level for odd-numbered output terminals and a first fixed logic level for even-numbered output terminals. Complementary second fixed logic levels are input, and the outputs of the first and second output buffer circuits are commonly connected to the one output terminal.
One of the second output buffer circuits is selected, the output of the non-selected output buffer circuit is turned off, and at the time of data output, each of the first output buffer circuit outputs the normal data before outputting the normal data. A semiconductor integrated circuit device wherein data "0" or "1" is output from a data output terminal.