JPH1145868A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

[PROBLEMS] To improve the uniformity of the remaining film thickness of a polishing film in a CMP process. SOLUTION: A member such as wiring is formed in a product chip region 3 where a product chip 2 is formed in an effective processing region 6 of a wafer 1, and an incomplete pseudo chip 4 which does not become a product is formed. In region 5, product chip region 3
A member having the same pattern as that of the member formed in the above is formed. Further, the pattern of the members formed in the pseudo chip region 5 may be a simple shape pattern having the same or similar density as the pattern density of the pattern of the members formed in the product chip region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the same, and more particularly, to a method for manufacturing a semiconductor integrated circuit device.
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device including a planarization process to which an MP (Chemical Mechanical Polishing) method is applied.

[0002]

2. Description of the Related Art As the minimum processing size of a semiconductor integrated circuit device decreases, it is necessary to improve the performance of a stepper, and the aperture diameter of a lens and the exposure wavelength are shortened. As a result, the depth of focus of the exposure optical system becomes shallow, and slight irregularities on the surface to be processed also pose a problem. As a result, planarization of the surface to be processed is an important technical problem in device processing. Moreover, the above-mentioned flattening is not flattening for the purpose of alleviating the step shape required for preventing disconnection of the wiring formed on the step, but global flattening, that is, complete flattening is required. Things.

As a technique for flattening a surface, SOG (spin
on glass) film or low melting glass, coating and melting, heat treatment by glass flow, CVD (Ch
There is known a method of applying self-planarization by applying a surface reaction mechanism of (emical vapor deposition) .However, complete planarization, that is, global In many cases, planarization cannot be performed. Therefore, as a technique capable of completely flattening practically, an etch back method and a CMP method are used.
The law looks promising.

[0004] The etch-back method uses a photoresist as a sacrificial film, an SOG film, a self-planarizing CV.
Although a method using a D film is known, the complexity of the process, cost, and a decrease in yield due to particles are problematic. On the other hand, the CMP method is generally superior in comparison with the problem of the etch-back method. The perception that this is a well-established process is generally forming. In other words, the CMP method is considered to be the most promising as a practical technique that can realize complete flattening.

[0005] An example of a detailed description of the CMP technique is, for example, "Electronic Materials", May, 1996, p.

[0006]

However, in the process of studying a device surface flattening technique to which the CMP method is applied, the present inventor has recognized the following problems.

That is, it has been observed that the remaining film thickness of the polishing film polished by the CMP method becomes large in the peripheral region of the semiconductor wafer, thereby impairing the uniformity of the polishing film. Such non-uniformity of the polishing film may reduce the exposure margin and the etching margin in photolithography in a subsequent step, and may cause a reduction in the manufacturing yield of the semiconductor integrated circuit device.

An object of the present invention is to improve the uniformity of the remaining thickness of a polishing film in a CMP process.

It is another object of the present invention to improve an exposure margin and an etching margin in a photolithography process after a CMP process, and to improve a manufacturing yield of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein a product chip region located in an effective processing region of a semiconductor wafer and in which product chips constituting the semiconductor integrated circuit device are formed, and a semiconductor wafer Located on the outer periphery of
A method for manufacturing a semiconductor integrated circuit device for processing a semiconductor wafer including a pseudo chip region in which an incomplete pseudo chip that does not become a product chip is formed, wherein a conductive element forming a semiconductor integrated circuit device in the product chip region Simultaneously with forming the constituent members, a first step of forming a pseudo member made of the same material as the element constituent members in the pseudo chip region, and depositing an insulating film covering the element constituent members and the pseudo members over the entire surface of the semiconductor wafer And a second step of polishing the insulating film by a CMP method.

According to such a method of manufacturing a semiconductor integrated circuit device, in the first step, not only the element forming member is formed in the product chip region but also the pseudo member is formed in the pseudo chip region. In the step, since the insulating film formed on both the element forming member and the pseudo member is polished by the CMP method, the uniformity of the remaining film thickness of the insulating film after the CMP can be improved.

That is, when the pseudo member is not provided in the pseudo chip region, a film or the like for forming the element forming member remains in the pseudo chip region without being patterned at all, and the insulating film in the pseudo chip region becomes This means that the entire surface is in a convex state in the region. Therefore, in the pseudo chip region, the pressure received from the polishing pad during the CMP polishing is applied to the entire surface of the flat insulating film, and the pressure per unit area applied to this region decreases. That is, since the insulating film on the patterned element forming member has a surface shape according to the unevenness of the element forming member, and the pressure received from the polishing pad is received only by the convex portion, the applied pressure per unit area However, the applied pressure is relatively low in the pseudo chip region. Since the polishing rate is generally proportional to the applied pressure, the difference in the applied pressure causes the remaining thickness of the insulating film to be non-uniform.

If the non-uniformity of the insulating film is limited only to the pseudo chip region, no problem occurs because the pseudo chip formed in this region does not become a product.
The non-uniformity extends to product chips adjacent to the pseudo chip. Therefore, this is a factor that reduces the yield of product chips adjacent to the pseudo chip.

Therefore, in the present invention, patterning is performed even in the pseudo chip region to form a dummy pseudo member. By providing the pseudo member in this manner, it is possible to prevent a decrease in the polishing pressure during the CMP polishing of the insulating film on the pseudo member, and to improve the uniformity of the remaining film thickness of the insulating film. As a result, the thickness uniformity of the insulating film of the product chip adjacent to the pseudo chip can be improved, and the product yield of the chip can be improved.

As the element forming member, an active region of a semiconductor substrate having a shallow trench element isolation structure, a polycrystalline silicon wiring serving as a gate electrode on a gate insulating film, a metal or polycrystalline silicon wiring on an interlayer insulating film are used. Examples can be given.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein a product chip region located in an effective processing region of a semiconductor wafer and in which product chips constituting the semiconductor integrated circuit device are formed, and a semiconductor wafer Located on the outer periphery of
A method of manufacturing a semiconductor integrated circuit device for processing a semiconductor wafer including a pseudo chip region in which an incomplete pseudo chip that does not become a product chip is formed, wherein the conductive film forming the semiconductor integrated circuit element is formed on an insulating film in the product chip region. Forming a recess in which a conductive element constituent member is formed, and simultaneously forming a pseudo recess in the insulating film in the peripheral chip region, and a surface of the insulating film including the recess and the inner surface of the pseudo recess in the entire surface of the semiconductor wafer And forming a conductive element forming member in the recess by polishing the conductive film by a CMP method.

According to such a method of manufacturing a semiconductor integrated circuit device, in the first step, not only a recess for forming an element component in the product chip region is formed in the insulating film but also in the pseudo chip region. In the second step, a conductive film is formed on the surface of the insulating film including the concave portion and the inner surface of the pseudo concave portion, and the conductive film is polished by a CMP method. As a result, the element constituent members can be formed uniformly.

The reason why the conductive film can be uniformly polished is the same as the reason why the insulating film is uniformly polished as described in the above (1).

The element constituent member may be a tungsten plug or a wiring by a damascene method, and the concave portion may be a connection hole for forming a plug or a groove for forming a wiring. Further, since the recess includes both the connection hole and the wiring groove, the formation of the connection hole and the wiring by a so-called dual damascene method is also included. Further, examples of the conductive film include polycrystalline silicon in addition to a metal film such as aluminum and copper.

(3) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to the above (1) or (2), wherein the pattern of the pseudo member or the pseudo recess in the pseudo chip region is provided. Is the same as the pattern of the element constituent member or the concave portion in the product chip area.

According to such a method of manufacturing a semiconductor integrated circuit device, in order to make the pseudo member or the concave portion pattern in the pseudo chip region the same as the element constituent member or the concave portion pattern in the product chip region, the voltage is applied in both regions. The pressure per unit area is the same and the CM of the insulating film or metal film
The P polishing rate can be made uniform.

Further, the pattern density of the pseudo member or the concave portion in the pseudo chip region is not limited to the pattern of the pseudo chip region being the same as the pattern of the product chip region. It can be the same or close to the density. In this way, not only by making the patterns of the pseudo chip region and the product chip region the same, but also by making the densities the same or similar, the polishing pressure per unit area applied to both regions can be substantially reduced. It can be the same, CM of insulating film or metal film
The P polishing rate can be made uniform.

Further, according to experiments and studies by the present inventors, practical uniformity can be obtained even when the following conditions are satisfied. That is, the pattern density N1 of the pseudo member or the pseudo recess in the pseudo chip region
Is defined as 0.5 × N2 ≦ N1 ≦ 2 × N with respect to the pattern density N2 of the element constituent member or the concave portion in the product chip area.
This is a case where both the first condition of 2 and the second condition of 0.1 ≦ N1 ≦ 0.8 are satisfied. That is, the pattern density N1 of the pseudo chip region is
50% to 200 of pattern density N2 in product chip area
%, And does not need to exactly match or approximate N2. However, the pattern density N1 of the pseudo chip region needs to be between 10% and 80%. For example, when the pattern density N2 of the product chip area is 20%, the pattern density N1 of the pseudo chip area is 10%.
% To 40%. However, N2 is 10%
, N1 needs to be in the range of 10% to 20%, and when N2 is 50%, N1 needs to be in the range of 25% to 80%.

Further, the pattern size of the pseudo member or the pseudo concave portion can be not less than twice the pattern width of the element constituting member or the concave portion and not more than 1 mm. In such a case, since the pattern size of the pseudo member or the concave portion is twice or more the pattern width of the element constituent member or the concave portion, it is possible to prevent dust generation factors such as pattern collapse in the pseudo chip region. That is, since the pseudo member or the pseudo concave portion is formed outside or over the effective processing region outside the process control range in the wafer processing step, lithography or etching is not performed well. In particular, if the metal film is not etched well in the wiring forming step, the metal pieces may peel off from the wafer and become conductive dust, which may cause a defect. Therefore, in the present invention, the pattern size of the pseudo member or the pseudo concave portion is set to be at least twice the pattern width of the element constituent member or the concave portion, thereby preventing separation of these members and suppressing the occurrence of defects in the manufacturing process of the semiconductor integrated circuit device. Things. However, if the pattern size of the pseudo member or the pseudo concave portion is too large, the effect of patterning may be weakened.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing an example of a wafer to which a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention is applied, and FIG.
It is an enlarged view of a part.

The wafer 1 used in the manufacturing method according to the first embodiment has a product chip area 3 where a product chip 2 is formed.
And a pseudo chip region 5 where an incomplete pseudo chip 4 that does not become a product is formed. The product chip 2 has an effective processing area 6 in which process management in each manufacturing process is guaranteed.
Formed within. Conversely, in a region outside the effective processing region 6, the product chip 2 cannot be formed, and all chips formed in such a region become the pseudo chip 4,
It is discarded after the end of the process. Therefore, the thin film formed in the pseudo chip region 5 is generally not patterned, and is left as a solid film.

However, in the wafer 1 of the present embodiment, as shown in FIG. 2, even in the pseudo chip region 5, the same pattern 7 as the pattern 7 of the product chip 2 is formed on the pseudo chip 4.
Is patterned. By forming the pattern 7 on the pseudo chip 4 as well, the uniformity of the amount of CMP of the insulating film on the pattern can be improved, and the uniformity of the remaining film thickness of the insulating film can be improved.

Hereinafter, the first embodiment will be described with reference to FIGS.
Will be described. 3 to 7 are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, and FIG.
FIG. 1B is a cross-sectional view taken along line a-b of FIG. 1.

First, a silicon nitride film (not shown) is deposited on the main surface of the wafer 1, and after patterning the silicon oxide film, a thermal oxidation process is performed using the patterned silicon oxide film as a mask, and a thick silicon oxide film is formed. A field insulating film 8 is formed. The well 9 is formed by ion-implanting a low concentration impurity. Thereafter, a silicon oxide film serving as the gate insulating film 10 is sequentially deposited by, for example, a thermal CVD method, a polycrystalline silicon film serving as the gate electrode 11 is deposited, for example, by an LPCVD method, and a silicon oxide film serving as a cap insulating film 12 is sequentially deposited, for example, by a plasma CVD method. And patterning the laminated film to form the gate insulating film 1
0, a gate electrode 11, and a cap insulating film 12 are formed.
Further, the impurity is ion-implanted using the gate electrode 11 and the cap insulating film 12 as a mask, and
To form Thereafter, a silicon oxide film is deposited, and is subjected to anisotropic etching to form a sidewall 14 (FIG. 3). Note that the cap insulating film 12 and the sidewalls 14 may be silicon nitride films.

For patterning the laminated film, known photolithography and etching techniques can be used.
After the sidewalls 14 are formed, high-concentration impurities are ion-implanted so that the impurity semiconductor regions 13 are LDD (Lightly Doped).
Drain) structure may be used. When the MISFET formed in the above step is of n-type conductivity, the impurity introduced into the well 9 is a p-type impurity such as boron, and the impurity introduced into the impurity semiconductor region 13 is n-type such as phosphorus or arsenic. Can be shaped impurities. If the conductivity type of the MISFET is p-type, the reverse can be achieved.

The MISFET has a product chip area of 3
And is not formed in the pseudo chip region 5.

Next, after an insulating film 15 is deposited on the entire surface of the wafer 1, the insulating film 15 is planarized by using an etch-back method, a CMP method or the like. The insulating film 15 can include a film having a self-planarizing function such as a BPSG film, an SOG film, or a silicon oxide film formed by a high-density plasma CVD method. In this case, in order to prevent diffusion of impurities such as boron and phosphorus, CVD using TEOS, for example, on the MISFET side is performed.
A silicon oxide film formed by a method can be included. Further, after opening the connection hole 16, a metal film to be the wiring 17 is deposited, and the metal film is patterned using a known photolithography and etching technique to form the wiring 17. Further, an insulating film 18 covering the wiring 17 is deposited (FIG. 4).

The wiring 17 can be, for example, a metal film containing aluminum as a main component, and can be deposited by a sputtering method or an evaporation method. At the time of this deposition, a film is simultaneously deposited in the connection hole 16, and the wiring 17 can be connected to the impurity semiconductor region 13 on the main surface of the wafer 1.

The wiring 17 is formed not only in the product chip area 3 but also in the pseudo chip area 5.
This is one of the patterns 7 described in FIG. By forming the wiring 17 also in the pseudo chip region 5, the uniformity of the remaining film thickness of the insulating film 18 after the CMP of the insulating film 18 can be improved as described later.

The insulating film 18 can include a film having a self-planarizing function such as a BPSG film, an SOG film, or a silicon oxide film formed by a high-density plasma CVD method.
It can also be a laminated film with a silicon oxide film or the like by a CVD method using EOS.

Next, the surface of the insulating film 18 is polished by the CMP method (FIG. 5). As shown in FIG.
Then, the convex portion of the insulating film 18 at the boundary between the pseudo chip region 5 and the product chip region 3 comes into contact with the polishing pad 19 with a length of 12 L (FIG. 5A), and the insulation at the boundary between the product chip regions 3 is formed. The protruding portion of the film 18 also has a length of 12 L and is in contact with the polishing pad 19 (FIG. 5B). This is because the wiring 17 is formed in the pseudo chip region 5 in the same pattern as the pattern of the product chip region 3, and thus the insulating film 18 and the polishing pad 19 are in contact with the same area. Therefore, the polishing rate of the insulating film 18 can be made uniform regardless of the location of the pseudo chip region 5 or the product chip region 3.

That is, in CMP polishing, generally, the polishing rate R depends on the pressure Ps applied to the sliding surface and the wafer 1
And a relative velocity v between the polishing pad 19 and the polishing pad 19, and R
= Kp × Ps × v (Kp is a coefficient). Therefore, when the pressure Ps decreases, the polishing rate R decreases in proportion thereto, and the remaining film thickness of the insulating film 18 increases.

For the sake of simplicity, assuming that the wiring 17 in FIG. 5 is a simple line and space, and assuming that the pattern density does not change in the direction perpendicular to the paper, the pressure Ps per unit area applied to the sliding surface is Is given as a value obtained by dividing the uniform applied pressure P applied to the back surface of the wafer 1 by the contact area, and becomes P / 12L. This value is the same at the boundary between the pseudo chip region 5 and the product chip region 3 (FIG. 5A) and at the boundary between the product chip regions 3 (FIG. 5B). This shows that the polishing rate of the insulating film 18 by polishing is not different.

On the other hand, consider the case where the solid pattern 20 of the wiring 17 is left in the pseudo chip region 5 as shown in FIG. 17, and as shown in FIG.
The pressure Ps per unit area at the boundary between the product chip region 3 and P / 21L is P / 21L (FIG. 18A), while the pressure Ps per unit area at the boundary between the product chip regions 3 is P / 1.
2L (FIG. 18B), the pressure Ps at the boundary between the pseudo chip region 5 and the product chip region 3 becomes smaller than the pressure Ps at the boundary between the product chip regions 3, and the pseudo chip Insulating film 1 at the boundary between region 5 and product chip region 3
8, the remaining film thickness becomes large.

However, according to the manufacturing method of the first embodiment, as described above, since the pattern 7 of the wiring 17 is formed also in the pseudo chip region 5, as shown in FIG.
The remaining film thickness of the insulating film 18 becomes uniform over the entire surface of the wafer 1, and the process margin of the photolithography or etching process in the subsequent process can be improved.
Specifically, the size of the convex portion of the pattern 7 is set to, for example, 80
μm and a pattern density of 20%, the remaining film thickness is 80
In the case of the insulating film 18 having a thickness of
and the variation when the pattern 7 is not formed in the pseudo chip region 5 is 300 nm, whereas the uniformity of 200 nm can be improved.

The conditions for the CMP polishing were as follows.
The pressure applied to the polishing pad 19 is 500 g / cm ² , the rotation speed of the platen and the carrier are both 20 rpm, and the polishing pad 19 can be a hard pad.

As shown in FIG. 7, a second-layer wiring 21 and an insulating film 22 may be further formed on the insulating film 18. It goes without saying that the pattern 7 is formed on the wiring 21 in the pseudo chip region 5 in the same manner as the wiring 17 so that the uniformity of the remaining film thickness of the insulating film 22 can be improved. Further, it goes without saying that three or more wiring layers may be formed.

(Embodiment 2) FIGS. 8 to 11 are sectional views showing an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps. Hereinafter, FIG.
The manufacturing method according to the second embodiment will be described with reference to FIGS.

First, the silicon nitride film 2 is formed on the main surface of the wafer 1.
Then, the shallow groove 24 is formed by patterning the silicon nitride film 23 and the main surface of the wafer 1 (FIG. 8). Known photolithography and etching techniques can be used for patterning the silicon nitride film 23 and the wafer 1.

This shallow groove is formed not only in the product chip area 3 but also in the pseudo chip area 5. Further, the pattern of the shallow groove 24 formed in the pseudo chip region 5 is the same as the pattern in the product chip region 3.

Next, for example, TEO
Silicon oxide film 25 by a plasma CVD method using S
Is deposited (FIG. 9). Also in the pseudo chip region 5, shallow grooves 24 having the same pattern as the shallow groove pattern in the product chip region 3.
Are formed, the surface irregularities of the silicon oxide film 25 have the same shape in the pseudo chip region 5 and the product chip region 3.

Next, as shown in FIG. 10, CMP polishing is performed. As described in the first embodiment, the contact area between the silicon oxide film 25 and the polishing pad 19 at the boundary region between the pseudo chip region 5 and the product chip region 3 is equal to the contact area at the boundary region between the product chip regions 3. Thus, the polishing rate of the silicon oxide film 25 can be made uniform over the entire surface of the wafer 1. As a result, a uniform element isolation region 26 can be formed (FIG. 11).

The silicon nitride film 23 shown in FIG.
Is removed to complete the wafer 1 on which the element isolation regions 26 are formed. However, the subsequent element formation steps are the same as in the first embodiment, and a description thereof will be omitted.

(Embodiment 3) FIGS. 12 to 15 are sectional views showing an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps. Hereinafter, the manufacturing method of the second embodiment will be described with reference to FIGS. (A) is a section taken along line aa in FIG. 1,
(B) shows a cross section taken along line bb in FIG.

Since the manufacturing method of the third embodiment is the same as that of the first embodiment until the first wiring layer is formed, the description is omitted.

An insulating film 27 is deposited on the insulating film 18 to form a groove 28 for forming a wiring and a connection hole 29 (FIG. 1).
2).

The insulating film 27 can be, for example, a TEOS silicon oxide film. If the insulating film 18 is sufficiently thick, the insulating film 27 can be omitted. The groove 28 and the connection hole 29 can be formed using known photolithography and etching techniques, and are formed not only in the product chip region 3 but also in the pseudo chip region 5.
The patterns of the grooves 28 and the connection holes 29 formed in the pseudo chip region 5 are the same as the patterns in the product chip region 3.

Next, a metal film 30 such as copper or aluminum is deposited on the entire surface of the wafer 1 by, for example, a sputtering method (FIG. 13). Since the grooves 28 and the connection holes 29 having the same pattern as the shallow groove pattern in the product chip region 3 are also formed in the pseudo chip region 5, the surface unevenness of the metal film 30 is changed to the pseudo chip region 5 and the product chip region 3.
Has a similar shape.

Next, as shown in FIG. 14, CMP polishing is performed. As described in the first embodiment, the contact area between metal film 30 and polishing pad 19 at the boundary region between pseudo chip region 5 and product chip region 3 is the contact area at the boundary region between product chip regions 3. The polishing speed of the metal film 30 can be made uniform over the entire surface of the wafer 1. As a result, a uniform wiring 31 can be formed by the damascene method (FIG. 15).

(Embodiment 4) FIG. 16 is a plan view showing a boundary region between a pseudo chip region 5 and a product chip region 3. FIG.

In the manufacturing method according to the fourth embodiment, the pattern 32 formed in the pseudo chip region 5 is different from the pattern 7 formed in the product chip region 3.
However, the pattern density of the pattern 32 and the pattern 7 is
Are identical.

As described above, by making the pattern densities of the pattern 32 and the pattern 7 the same, the CMP polishing rates in the pseudo chip region 5 and the product chip region 3 can be made uniform. The uniformity of the remaining film thickness can be improved.

The pattern densities of the pattern 32 and the pattern 7 do not need to be exactly the same. According to experiments and studies by the inventor, the pattern density N1
Is 0.5 × N with respect to the pattern density N2 of the pattern 7.
2 ≦ N1 ≦ 2 × N2, and 0.1 ≦ N1 ≦ 0.8,
And it is sufficient. That is, the pattern density N of the pattern 32
1 is 50% to 20% of the pattern density N2 of the pattern 7.
It may be between 0%. However, the pattern density N1 of the pattern 32 needs to be between 10% and 80%.

To show specific numerical values, for example, N
When 2 is 20%, N1 may be in the range of 10% to 40%. When N2 is 10%, N2
1 is in the range of 10% to 20%, and when N2 is 50%, N1 may be in the range of 25% to 80%.

The pattern size of the pattern 32 is at least twice the pattern width of the pattern 7 and 1 mm
It can be: In such a case, pattern 3
2 can prevent the generation of dust, such as the collapse of the wiring pattern formed by the wiring. That is, the pattern 32
In some cases, the wiring formed by the above process does not enter the effective processing region 6, and the processing of the members located outside the effective processing region 6 is generally not good. If the pattern width is increased, such a problem hardly occurs.

However, if the pattern size of the pseudo member or the pseudo recess is too large, the effect of patterning may be weakened.

The pattern 32 of the fourth embodiment is
It can be used also in the first to third embodiments.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, in the first to third embodiments, the case where the present invention is applied to an element isolation region and a metal wiring has been described. However, the present invention can also be applied to other members such as a gate wiring and a bit line.

[0068]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) The uniformity of the remaining film thickness of the polishing film in the CMP step can be improved.

(2) The exposure margin and the etching margin in the photolithography process after the CMP process can be improved, and the production yield of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of a wafer to which a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention is applied.

FIG. 2 is an enlarged view of a portion II in FIG.

FIG. 3 is a sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;
(A) shows a cross section taken along the line aa in FIG. 1, and (b) shows a cross section taken along the line bb in FIG. 1.

FIG. 4 is a sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;
(A) shows a cross section taken along the line aa in FIG. 1, and (b) shows a cross section taken along the line bb in FIG. 1.

FIG. 5 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;
(A) shows a cross section taken along the line aa in FIG. 1, and (b) shows a cross section taken along the line bb in FIG. 1.

FIG. 6 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;
(A) shows a cross section taken along the line aa in FIG. 1, and (b) shows a cross section taken along the line bb in FIG. 1.

FIG. 7 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;
(A) shows a cross section taken along the line aa in FIG. 1, and (b) shows a cross section taken along the line bb in FIG. 1.

FIG. 8 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.

FIG. 9 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.

FIG. 10 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.

FIG. 11 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.

12A and 12B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps, and FIG. 12A is a cross-sectional view taken along line aa in FIG.
(B) shows a cross section taken along line bb in FIG.

13A and 13B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps, and FIG. 13A is a cross-sectional view taken along line aa in FIG.
(B) shows a cross section taken along line bb in FIG.

14A and 14B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps, and FIG. 14A is a cross-sectional view taken along line aa in FIG.
(B) shows a cross section taken along line bb in FIG.

15A and 15B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps, and FIG. 15A is a cross-sectional view taken along line aa in FIG.
(B) shows a cross section taken along line bb in FIG.

FIG. 16 is a plan view showing a boundary region between a pseudo chip region and a product chip region according to the fourth embodiment.

FIG. 17 is a plan view showing an example in which a solid pattern is left in a pseudo chip area.

FIG. 18 is a cross-sectional view showing an example in which a solid pattern is left in a pseudo chip region.

[Explanation of symbols]

 Reference Signs List 1 wafer 2 product chip 3 product chip region 4 pseudo chip 5 pseudo chip region 6 effective processing region 7 pattern 8 field insulating film 9 well 10 gate insulating film 11 gate electrode 12 cap insulating film 13 impurity semiconductor region 14 sidewall 15 insulating film 16 Connection hole 17 Wiring 18 Insulating film 19 Polishing pad 20 Solid pattern 21 Wiring 22 Insulating film 23 Silicon nitride film 24 Shallow groove 25 Silicon oxide film 26 Element isolation region 27 Insulating film 28 Groove 29 Connection hole 30 Metal film 31 Wiring 32 Pattern N1 pattern Density N2 Pattern density P Applied pressure Ps Pressure R Polishing speed v Relative speed

Claims (6)

[Claims] 1. A product chip area located in an effective processing area of a semiconductor wafer, in which a product chip constituting a semiconductor integrated circuit device is formed, and an outer peripheral portion of the semiconductor wafer. A method of manufacturing a semiconductor integrated circuit device for processing a semiconductor wafer including a pseudo chip region in which an incomplete chip is formed, wherein a conductive element constituting a semiconductor integrated circuit element is formed in the product chip region. At the same time, a first step of forming a pseudo member made of the same material as the element constituent member in the pseudo chip region, and depositing an insulating film covering the element constituent member and the pseudo member on the entire surface of the semiconductor wafer, A second step of polishing the insulating film by a CMP method. 2. A product chip region located in an effective processing region of a semiconductor wafer, wherein a product chip constituting a semiconductor integrated circuit device is formed, and an outer peripheral portion of the semiconductor wafer, wherein the product chip is A method of manufacturing a semiconductor integrated circuit device for processing a semiconductor wafer including a pseudo chip region on which an incomplete chip is formed, wherein a conductive element constituting member for forming a semiconductor integrated circuit element on an insulating film of the product chip region A first step of forming a pseudo recess in the insulating film in the peripheral chip region at the same time as forming the recess in which the concave portion is formed; and forming a pseudo recess in the entire surface of the semiconductor wafer. A second step of depositing a conductive film and polishing the conductive film by a CMP method to form a conductive element forming member in the concave portion. Method for producing a body integrated circuit device. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the pattern of the pseudo member or the pseudo recess in the pseudo chip region is the element constituent member or the pseudo recess in the product chip region. A method for manufacturing a semiconductor integrated circuit device, wherein the pattern is the same as a pattern of a concave portion. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the pattern density of the pseudo member or the pseudo recess in the pseudo chip region is equal to the element constituent member or the pseudo component in the product chip region. A method of manufacturing a semiconductor integrated circuit device, wherein the pattern density is the same as or approximate to the pattern density of the recess. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the pattern density N1 of the pseudo member or the pseudo recess in the pseudo chip region is the element component in the product chip region. Or the pattern density N of the concave portion
2 satisfies both the first condition of 0.5 × N2 ≦ N1 ≦ 2 × N2 and the second condition of 0.1 ≦ N1 ≦ 0.8. A method of manufacturing a semiconductor integrated circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein a pattern dimension of the pseudo member or the pseudo recess is at least twice a pattern width of the element constituent member or the recess. A method for manufacturing a semiconductor integrated circuit device, wherein the thickness is 1 mm or less.