JPH1141570A - Multiplexing device and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce degradation of picture quality at each channel by setting the amount of data to be allocated to each channel corresponding to the amount of data to be generated on fixed conditions within the range of upper limit and/or lower limit value. SOLUTION: At encoder circuits 21A-21C, parameter calculation circuits 22A-22C respectively receive digital video signals SVASVC and detect parameters ME, DC, IAC and FLT. A central processing unit(CPU) 25 calculates the difficulty levels of respective video signals SVA-SVC from these parameters. Concerning the video signals SVA-SVC, the CPU 25 calculates a target code amount corresponding to the cumulative values of difficulty levels within the range of the upper limit or lower limit value of transmission speed and sets this amount to respective encoders 24A-24C. A multiplexer 20 multiplexes the respective encoded digital video signals with this target code amount in time division manner and transmits them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multiplexing apparatus and a multiplexing method, and can be applied to, for example, satellite broadcasting. According to the present invention, when a digital signal of a plurality of channels is subjected to encoding processing and then transmitted in a time-division multiplexed manner, data to be allocated to each channel according to the amount of data generated under certain conditions in the range of an upper limit and / or a lower limit By setting the amount, or by setting the data amount of each channel based on the amount of data generated under a certain condition from the specified data amount, it is possible to reduce the image quality deterioration of each channel. I do.

[0002]

2. Description of the Related Art Conventionally, in a satellite broadcast or the like, a multiplexing apparatus as shown in FIG. 11 multiplexes broadcast signals of a plurality of channels in real time to perform uplink.

That is, in the multiplexing apparatus 1, the encoders 2A to 2C use MPEG (Moving Picture Experts Gr.)
oup), and compresses data of digital video signals constituting each broadcast channel. Multiplexer 3 includes encoders 2A-2
The bit streams DA to DC output from C are time-division multiplexed by packetizing them sequentially, and the resulting multiplexed bit stream DM is sent to the transponder.

FIG. 12 is a block diagram showing a video signal processing system of these encoders 2A to 2C. Since the encoders 2A to 2C have the same configuration, only the encoder 2A will be described below, and redundant description will be omitted.

In the encoder 2A, a reordering circuit 6 receives the digital video signals SVA sequentially input in a time series, rearranges the order of the frames of the digital video signals SVA, and outputs them in the order of encoding. That is, when the digital video signal SVA is divided into GOP units and viewed,
Rearrange the order so that the picture comes first. In addition, the order of each frame is switched so that the corresponding predicted frame is encoded first between consecutive frames.

[0006] The following blocking circuit 7 changes the order of the image data constituting the digital video signal, and converts continuous image data in the order of raster scanning in units of one frame in units of macroblocks of 16 × 16 pixels. The data is output to the motion detection circuit 8 and the subtraction circuit 9 according to the raster scanning order.

The motion detecting circuit 8 detects the motion vector MV of the image data output from the blocking circuit 7 by using, for example, the prediction frame held in the motion compensating circuit 10 by a block matching technique. At this time, the motion detection circuit 8 detects a motion vector MV by pre-prediction, post-prediction, and bidirectional prediction according to the picture set in the image data output from the blocking circuit 7. The image data output from the blocking circuit 7 is I
In the case of a picture, the detection of the motion vector MV is stopped.

The motion compensation circuit 10 outputs the image data of the predicted frame to the subtraction circuit 9 at a timing according to the motion vector MV. At this time, when the image data input to the subtraction circuit 9 is an I picture, the motion compensation circuit 10 stops outputting the image data. On the other hand, when the image data input to the subtraction circuit 9 is a B picture, a prediction frame is set by pre-prediction, post-prediction, or bidirectional prediction based on the detection result of the motion vector MV.

The subtraction circuit 9 subtracts the image data output from the motion compensation circuit 10 from the image data output from the blocking circuit 7 and outputs the result. Accordingly, the subtraction circuit 9 determines that the image data output from the blocking circuit 7 is I
In the case of a picture, the sequentially input image data is output as it is. When the image data is a P or B picture, difference data from a motion-compensated predicted frame is output.

A discrete cosine conversion circuit (DC
T) 11 performs discrete cosine transform processing on the image data output from the subtraction circuit 9 in macroblock units. Further, the discrete cosine transform circuit 11 sequentially outputs coefficient data as a processing result, starting from a low-order coefficient.

The quantization circuit (Q) 12 switches the quantization table under the control of the code amount control circuit 13, and sequentially quantizes and outputs the coefficient data output from the discrete cosine transform circuit 11. Inverse quantization circuit (IQ) 1
4 dequantizes the output data of the quantization circuit 12,
As a result, the coefficient data corresponding to the input data of the quantization circuit 12 decoded at the transmission destination is reproduced. An inverse discrete cosine transform circuit (IDCT) 16 performs an inverse discrete cosine transform process on the output data of the inverse quantization circuit 14, thereby decoding the image data corresponding to the input data of the discrete cosine transform circuit 11 at the transmission destination. To reproduce.

The addition circuit 17 adds the image data output from the motion compensation circuit 10 and the image data output from the inverse discrete cosine conversion circuit 16 and thereby, the subtraction circuit 9 is decoded at the transmission destination. And reproduces image data corresponding to the input data. Further, the addition circuit 17
Stores these image data in a frame memory built in the motion compensation circuit 10 when these image data are set in a predicted frame of another frame. Through a series of processes from the inverse quantization circuit 14 to the motion compensation circuit 10, the encoder 2A sequentially encodes continuous image data so that errors in the encoding process and the decoding process are not accumulated.

A variable length coding circuit (VLC) 18 performs variable length coding on output data of the quantization circuit 12 and outputs the result. The buffer 19 outputs the output data of the variable length coding circuit 18 at a predetermined transmission rate.

The code amount control circuit 13 monitors the generated code amount of the coded data DA via the buffer 19, and controls the quantization of the quantization circuit 12 according to the target code amount assigned to each broadcast channel. Switch tables,
Thereby, the operation of the quantization circuit 12 is controlled so that the code amount generated by the encoding process becomes the target code amount. Thus, in the conventional multiplexing apparatus 1, a digital video signal is encoded according to the code amount assigned to each channel, and then multiplexed and transmitted.

[0015]

In the case where the encoding process is performed using the correlation between consecutive frames as described above, the data amount after motion compensation increases in a scene change in which a scene is switched. . Similarly, in the case of transmitting a sports program or the like in which the movement is intense, the data amount after the motion compensation similarly increases.

In such a case, as in other scenes and programs, a quantization table is set according to the bit rate assigned to each broadcast channel, and this kind of video signal is transmitted with a uniform code amount. The image quality is degraded in scenes where scene changes and intense movement occur.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a multiplexing apparatus and a multiplexing method capable of reducing image quality deterioration of each channel.

[0018]

According to the present invention, there is provided a multiplexing apparatus or a multiplexing method in which a parameter corresponding to a data amount of encoded data generated by an encoding process under a predetermined condition is set. Detecting and controlling the encoding process by the encoding means so that the data amount of the encoded data of each channel in the multiplexed data becomes the data amount corresponding to the parameter within the range of the upper limit value and / or the lower limit value.

Similarly, in the multiplexing apparatus or the multiplexing method, the reference data amount set for each channel is corrected by a parameter to set the target data amount of each channel, and the encoding of each channel in the multiplexed data is performed. The encoding process by the encoding means is controlled so that the data amount of the data becomes the target data amount.

A parameter corresponding to the data amount of the encoded data generated by the encoding process under a certain condition is detected, and the data amount of the encoded data of each channel in the multiplexed data within the range of the upper limit and / or the lower limit. If the encoding process is controlled such that is equal to the data amount corresponding to the parameter, the data amount of the multiplexed data can be appropriately distributed within the range limited by the upper limit and / or the lower limit. Thus, for example, in the case of transmitting a digital video signal, the image quality can be improved by guaranteeing the image quality by the upper limit value and / or the lower limit value and changing the data amount according to the change of the digital video signal.

Alternatively, the target data amount of each channel is set by correcting the reference data amount set for each channel by a parameter, and the data amount of the coded data of each channel in the multiplexed data is set to the target value. If the encoding process is controlled so as to achieve the data amount, the data amount can be increased or decreased in accordance with the change in the digital signal to be transmitted based on the reference data amount set for the channel. The image quality can be improved by changing the data amount in response to a change in the digital video signal while guaranteeing the image quality of the digital video signal.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment FIG. 2 is a block diagram showing a multiplexing apparatus according to a first embodiment of the present invention. The multiplexer 20 converts the three-channel digital video signals SVA to SVC into MPEs.
After compressing the data according to the format specified in G, the data is multiplexed and transmitted. In the multiplexing device 20, the encoding circuits 21A, 21B, and 21C have the same configuration, compress data of the digital video signals SVA to SVC in a format prescribed by MPEG, and output bit streams DA, DB, and DC. .

That is, the encoding circuits 21A, 21B, 21
In C, the parameter calculation circuits 22A, 22B, 22
C receives digital video signals SVA to SVC, respectively, and obtains parameters ME, DC, and IA necessary for calculating the degree of difficulty of each digital video signal SVA to SVC.
C, FLT is detected. Encoding circuits 21A, 21B, 2
1C is each parameter calculation circuit 22A, 22B, 22C
Video signals SVA to SV output through
C is received by the encoders 24A, 24B, 24C via the FIFOs 23A, 23B, 23C, where the parameter M
The digital video signals SVA to SVC are data-compressed at a rate set by the central processing unit (CPU) 25 based on E, DC, IAC, and FLT.

Here, the difficulty is a variable corresponding to the amount of data generated by encoding each of the digital video signals SVA to SVC without limiting the amount of generated bits at all. For example, in the encoder described with reference to FIG. , With the quantization table fixed, respectively, and corresponds to the output data amount of the buffer 19 measured by supplying the digital video signal.

On the other hand, parameters ME, DC, IA
C and FLT are parameters that can be directly detected from the digital video signal and show a high correlation with the degree of difficulty, and are parameters that can be approximated to the degree of difficulty by a linear expression. Therefore, the parameters ME, DC, IAC, FLT
Are parameters corresponding to the data amount of the encoded data generated when the digital video signal is subjected to the encoding process under certain conditions, and the degree of difficulty directly corresponds to the data amount. The difference is that the parameter indirectly corresponds to the data amount.

The first parameter ME is a so-called ME residual, and the luminance data is detected between the corresponding macroblock by performing motion compensation on the predicted frame using the motion vector (mv _x , mv _y ). Is the cumulative value of the absolute value of the difference signal. Thus, the first parameter ME is the cumulative value of the inter-frame difference obtained by performing motion compensation on the luminance data of the digital video signal, and is expressed by the following equation. Where f _curr (x, y)
_{(X s ≦ x <x e} , y s ≦ y <y e) is the corresponding macroblock, f _ref (x, y) is the corresponding area of the predicted _{frame, x s, x e, y} s , Y _e indicate the range in the x and y directions of the macroblock.

[0028]

(Equation 1)

Since the first parameter is the accumulation of the absolute value of the inter-frame difference obtained by motion compensation, the first parameter increases in a portion where the movement is severe or a scene change. In the inter-frame encoding process, the degree of difficulty and the amount of data generated by the encoding process are highly correlated.

On the other hand, the second parameter DC is detected by accumulative addition of luminance data for each frame, and is represented by the following equation.

[0031]

(Equation 2)

Thus, this second parameter DC
Indicates the DC level of the luminance level by detecting the cumulative addition of the luminance data for each frame. In image data, as the DC level of the luminance level is higher, if the DC level is lost, the image quality is visually deteriorated. This allows the encoder to:
If the value of the generated data is limited when the value of the second parameter DC is large, the image quality deteriorates. As a result, the second parameter DC shows a high correlation with the degree of difficulty and the amount of generated data in the intra-frame encoding process.

On the other hand, the third parameter IAC is
The level difference between the average luminance level and the luminance level in the macro block is converted into an absolute value and accumulated, and is represented by the following equation. Here, AV indicates the average luminance level in the macroblock, and N indicates the number of luminance data in the macroblock.

[0034]

(Equation 3)

Thus, this third parameter IA
C is a value obtained by accumulating the level difference between the average luminance level and the luminance level in the macroblock by making the absolute value into an absolute value. Therefore, the value increases in a frame in which the luminance level changes drastically. The higher-order coefficient data takes a significant value by the discrete cosine transform processing by the inner encoding processing. As a result, the third parameter IAC shows a high correlation with the degree of difficulty and the amount of generated data in the intra-frame encoding process.

On the other hand, the fourth parameter FLT is
When one screen is viewed in a diagonal direction, the points where the change in the luminance level is smaller than a predetermined value are counted. In this embodiment, one screen is divided into small blocks of 2 × 2 pixels, and two difference values are detected by detecting a difference value between pixels in an oblique direction in each block. When any of the difference values detected in this way is converted into an absolute value and is equal to or lower than a predetermined level, this block is counted.

Thus, the fourth parameter FL
T indicates the magnitude of the change in the brightness level when one screen is viewed obliquely, so that in the intra-frame encoding process,
This shows a high correlation with the degree of difficulty and the amount of generated data.

FIGS. 3 and 4 are block diagrams showing each encoding circuit 21A in detail. The encoding circuits 21B and 21C have the same configuration as that of the encoding circuit 21A except that the digital video signal to be processed is different, and thus redundant description is omitted. In the configurations shown in FIGS. 3 and 4, the same configurations as those of the conventional configuration described above with reference to FIGS.
Duplicate description is omitted.

In the encoding circuit 21A, the reordering circuit 26 receives the digital video signals SVA sequentially input in a time series, and outputs the digital video signals SVA by changing the frame order. That is, when the digital video signal SVA is divided into GOP units and viewed, the rearrangement circuit 26 rearranges the order so that the I picture is first in each GOP. In addition, the order of each frame is switched so that the corresponding predicted frame is encoded first between consecutive frames.

The block forming circuit 27 changes the order of the image data constituting the digital video signal, and converts the continuous image data in the raster scanning order in units of one frame in units of macroblocks of 16 × 16 pixels. Are output in the order of the raster scanning.

The intra AC detection circuit 28 is a digital video signal SV output from the blocking circuit 27.
From A1, the third parameter (intra AC) IAC described by equation (3) is calculated. That is, as shown in FIG. 5, the intra AC detection circuit 28
The luminance data of the digital video signal SVA1 is cumulatively added for each macroblock by the accumulator of the delay circuit (D) 30.

The latch circuit 31 latches the accumulated data by the adder 29 and the delay circuit 30 by latching the output data of the adder 29 at the timing when the macroblock ends. At this time, the latch circuit 31 bit-shifts and latches the cumulative addition value by the number of pixels constituting the macroblock, thereby taking in the average luminance level AV in the macroblock. The subsequent latch circuit 32 continuously supplies the average luminance level taken into the latch circuit 31 to the subtraction circuit 33 during the period of the subsequent macro block.

The FIFO 34 delays the digital video signal SVA1 input to the subtraction circuit 29 by a predetermined period, and outputs the digital video signal SVA1 to the subtraction circuit 33 at a corresponding timing. Thus, the subtraction circuit 33 sequentially outputs the level difference between the average luminance level and the luminance level.

The absolute value conversion circuit (ABS) 35 converts the output data of the subtraction circuit 33 into an absolute value and outputs the data. The addition circuit 36 and the delay circuit 37 constitute a cumulative adder, and cumulatively add the output data of the absolute value conversion circuit 35 to obtain a parameter I.
Detect AC. In this embodiment, the intra AC detection circuit 28 is provided with an addition circuit 36 for each frame.
And reset the accumulator by the delay circuit 37. This accumulates and outputs the third parameter IAC for one frame.

The flatness detection circuit 40 (FIG. 3) calculates the fourth parameter FL from the digital video signal SVA1.
T is detected and output. That is, as shown in FIG. 6, the flatness detection circuit 40 outputs the digital video signal SV
The luminance data of A1 is supplied to the FIFO 41, where it is delayed by a timing corresponding to 16 pixels. Thus, 16 pixels are the number of pixels constituting one line of the macro block. The delay circuit (D) 42
While one input data is delayed by a timing corresponding to one pixel, the delay circuit 43 delays the output data of the FIFO 41 by a timing corresponding to one pixel.

The subtraction circuit 44 subtracts the input data of the delay circuit 43 from the output data of the delay circuit 42 and outputs the result. The subtraction circuit 45 subtracts the output data of the delay circuit 43 from the input data of the delay circuit 42. Output. As a result, the subtraction circuits 44 and 45 output difference data between luminance data adjacent in the diagonal direction in the 2 × 2 pixel area.

The absolute value conversion circuit (ABS) 46 converts the output data of the subtraction circuit 44 into an absolute value and outputs the data, and the absolute value conversion circuit (ABS) 47 converts the output data of the subtraction circuit 45 into an absolute value and outputs it. . The minimum value selection circuit (MIN) 48 selects and outputs output data having a smaller value than the output data of the absolute value conversion circuits 46 and 47. Comparison circuit (CMP) 49
Outputs the comparison result of the value 1 when the output data of the minimum value selection circuit 48 is smaller than the threshold data TH.

The adder circuit 50 and the delay circuit 51 constitute a cumulative adder, and cumulatively add the output data of the comparator circuit 49 on a frame-by-frame basis to generate and output a fourth parameter FLT.

The accumulator 53 (FIG. 3) is composed of an addition circuit and a delay circuit, and the digital video signal SVA
The second parameter DC is generated by cumulatively adding the luminance data of each frame.

The motion detection circuit 54 holds a predicted frame by selectively holding the digital video signal SVA1 in a built-in frame memory. Thus, while the encoder decodes the coefficient data provided for transmission to form a predicted frame, the motion detection circuit 54 holds image data that has not been encoded at all as a predicted frame. Will be different.

Further, the motion detection circuit 54 applies a block matching technique to calculate the motion vector M for the macroblock set in the P picture and the B picture.
V is detected and output. That is, the motion detection circuit 54
Image data input in the order of raster scanning in units of macroblocks is input to a plurality of subtraction circuits corresponding to the motion detection range. Further, the image data of the prediction frame corresponding to the motion detection range is supplied to these subtraction circuits simultaneously and in parallel with the image data, and the difference data obtained from each subtraction circuit is accumulated in macroblock units. Further, the motion detection circuit 54 detects the minimum value of these accumulated values, and detects the motion vector MV from the relationship between the digital video signal SVA1 and the predicted frame in the subtraction circuit from which the minimum value has been obtained.

Further, the motion detecting circuit 54 outputs the accumulated value of the difference data in the motion vector detected in this way as ME residual error ME. The accumulative adder 55 accumulatively adds the ME residual output from the motion detection circuit 54 in macroblock units in frame units and outputs the result.

The FIFO 56 delays the motion vector MV detected by the motion detection circuit 54 by a predetermined period, and inputs the motion vector MV to the encoder 24A at the timing when the corresponding digital video signal SVA1 is input to the encoder 24A. I do.

The FIFO 23A has a parameter calculation circuit 2
The digital video signal SVA1 output from 2A is set to 1
The signal is input to the encoder 24A after being delayed by the GOP period.

The encoder 24A (FIG. 4) encodes this digital video signal SVA1 in a format prescribed by MPEG and outputs it. Thus, in the encoding circuit 21A, the image data of the digital video signal SVA1 is rearranged in the encoding order and in macroblock units in the parameter calculation circuit 22A. The arrangement circuit 6 and the blocking circuit 7 described above are omitted, and the motion detection circuit 8 is omitted. Thus, the encoding circuit 21A can be created by a simple configuration in which a configuration such as the intra AC detection circuit 28 is added to the encoder having the conventional configuration.

To this end, the encoder 24A uses the subtraction circuit 9 in the discrete cosine conversion circuit 11.
The obtained differential data or image data is subjected to discrete cosine transform processing, and the resulting coefficient data is quantized by the quantization circuit 12 and output. At this time, by setting the quantization table by the code amount control circuit 13, the encoder 24A performs quantization processing on the coefficient data so that the generated data amount becomes the target code amount set in the code amount control circuit 13, The quantized coefficient data is subjected to a variable length encoding process by a variable length encoding circuit (VLC) 18. The encoder 24A outputs the encoded data DA generated in this way via the buffer 19.

FIG. 7 shows parameters ME, IAC, DC,
Central processing unit 2 for setting target data amount from FLT
5 is a flowchart showing the procedure of FIG. 5 (FIG. 2). The central processing unit 25 converts the digital video signals SVA to
This processing procedure is executed in the SVC GOP cycle.

That is, the central processing unit 25 proceeds from step SP1 to step SP2, and
The IAC, DC, and FLT are encoded by the respective encoding circuits 21A, 21B,
21C, the parameters ME, IAC, DC, FLT are calculated by executing the following arithmetic processing.
From the difficulty level D of each digital video signal SVA to SVB
Calculate A-DC.

[0059]

(Equation 4)

Here, A1 to A4 and B are coefficients. When the digital video signals SVA to SVC are I pictures, the coefficients A2 to A4 and B are set to significant values other than the value 0, and the coefficient A1 is Set to the value 0. When the digital video signals SVA to SV are P-pictures and B-pictures, the coefficient A1 is set to a value 0 and the coefficient A2
A3, coefficient B is set to a significant value other than the value 0.
Further, the significant values set in these coefficients A1 to A4, B are set by approximating the degree of difficulty detected for various digital video signals and the values of the parameters ME, IAC, DC, FLT by a linear expression. You.

Thus, each digital video signal S
Upon detecting the difficulty levels DA to DC for one frame of VA to SV, the central processing unit 25 proceeds to step SP3.
Then, the difficulty level is added to the cumulative addition value. Note that the central processing unit 25 resets the cumulative addition value at the GOP cycle.

Subsequently, the central processing unit 25 proceeds to step SP4 and determines whether or not the difficulty level has been accumulated for one GOP. If a negative result is obtained here, the processing returns to step SP2. As a result, the central processing unit 25 executes step SP
By repeating the processing procedure of 2-SP3-SP4-SP2, 1
When the degree of difficulty for the GOP is accumulated, a positive result is obtained in step SP4, and the process proceeds to step SP5.

In step SP5, the central processing unit 25 executes the target code amount calculation process to calculate the target code amount for one GOP of each digital video signal from the cumulative value of the difficulty of each digital video signal. I do. Subsequently, the central processing unit 25 proceeds to step SP6, sets the calculated target code amount in each of the encoders 24A to 24C, and then proceeds to step SP2 to similarly start calculating the target code amount for the subsequent GOP.

As a result, the central processing unit 25 converts the GOP of the digital video signal into a unit.
A target code amount is set to A to 24C, and the multiplexing device 20 is configured to time-division multiplex and transmit each digital video signal coded according to the target code amount.

FIG. 1 is a flowchart showing the target code amount calculation processing. The central processing unit 25 receives an upper limit value and a lower limit value of the transmission speed in advance for the two-channel digital video signal. For the remaining one-channel digital video signal, the lower limit of the transmission speed is accepted. In this embodiment, upper limit values uA,
It is assumed that uB and lower limits lA, lB, and lC have been received.

Further, before executing the processing procedure described above with reference to FIG. 7, the central processing unit 25 executes the arithmetic processing of the following equation to determine the upper limit values uA and uB and the lower limit values lA and lA.
B, 1C, the transmission rate T allowed for the multiplexer,
Upper limits UA, UB and lower limit L allowed for one GOP
A, LB, LC, and the transmission rate M allowed by the multiplexer are converted. Here, N is the number of frames of one GOP.

[0067]

(Equation 5)

[0068]

(Equation 6)

[0069]

(Equation 7)

[0070]

(Equation 8)

[0071]

(Equation 9)

[0072]

(Equation 10)

More specifically, digital video signals SVA-
SVC is NTSC system, N is 30 frames, T is 10
[Mbps], the operator sets the upper limit value uA =
2.5 [Mbps], uB = 3.0 [Mbps], lower limit lA = 1.8 [Mbps], lB = 2.0 [Mbp]
s] and 1C = 4.5 [Mbps], the upper limit values UA and UB and the lower limit values LA and LB of each GOP are as follows.

[0074]

[Equation 11]

At the time of setting by the operator, the central processing unit 25 determines whether or not the following relational expression is satisfied. If the relational expression is not satisfied, the central processing unit 25 notifies the operator of an erroneous input.

[0076]

(Equation 12)

After executing such arithmetic processing in advance, the central processing unit 25 moves from step SP10 to step SP11 in the target code amount calculation processing, and sets one digital video signal SV having an upper limit set.
For A, the following arithmetic processing is executed. As a result, the entire target code amount is allocated according to the degree of difficulty DA to DC, and the target code amount EA is calculated for the digital video signal of one channel. Note that the difficulty levels DA to DC in this processing procedure are the difficulty levels accumulated in GOP units.

[0078]

(Equation 13)

Thus, in the above specific example, when the difficulty levels DA, DB, and DC are 10, 20, and 30, respectively,
The target code amount EA of the following equation is calculated.

[0080]

[Equation 14]

Subsequently, the central processing unit 25 proceeds to step SP12, where the calculated code amount EA and the upper limit U
A, by comparing the code amount EA with the lower limit LA,
A branch condition for limiting the code amount EA by the upper limit value UA and the lower limit value LA is determined.

Subsequently, the central processing unit 25 proceeds to step SP13, and determines from the comparison result in step SP12 whether or not the code amount EA is equal to or smaller than the lower limit value LA.
If a positive result is obtained here, the central processing unit 25
Moves to step SP14, sets the lower limit value LA to the target code amount EA1 instead of the calculated code amount EA, and then moves to step SP15.

On the other hand, if a negative result is obtained in step SP13, the central processing unit 25 proceeds to step SP16, and determines whether or not the code amount EA is in the range from the lower limit LA to the upper limit UA. If a positive result is obtained here, the central processing unit 25 proceeds to step SP17.
After setting the calculated code amount EA to the target code amount EA1, the process moves to step SP15.

On the other hand, if a negative result is obtained in step SP16, the central processing unit 25 proceeds to step SP18. In this case, since the code amount EA exceeds the upper limit value UA, instead of the calculated code amount EA,
After setting the upper limit value UA to the target code amount EA1, the process moves to step SP15.

Thus, the central processing unit 25 sets the target code amount EA1 from the code amount EA calculated in step SP11 as shown by the following equation.

[0086]

(Equation 15)

In the above-described example, the relationship of EA <LA is obtained, so that the central processing unit 2
5 is 1.8 [Mbps] in which the target code amount EA1 of the digital video signal SVA is the lower limit value LA.
Will be set to

Subsequently, the central processing unit 25 proceeds to step SP15, and calculates a target code amount for the remaining digital video signal SVB having the upper limit set. Here, the central processing unit 25 calculates the following equation.
The target code amount EB1 is assigned to the digital video signal SVA, and the remaining code amount (M-EA1) is distributed by the remaining two channels of difficulty DB and DC to calculate the target code amount EB.

[0089]

(Equation 16)

Specifically, in the above example, the central processing unit 25 calculates the target code amount EB represented by the following equation.

[0091]

[Equation 17]

Subsequently, the central processing unit 25 proceeds to step SP19, where the calculated code amount EB and the upper limit U
B, by comparing the code amount EB with the lower limit value LB,
A branch condition for limiting the code amount EB by the upper limit value UB and the lower limit value LB is determined.

Subsequently, as shown in FIG. 8, the central processing unit 25 proceeds to step SP20,
From the comparison result in 19, it is determined whether or not the code amount EB is equal to or smaller than the lower limit value LB. If a positive result is obtained here, the central processing unit 25 proceeds to step SP21, and sets the lower limit value LB to the target code amount EB1 instead of the calculated code amount EB.
Then, the process proceeds to step SP22.

On the other hand, if a negative result is obtained in step SP20, the central processing unit 25 proceeds to step SP23, and determines whether or not the code amount EB is in the range from the lower limit value LB to the upper limit value UB. If a positive result is obtained here, the central processing unit 25 proceeds to step SP24.
Then, the calculated code amount EB is set to the target code amount EB1, and then the process proceeds to step SP22.

On the other hand, if a negative result is obtained in step SP23, the central processing unit 25 proceeds to step SP25. In this case, since the code amount EB exceeds the upper limit value UB, instead of the calculated code amount EB,
After setting the upper limit value UB to the target code amount EB1, the process moves to step SP22.

Thus, the central processing unit 25 sets the target code amount EB1 from the code amount EB calculated in step SP19 as shown by the following equation.

[0097]

(Equation 18)

In the specific example described above, since the relationship of EB> UB is obtained, the central processing unit 25 sets the target code amount EB1 of this digital video signal SVB to the upper limit value UB of 3.0 [3.0]. Mbps].

Thus, the digital video signal SV
After setting the target code amount EB for B, the central processing unit 25 calculates the target code amount for the remaining digital video signal SVC in step SP22. Here, the central processing unit 25 applies the target code amount EA to the digital video signals SVA and SVB by the following arithmetic processing.
1 and EB1 are allocated and the remaining code amount (M-EA1-E
B1) is set to the target code amount EC of the remaining channels.

[0100]

[Equation 19]

In the above example, the target code amount EC represented by the following equation is set.

[0102]

(Equation 20)

Subsequently, the central processing unit 25 proceeds to step SP26, and calculates the calculated target code amounts EA1, EB1,.
After the EC sets the parameters NA, NB, and BC corresponding to the encoders 24A, 24B, and 24C, the process proceeds to step SP27 and returns to the original processing routine.

In the above configuration, in the multiplexer 20, the digital video signals SVA, SVB, and SVC (FIGS. 2 and 3) are converted into parameter calculation circuits 22A and 22.
B, 22C, parameters ME, DC, IAC, FLT corresponding to the amount of generated code under predetermined coding conditions
Are sequentially detected in frame units.

That is, the difference data obtained from the motion detecting circuit 54 is cumulatively added in the cumulative adder 55, and the first parameter ME is detected by a so-called ME residual. In addition, the accumulator 53 accumulates the luminance data and detects the second parameter DC. Further, in the intra AC detection circuit 28, the level difference between the average luminance level and the luminance level of the macro block is converted into an absolute value and accumulated, and the third parameter IAC is detected. Further, in the flatness detection circuit 40, when one screen is viewed obliquely, a portion where the change in the brightness level is smaller than a predetermined value is counted, and the fourth parameter FLT is detected.

Digital video signals SVA, SVB, S
VC calculates these parameters ME, DC, IAC, FL
T are sequentially input to the central processing unit 25, and the degree of difficulty DA, DB, DC corresponding to the amount of generated code under predetermined coding conditions is calculated by the arithmetic processing of equation (4). Is accumulated.

The digital video signals SVA to SVC are
Limited by the upper and lower limits, this difficulty DA,
In accordance with DB and DC, code amounts that can be allocated are allocated in GOP units, and the allocated target code amounts EA1, EA
The data is coded and multiplexed by B1 and EC.

That is, the digital video signals SVA to SVA
VC first determines that the code amount M that can be assigned to the digital video signal SVA of the first channel is the difficulty level D.
After the target code amount EA is temporarily set by distributing by A, DB, and DC, the target code amount EA1 of the digital video signal SVA is calculated by limiting the target code amount EA with the upper limit value UA and the lower limit value LA. Further, with respect to the second channel digital video signal SVA, the remaining allocatable code amount ME is set.
A1 is distributed by the difficulty level DB and DC, and the target code amount E
After B is temporarily set, the target code amount EB1 of the digital video signal SVB is calculated by limiting the upper limit value UB and the lower limit value LB. Further, the remaining assignable code amount M-EA1-EB1 is assigned to the digital video signal SVC of the remaining channel.

As a result, digital video signals SVA-
In the SVC, a large amount of code is allocated in the case of rapid movement, scene change, etc. by allocating a code amount based on the degree of difficulty DA, DB, and DC. It is transmitted with higher image quality.

At this time, due to the limitation by the upper limit value, the amount of codes to be allocated is limited even in the case of rapid movement, scene change, etc., thereby effectively preventing image quality deterioration due to a sharp decrease in the amount of codes in other digital video signals. Can be avoided. In addition, even if the other digital video signals are intensely moving or a scene change is performed, a code amount of such a level that the minimum image quality can be compensated is also assigned due to the limitation by the lower limit value, thereby effectively avoiding image quality deterioration. be able to.

According to the above configuration, the degrees of difficulty DA, DB,
By allocating the code amount that can be allocated according to DC, a digital video signal can be transmitted with higher image quality than when a uniform code amount is allocated. At this time, by allocating the code amount by restricting the upper limit value and the lower limit value, it is possible to effectively avoid the deterioration of the image quality of other digital video signals even in the case of rapid movement or scene change.

(2) Second Embodiment FIG. 9 is a flowchart showing a target code amount calculation processing procedure by a central processing unit according to a second embodiment of the present invention. The multiplexing apparatus according to this embodiment has the same configuration as that of the first embodiment except that the target code amount calculation processing procedure in the central processing unit is different. Further, in response to this processing procedure, the central processing unit accepts the setting of the average code amounts aA, aB, and aC of each channel from the operator instead of the upper and lower limits. Note that these average code amounts aA, aB, and aC need to satisfy the following equation with respect to the transmission speed T allowed for the multiplexer 3.

[0113]

(Equation 21)

The central processing unit executes the following arithmetic processing based on the input average code amounts aA, aB, and aC in advance, and converts the average code amounts aA, aB, and aC into code amounts AA, AB in GOP units. , AC, and performs a target code amount calculation process using the code amounts AA, AB, and AC in GOP units.

[0115]

(Equation 22)

[0116]

(Equation 23)

[0117]

(Equation 24)

As a specific example, 1 GOP = 30 frames (N = 30) of an NTSC digital video signal
, The average code amounts aA, aB, and aC are 2.0 [Mbps], 3.0 [Mbps], respectively.
When set to 5.0 [Mbps], the central processing unit determines the code amounts AA, A
B and AC will be calculated.

[0119]

(Equation 25)

The central processing unit executes the following arithmetic processing together with these arithmetic processings in advance, and calculates the distribution ratio P0 of the equal code amount to each channel.

[0121]

(Equation 26)

The central processing unit operates similarly to the first embodiment to sequentially input digital video signals SV.
For A to SVB, first to fourth parameters ME and D
C, IAC, and FLT in order of GOP unit DA,
DB and DC are calculated, and the calculated degree of difficulty DA, DB,
The target code amount is sequentially calculated and set from DC. At this time, the target code amount is corrected using the code amounts AA, AB, and AC in GOP units calculated by the previous arithmetic processing and the distribution ratio P0 of the equal code amount to each channel.

That is, the central processing unit executes step S
The process proceeds from step P30 to step SP31 and executes the arithmetic processing of the following equation, thereby detecting the detected degrees of difficulty DA, DB, and D.
The code amount distribution ratios pA, pB, and pC based on C are calculated.

[0124]

[Equation 27]

Specifically, when the degrees of difficulty DA, DB, and DC are 50, 40, and 10, respectively, the central processing unit determines the distribution ratio pA of the code amount by the degrees of difficulty DA, DB, and DC as shown by the following equation. Calculate pB and pC.

[0126]

[Equation 28]

Subsequently, the central processing unit proceeds to step SP
32, where the calculation processing of the following equation is executed, whereby the differences PA, PB, PC between the equally divided distribution ratio P0 and the distribution ratios pA, pB, pC by the degrees of difficulty DA, DB, and DC.
Calculate C. Thus, the central processing unit detects a change in the distribution of the code amount due to the degree of difficulty based on the distribution of the equal code amount.

[0128]

(Equation 29)

More specifically, in the case of the above example, the central processing unit calculates the differences PA, PB, and PC as shown in the following equations.

[0130]

[Equation 30]

Subsequently, the central processing unit proceeds to step SP
Then, the process proceeds to step 33, where the following arithmetic operation is executed to calculate the code amount corresponding to the calculated difference from the average code amount set for each channel. At this time, the central processing unit, as shown in parentheses in the following equation,
A code amount margin corresponding to the difference is calculated for a channel in which a negative calculation processing result is obtained by the arithmetic processing of the equation (29) and which has a margin for code distribution due to difficulty in equal code distribution. .

[0132]

(Equation 31)

Thus, according to the above-described example, PA
By obtaining the relationships of> 0, PB> 0, and PC <0, the central processing unit calculates the code amount BC of the digital video signal SVC of the third channel by the following equation.

[0134]

(Equation 32)

Subsequently, the central processing unit proceeds to step SP
The process proceeds to S34, where the code amount margin is distributed, and the code amount margin detected in step SP33 is allocated to other channels to set the target code amount for each channel. Further, the central processing unit sets the target code amount of each channel to the encoders 24A, 24B, 24C, and then proceeds to step SP35 to return to the original processing procedure.

FIG. 10 is a flowchart showing the distribution processing of the code amount margin. The central processing unit proceeds from step SP40 to step SP41, where it determines whether any of the differences PA, PB, and PC calculated in step SP32 is zero. If a positive result is obtained here, the central processing unit proceeds to step SP42,
As shown by the following equation, the code amount A of the GOP based on the average code amounts aA, aB, and aC set for each channel.
After setting A, AB, and AC to the target code amounts NA, NB, and NC, the process moves to step SP43 and ends the processing procedure.

[0137]

[Equation 33]

On the other hand, if a negative result is obtained in step SP41, the central processing unit proceeds to step S41.
The process proceeds to P44, where it is determined whether or not the difference calculated for the first channel in step SP32 is a negative value, thereby determining whether or not the code amount is sufficient in the first channel. Here, if a positive result is obtained, the central processing unit proceeds to step SP45, and similarly determines whether or not the code amount for the second channel has a margin.

If a positive result is obtained here, in this case, the difference calculated in step SP32 is held at a positive value in the third channel, and the code amount has no margin as compared with the other channels. The central processing unit proceeds to step SP46 and executes the arithmetic processing of the following equation. Accordingly, the central processing unit sets the target code amounts NA, NB, and NC by allocating the margins BA and BB of the first and second channels to the third channel.

[0140]

(Equation 34)

On the other hand, if a negative result is obtained in step SP45, the central processing unit proceeds to step S45.
Move to P47. Here, the central processing unit determines whether or not the difference calculated in step SP32 for the third channel is a negative value, thereby determining whether or not the third channel has a sufficient code amount. If a positive result is obtained here, in this case, the first and third channels have a margin in the code amount, and the second channel has no margin in the code amount as compared with the other channels. The unit moves to step SP48,
The following arithmetic processing is executed. Thereby, the central processing unit allocates the spare BA and BC of the first and third channels to the second channel, and sets the target code amounts NA, NB, N
Set C.

[0142]

(Equation 35)

If a negative result is obtained in step SP47, the central processing unit proceeds to step S47.
Move to P49. In this case, since there is a margin in the code amount only for the first channel, and there is no margin for the other channels, the central processing unit performs the following arithmetic processing.
The spare BA of the first channel is allocated to the second and third channels according to the difference calculated in step SP32,
The target code amounts NA, NB, and NC are set.

[0144]

[Equation 36]

On the other hand, if a negative result is obtained in step SP44, the central processing unit proceeds to step S44.
Move to P50. Here the central processing unit is
By determining whether or not the difference calculated for the channel in step SP32 is a negative value, it is determined whether or not the second channel has a sufficient code amount. If a positive result is obtained here, the central processing unit proceeds to step SP51, and similarly performs processing for the third channel.
It is determined whether or not the code amount has a margin.

Here, if a positive result is obtained, the central processing unit proceeds to step SP52, and in this case, since there is a margin in the code amount in the second and third channels, the central processing unit executes the following arithmetic processing. As a result, the central processing unit sets the margins BB and BC of the second and third channels to the first.
Allocation to channels, target code amount NA, NB, NC
Set.

[0147]

(37)

On the other hand, if a negative result is obtained in step SP51, the central processing unit proceeds to step S51.
Move to P53. In this case, since there is a margin in the code amount only for the second channel, and there is no margin for the other channels, the central processing unit executes the arithmetic processing of the following equation, thereby calculating the margin BB of the second channel by step It is allocated to the second and third channels according to the difference calculated in SP32, and the target code amounts NA, NB, and NC are set.

[0149]

(38)

If a negative result is obtained in step SP50, the central processing unit proceeds to step S50.
Move to P54. In this case, since there is no margin in the first and second channels, there is a margin in the code amount for the third channel. This allows the central processing unit to:
By executing the following equation, the margin BC of the third channel is allocated to the first and second channels according to the difference calculated in step SP32, and the target code amount N
A, NB, and NC are set.

[0151]

[Equation 39]

By determining and allocating a code margin according to the sign of each of the differences PA, PB, and PC, the central processing unit determines that PA>
By obtaining the relationship of 0, PB> 0, PC <0,
1.15 [Mbps] calculated by the equation (32) is distributed to the first and second channels by the following equation, and the target code amount NA is calculated.
NB and NC are set.

[0153]

(Equation 40)

According to the above configuration, by allocating the code amount according to the degree of difficulty based on the average code amount, it is possible to guarantee the image quality based on the average code amount and to reduce the code amount according to the characteristics of the image. The digital video signal can be transmitted with an increased image quality.

(3) Other Embodiments In the above-described embodiment, as shown in equation (4), when the difficulty is calculated by weighting four parameters ME, IAC, DC, and FLT , But
The present invention is not limited to this, and the difficulty may be calculated by selectively using any of these parameters as needed.
Further, each weighting coefficient of the equation (4) may be adaptively switched or its value may be changed according to scene change, flash, type of material, and the like.

Furthermore, in the above-described embodiment, by calculating the degree of difficulty by weighting the four parameters ME, IAC, DC, and FLT, the code generated when the coding processing is indirectly performed under certain conditions is obtained. For the encoded data, the case where the parameter corresponding to the data amount of the encoded data is detected has been described. However, the present invention is not limited to this, and the encoding process is performed by using a quantization table fixed by preparing a separate encoder. , The amount of generated data may be detected, and thereby the parameter corresponding to the data amount of the encoded data may be directly detected.

In the first embodiment described above,
Set upper and lower limits for the two channels,
Although the case where the lower limit is set for the remaining channels has been described, the present invention is not limited to this, and can be widely applied to the case where only the upper limit is set and the case where only the lower limit is set.

Further, in the above-described second embodiment, the case where the presence or absence of a margin is detected and sorted is described. However, the present invention is not limited to this. Alternatively, the code amount of a channel having a margin may be allocated.

In the second embodiment described above,
As shown by the equation (26), the case has been described where the difference is detected from the equal code amount to each channel and the code amount is redistributed. However, the present invention is not limited to this, and the equal code amount is not limited to this. Instead, the difference may be detected from the code amount set for each channel and the code amount may be redistributed.

Further, in the above embodiment, GO
Although the case where the code amount is distributed in P units has been described, the present invention is not limited to this, and the code amount may be distributed in frame units, and further, the code amount may be distributed in multiple GOP units.

In the above embodiment, the MPE
Although the description has been given of the case where the encoding process is performed according to the G format, the present invention is not limited to this, and is widely applied to various encoding processes such as a case where the encoding process is performed by the Haar transform process instead of the discrete cosine transform process. be able to.

Further, in the above-described embodiment, a case has been described in which digital video signals of three channels are multiplexed. However, the present invention is not limited to this, and when digital video signals of various channels are multiplexed, Further, the present invention can be widely applied to a case where various digital signals are encoded and multiplexed.

[0163]

As described above, according to the present invention, the data amount to be allocated to each channel is set or specified in the range of the upper limit value and / or the lower limit value according to the data amount generated under certain conditions. By setting the data amount of each channel based on the data amount generated under certain conditions from the data amount thus set, it is possible to reduce the image quality deterioration of each channel.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a target amount calculation process of a central processing unit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a multiplexing device according to a first embodiment.

FIG. 3 is a block diagram showing an encoding circuit of FIG. 2;

FIG. 4 is a block diagram showing the encoder of FIG. 2 in detail.

FIG. 5 is a block diagram showing an intra AC detection circuit shown in FIG. 3;

FIG. 6 is a block diagram illustrating a flatness detection circuit of FIG. 3;

FIG. 7 is a flowchart illustrating a processing procedure of a central processing unit of FIG. 2;

FIG. 8 is a flowchart showing a processing procedure following FIG. 1;

FIG. 9 is a flowchart illustrating a target amount calculation process of the central processing unit according to the second embodiment of the present invention.

FIG. 10 is a flowchart showing a redistribution process for a code amount margin in FIG. 9;

FIG. 11 is a block diagram showing a conventional multiplexer.

FIG. 12 is a block diagram showing the encoder of FIG. 11;

[Explanation of symbols]

1, 20 ... Multiplexer, 2A-2C, 24A-24C
…… Encoder, 8, 54 …… Motion detection circuit, 21A-
21C: coding circuit, 22A to 22C: parameter calculation circuit, 23A to 23C: FIFO, 28: intra AC detection circuit, 40: flatness detection circuit, 5
3, 55 cumulative accumulator

Claims (24)

[Claims] A multiplexing apparatus for generating multiplexed data by time-division multiplexing multiplexed data generated by encoding processing of digital signals of a plurality of channels by encoding means and by multiplexing means. Detecting a parameter corresponding to a data amount of the encoded data generated by the encoding process under a certain condition, and detecting each parameter in the multiplexed data within a range of an upper limit and / or a lower limit set for the channel. A multiplexing apparatus, comprising: controlling an encoding process by said encoding means so that a data amount of said encoded data of a channel becomes a data amount corresponding to said parameter. 2. The method according to claim 1, wherein the digital signal is a digital video signal, and the parameter is detected by measuring a data amount generated by encoding the digital video signal in a predetermined block unit. The multiplexing device according to claim 1. 3. The multiplexing apparatus according to claim 1, wherein said digital signal is a digital video signal, and said parameter is detected by integrating a luminance level of said digital video signal. 4. The digital signal is a digital video signal, and the parameter is detected by integrating an absolute value of a level difference between a luminance level of the digital video signal and a reference level. Item 3. The multiplexing device according to Item 1. 5. The method according to claim 1, wherein the digital signal is a digital video signal, and wherein the parameter is detected by counting a portion where a change in luminance level is large or small in a diagonal direction of an image based on the digital video signal. The multiplexing device according to claim 1, wherein 6. The digital signal is a digital video signal, the encoded data is generated by orthogonally transforming a difference signal between frames or fields of the digital video signal, and the parameter is the difference signal 2. The multiplexing apparatus according to claim 1, wherein the absolute value of is accumulated and detected. 7. A multiplexing apparatus for generating multiplexed data by time-division multiplexing the coded data of a plurality of channels generated by encoding each of the digital signals of the plurality of channels by the encoding means by the multiplexing means. Detecting a parameter corresponding to a data amount of the encoded data generated by the encoding process under a certain condition, and correcting a reference data amount set for each channel by the parameter to obtain target data of each channel. Setting the amount, so that the data amount of the coded data of each channel in the multiplexed data is the target data amount,
A multiplexing device for controlling an encoding process by said encoding means. 8. The digital signal is a digital video signal, and the parameter is detected by measuring an amount of data generated by encoding the digital video signal in a predetermined block unit. The multiplexing device according to claim 7. 9. The multiplexing apparatus according to claim 7, wherein said digital signal is a digital video signal, and said parameter is detected by integrating a luminance level of said digital video signal. 10. The digital signal is a digital video signal, and the parameter is detected by integrating an absolute value of a level difference between a luminance level of the digital video signal and a reference level. Item 8. The multiplexing device according to Item 7. 11. The digital signal is a digital video signal, and the parameter is that a point where a change in luminance level is large or small is detected in a diagonal direction of an image by the digital video signal. The multiplexing device according to claim 7, wherein 12. The digital signal is a digital video signal, the encoded data is generated by orthogonally transforming a difference signal between frames or fields of the digital video signal, and the parameter is the difference signal 8. The multiplexing apparatus according to claim 7, wherein the absolute value of is detected by accumulating. 13. A multiplexing method for generating multiplexed data by time-division multiplexing of coded data of a plurality of channels generated by encoding processing of digital signals of a plurality of channels by an encoding means by a multiplexing means. Detecting a parameter corresponding to a data amount of the encoded data generated by the encoding process under a certain condition, and detecting each parameter in the multiplexed data within a range of an upper limit and / or a lower limit set for the channel. A multiplexing method, characterized by controlling an encoding process by said encoding means so that a data amount of said encoded data of a channel becomes a data amount corresponding to said parameter. 14. The digital signal is a digital video signal, and the parameter is detected by measuring an amount of data generated by encoding the digital video signal in predetermined block units. The multiplexing method according to claim 13. 15. The multiplexing method according to claim 13, wherein said digital signal is a digital video signal, and said parameter is detected by integrating a luminance level of said digital video signal. 16. The digital signal according to claim 16, wherein the parameter is detected by integrating an absolute value of a level difference between a luminance level of the digital video signal and a reference level. Item 14. The multiplexing method according to Item 13. 17. The digital signal is a digital video signal, and the parameter is that a point where a change in luminance level is large or small is counted and detected in an oblique direction of an image based on the digital video signal. 14. The multiplexing method according to claim 13, wherein: 18. The digital signal is a digital video signal, the encoded data is generated by orthogonally transforming a difference signal between frames or fields of the digital video signal, and the parameter is the difference signal 14. The multiplexing method according to claim 13, wherein the detection is performed by accumulating the absolute value of. 19. A multiplexing method for generating multiplexed data by time-division multiplexing the coded data of a plurality of channels generated by respectively coding digital signals of the plurality of channels by the coding means by the multiplexing means. Detecting a parameter corresponding to a data amount of the encoded data generated by the encoding process under a certain condition, and correcting a reference data amount set for each channel by the parameter to obtain target data of each channel. Setting the amount, so that the data amount of the coded data of each channel in the multiplexed data is the target data amount,
A multiplexing method characterized by controlling an encoding process by the encoding means. 20. The digital signal comprising a digital video signal, wherein the parameter is detected by measuring an amount of data generated by encoding the digital video signal in a predetermined block unit. The multiplexing method according to claim 19. 21. The multiplexing method according to claim 19, wherein said digital signal is a digital video signal, and said parameter is detected by integrating a luminance level of said digital video signal. 22. The digital signal comprising a digital video signal, wherein the parameter is detected by integrating an absolute value of a level difference between a luminance level of the digital video signal and a reference level. Item 20. The multiplexing method according to Item 19. 23. The digital signal is a digital video signal, and the parameter is such that a position where a change in luminance level is large or small is counted and detected in an oblique direction of an image based on the digital video signal. 20. The multiplexing method according to claim 19, wherein: 24. The digital signal is a digital video signal, the encoded data is generated by orthogonally transforming a difference signal between frames or fields of the digital video signal, and the parameter is the difference signal 20. The multiplexing method according to claim 19, wherein the absolute value of the sum is detected by accumulating.