JPH1141071A - Latch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS without increasing the circuit scale
With a simple circuit configuration based on a differential pair, the operation of the latch circuit is ensured and stable. SOLUTION: Each drain of first and second MOS transistors is connected to a power supply potential via a load circuit, and each source is commonly connected to a constant current source to form a differential pair. The drain of the first MOS transistor is connected to the gate of the second MOS transistor, and the transfer switch circuit, which is controlled to be turned on by a clock signal, is interposed in series between the gate of the first MOS transistor and the input line. In a latch circuit for holding and outputting a binary signal appearing on an input line in synchronization with the clock signal,
First MOS transistor and / or second MOS
A feedback circuit is provided for positively feeding the drain voltage of the transistor to the gate of the first MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to a latch circuit, and further to a MOS-structured latch circuit for holding and outputting a binary logic signal in synchronization with a clock signal. The present invention relates to a technology effective when used for an address input buffer of a so-called on-chip RAM incorporated in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art For example, in an on-chip RAM, 2
In order to make the inter-bit timing of a multi-bit address signal input as a value logic signal uniform, it is effective to use a buffer with a latch function for holding the address signal in synchronization with a clock signal (for example, published by Nikkei BP). "Nikkei Electronics September 14, 1981 issue (n
o. 273) "174-200).

In order to construct this buffer with a latch function, the present inventors studied a MOS-structured latch circuit as shown in FIG.

[0004] The latch circuit 1 shown in FIG. 4 is not disclosed, but has been studied by the present inventors prior to the present invention, and includes n channel MOS transistors N1 to N4, p
It is composed of channel MOS transistors P1 to P5, inverters (logic inversion circuits) L1 to L6, and the like.

Here, N1 and N2 form a MOS differential pair 11 whose sources are commonly connected. N3 forms a constant current source for supplying a constant current from the common source to the reference potential Vss side. P1 and P2 form a drain load circuit 12 for N1 by being interposed in series between the drain of N1 and the power supply potential Vdd. Similarly, P3 and P4 form a drain load circuit 13 for N2 by being interposed in series between the drain of N2 and the power supply potential Vdd. N4 and P5 are N
A bidirectional transfer switch circuit 14 interposed in series between one gate and the input line. Inverter L 1 transmits the buffer of address input signal An to the input side of switch circuit 12. Inverters L2 to L4 are switch circuits 1
4 is controlled on / off by a clock signal CK. Inverters L5 and L6 form an output buffer.

In the circuit 1 described above, a kind of sampling and holding circuit is formed by the switch circuit 14 and the gate capacitance Cg of N1, and a kind of positive feedback loop is formed by connecting the drain of N1 to the gate of N2. Have been. When the switch circuit 14 is turned on by the clock signal CK, an input signal is applied to the gate of N1 through the switch circuit 14. This gives N
One gate capacitance Cg is charged to either high or low according to the logic level of the input signal. This charging voltage (Vg) is maintained as the gate voltage Vg even after the switch circuit 14 returns to the off state.

Here, if the gate voltage Vg of N1 is charged to a high level, N1 is turned on and N2 is turned off, and a stable first latch state is formed. Also,
When the gate voltage Vg of N1 is charged to the low level, on the contrary, N1 is turned off and N2 is turned on, so that a second latch state is formed in which the state is stabilized. In this way,
One of the two latch states is set by the logic level of the input signal when the switch circuit 14 is turned on by the clock signal CK. This latch state is taken out from the drains of N1 and N2 and output via inverters L5 and L6 (+ An
/ -An).

[0008]

However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, in the above-described latch circuit 1, as shown in FIG. 5, there is a timing difference between the ON period ton of the switch circuit 14 set by the clock signal CK and the definite period tst of the input signal An. Or the rise / fall time of the input signal An becomes longer, the gate voltage Vg when the switch circuit 14 returns from on to off becomes high or low of 2
It may be held at an intermediate level that has nothing to do with any of the value logic levels. If the gate voltage Vg is held at this intermediate level, the latch state of the latch circuit 1 becomes very unstable, and there is a problem that malfunctions easily occur due to noise and the like.

If a master-slave type latch circuit is used as a countermeasure against the above-mentioned problem, a reliable and stable latch operation can be expected. However, in this case, there is another problem that the circuit scale becomes large and the number of required elements is greatly increased.

An object of the present invention is to provide a technique for ensuring a stable and stable operation of a latch circuit with a simple circuit configuration based on a MOS differential pair without increasing the circuit scale. Is to do.

The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones will be briefly described as follows.

That is, the drains of the first and second MOS transistors (N1, N2) are connected to the power supply potential (Vdd) via the load circuits (12, 13), respectively.
In addition, a differential pair (11) is formed by commonly connecting each source to the constant current source (N3), and the drain of the first MOS transistor (N1) is connected to the gate of the second MOS transistor (N2). By interposing a transfer switch circuit (14), which is turned on by a clock signal (CK), in series between the gate of the first MOS transistor (N1) and the input line, a binary signal appearing on the input line is obtained. Is the clock signal (CK)
And a latch circuit (1) for holding and outputting in synchronism with a feedback circuit for positively feeding back the output state of the latch circuit (1) to the gate of the first MOS transistor (N1) as a DC voltage. 15) is provided.

According to the above-described means, the gate potential of the first MOS transistor is maintained at the intermediate level by the positive feedback operation such as latching the gate voltage to the high or low logic level. Can be avoided. At this time, the positive feedback operation is achieved by a driving capability that only brings the gate voltage from the intermediate level to either high or low. That is, MOS
It is only necessary to have a small load driving capability of only the gate capacitance of the transistor.

With this structure, the operation of the latch circuit can be made reliable and stable with a simple circuit configuration based on the MOS differential pair without increasing the circuit scale.
Is achieved.

Further, the first MOS transistor (N
1) and / or second MOS transistor (N2)
Is preferably fed back to the gate of the first MOS transistor (N1). Thereby, the gate voltage of the first MOS transistor (N1) can be latched at either the high or low level.

Further, as the feedback circuit (15), there is provided a CMOS inverter which is complementarily driven by both drain voltages of the first and second MOS transistors (N1, N2), and a node output of the CMOS inverter is a first output. Is connected to the gate of the MOS transistor (N1). Thus, the operation of latching the gate voltage (Vg) of the first MOS transistor (N1) at either the high or low level can be reliably performed.

Further, as the switch circuit (14),
A p-channel MOS transistor (P5) and an n-channel MOS transistor (N4) are connected in parallel between the drains and the sources and connected so as to be simultaneously turned on / off by a clock signal (CK). .

In addition, an n-channel MOS transistor is used as the first and second MOS transistors (N1, N2), and a drain load circuit (12) of the first MOS transistor (N1) has a second MOS transistor (N1).
A p-channel MOS transistor (P2) having a gate connected to the drain of the transistor (N2) and a p-channel MOS transistor (P1) having a gate to which a clock signal (CK) is applied are connected in parallel between the drains and the sources. And the drain load circuit (13) of the second MOS transistor (N2)
A p-channel MOS transistor (P4) having a gate connected to the drain of the OS transistor (N1) and a p-channel MOS transistor (P3) having a gate to which a clock signal (CK) is applied are connected in parallel between the drains and the sources. To do.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a latch circuit to which the technique of the present invention is applied.

The latch circuit 1 shown in FIG.
OS transistors N1 to N5, p-channel MOS transistors P1 to P6, inverter (logic inversion circuit) L1
L7 and the like.

Here, the MOS transistors N1 and N2 form a MOS differential pair 11 whose sources are commonly connected.
The MOS transistor N3 forms a constant current source for supplying a constant current from the common source to the reference potential Vss side.

The MOS transistors P1 and P2 are connected in parallel with each other at their drains and at their sources, and form a drain load circuit 12 for the MOS transistor N1 by being interposed in series between the drain of the MOS transistor N1 and the power supply potential Vdd. Similarly, the MOS transistor P
3 and P4 are connected in parallel between the drains and the sources, and the drain of the MOS transistor N2 and the power supply potential V
By interposing in series between dd and dd, the drain load circuit 13 of the MOS transistor N2 is formed. Further, M
The clock signal CK is applied to each gate of the OS transistors P1 and P3, the gate of the MOS transistor P2 is connected to the drain of the MOS transistor N1,
The gate of the transistor P4 is connected to the gate of the MOS transistor N2.

The MOS transistors N4 and P5 are connected in parallel between the drains and the sources to form a bidirectional transfer switch circuit 14. This switch circuit 14
Are serially interposed between the gate of the MOS transistor N1 and the input line (the output side of the inverter L1), and are simultaneously turned on / off by a clock signal CK supplied through the inverters L2 to L4. Inverter L 1 transmits the buffer of address input signal An to the input side of switch circuit 12.

The inverters L5 and L6 form an output buffer of the latch circuit 1.

The MOS transistors N5 and P6 and the inverter L7 form a feedback circuit 15 for positively feeding back the output state of the latch circuit 1 to the gate of the MOS transistor N1 as a DC voltage. In this case, the feedback circuit 15 sets the voltage appearing at each drain of the MOS transistors N1 and N2 to MO
A loop is formed such that a positive feedback is made to the gate of the S transistor N1. MOS transistors N5 and P6 are connected to N1
Driven complementarily by the drain voltages of N2 and N2
A MOS inverter is formed, and the node output of the CMOS inverter is applied to the gate of the MOS transistor N1.

In this case, the load of the CMOS inverter is the gate capacitance Cg of the MOS transistor N1. Therefore, the MOS transistors N5 and P6 are formed in such an element size that a driving capacity for charging or discharging the gate capacitance Cg to either high or low can be obtained.

Next, the operation will be described.

In the circuit 1 described above, first, a kind of sampling and holding circuit is formed by the switch circuit 14 and the gate capacitance Cg of the MOS transistor N1, and the drain of the MOS transistor N1 is N2.
And a kind of positive feedback loop is formed. When the switch circuit 14 is turned on by the clock signal CK, an input signal is applied to the gate of the MOS transistor N1 through the switch circuit 14. As a result, the gate capacitance Cg of the MOS transistor N1 becomes
Depending on the logic level of the input signal, it is charged to either high or low. This charging voltage (Vg) is maintained as the gate voltage Vg even after the switch circuit 14 returns to the off state.

Here, if the gate voltage Vg of the MOS transistor N1 is charged to a high level, the MOS transistor N1 is charged by the high level gate voltage Vg.
1 is turned on. When the MOS transistor N1 is turned on, the drain of the MOS transistor N1 falls to a low level, thereby turning off the MOS transistor N2. By turning off the MOS transistor N2, the drain of N2 rises to a high level. As a result, the MOS transistor P2 is turned off and P4 is turned on,
A positive feedback state occurs in which the drain of the OS transistor N1 is energized in the low level direction and the drain of the MOS transistor N2 is energized in the high level direction. As a result, the MOS transistor N1 is turned on and N2 is turned off. A stable first latch state is formed. When the gate voltage Vg of the MOS transistor N1 is charged to a low level, the operation reverse to the above is performed, and the MOS transistor N1 is turned off and N2 is turned on, so that a stable second latch state is formed.

As described above, one of the two latch states is set by the logic level of the input signal when the switch circuit 14 is turned on by the clock signal CK. This latch state corresponds to MOS transistors N1,
Taken out from each drain of N2, the inverters L5, L
6 (+ An / −An).

Further, in the circuit shown in FIG. 1, in addition to the above-described operation, the feedback circuit 15 formed by the MOS transistors N5, P6 and L7 raises the gate voltage Vg of the MOS transistor N1 to either high or low. A positive feedback operation is performed such that the signal is latched at the logical level of.

This positive feedback operation is performed as follows. That is, when the drain of the MOS transistor N1 is at the low level and the drain of the MOS transistor N2 is at the high level, the MOS transistor P6 is turned on to charge the gate voltage Vg of the MOS transistor N1 in the high level direction (charge). Up) is formed. Also, the MOS transistor N1
Of the MOS transistor N2
Is on the low level side, the MOS transistor N5 is turned on and the MOS transistor N1 is turned on.
A positive feedback loop is formed such that the gate voltage Vg is charged (charged down) in the low level direction.

Thus, for example, as shown in FIG.
There is a timing deviation between the ON period ton of the switch circuit 14 set by the clock signal CK and the definite period tst of the input signal An, or the input signal An
Switch circuit 14 returns from on to off when the gate voltage Vg of MOS transistor N1 is at an intermediate level that has no relation to either a high or low binary logic level. However, the gate voltage Vg of the MOS transistor N1 is charged to either high or low and stabilized by the above-described positive feedback operation.

As described above, the MOS transistor N1
Can be reliably prevented from becoming unstable due to the gate voltage Vg being at the intermediate level, and the fear of malfunction due to noise or the like can be eliminated. It should be further noted that the feedback circuit 15
The positive feedback operation is achieved by a drive capability that only brings the gate voltage Vg of the MOS transistor N1 from the intermediate level to either high or low. Therefore, the feedback circuit 15 only needs to have a small load driving capability of only the gate capacitance of the MOS transistor, and the element size of the MOS transistors P6 and N5 for obtaining the driving capability can be minimized. This achieves the object of ensuring the stable and stable operation of the latch circuit with a simple circuit configuration based on MOS differential pairs without increasing the circuit scale.

FIG. 3 shows an application example of the latch circuit according to the present invention.

The application example shown in FIG. 1 is a RAM incorporated in a semiconductor integrated circuit, and includes an address latch circuit 1 according to the present invention, a memory mat 2 having a large number of memory cells 21 arranged in a matrix, and a word. It comprises a decoder / driver 3 for selecting and driving lines, a data line selection circuit 4, a read / write circuit 5, a data input / output circuit 6, a clock distribution circuit 7, and the like. A0-An
Is an address signal, and Di / Do is storage input / output data.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, feedback circuit 15 may be a circuit that positively feeds the drain voltage of one of MOS transistors N1 and N2 to the gate of MOS transistor N1. However, in order to increase the reliability of the operation, it is desirable that both drain voltages of the MOS transistors N1 and N2 are positively fed back as in the above-described embodiment.

The feedback input signal of the feedback circuit 15 is supplied to the inverters L5 and L6 forming the output buffer of the latch circuit 1.
May be taken from the output signal of.

In the above description, the case where the invention made by the present inventor is applied to an address latch circuit which is a field of application as the background has been described. However, the present invention is not limited to this. It can be applied to a latch circuit.

[0044]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the operation of the latch circuit can be made reliable and stable with a simple circuit configuration based on the MOS differential pair without increasing the circuit scale. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a latch circuit to which the technique of the present invention is applied.

FIG. 2 is a waveform chart showing an operation example of the latch circuit of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a RAM to which the latch circuit of the present invention is applied;

FIG. 4 is a circuit diagram showing a configuration of a latch circuit studied prior to the present invention;

FIG. 5 is a waveform chart showing an operation example of the latch circuit shown in FIG. 4;

[Explanation of symbols]

 Reference Signs List 1 latch circuit N1 to N5 n-channel MOS transistor P1 to P6 p-channel MOS transistor L1 to L7 inverter (logical inversion circuit) 11 MOS differential pair 12 drain load circuit 13 drain load circuit 14 transfer switch circuit 15 feedback circuit Vdd power supply potential Vss Reference potential CK Clock signal Cg Gate capacitance Vg Gate voltage

Claims (5)

[Claims] 1. A differential pair is formed by connecting each drain of a first and a second MOS transistor to a power supply potential via a load circuit and connecting each source to a constant current source in common. By connecting the drain of the first MOS transistor to the gate of the second MOS transistor and interposing a transfer switch circuit, which is turned on by a clock signal, in series between the gate of the first MOS transistor and the input line, A latch circuit for holding and outputting a binary signal appearing on the input line in synchronization with the clock signal,
A latch circuit comprising: a feedback circuit that positively feedbacks the output state of the latch circuit as a DC voltage to the gate of a first MOS transistor. 2. The feedback circuit according to claim 1, wherein a voltage appearing at the drain of the first MOS transistor and / or the second MOS transistor is fed back to the gate of the first MOS transistor. The latch circuit according to claim 1. 3. The first and second MOs as a feedback circuit.
A CMOS inverter driven complementarily by both drain voltages of the S transistor;
3. The latch circuit according to claim 1, wherein a node output of the inverter is connected to a gate of the first MOS transistor. 4. A switch circuit comprising a p-channel MOS transistor and an n-channel MOS transistor connected in parallel between drains and sources and connected to be simultaneously turned on / off by a clock signal. 4. The latch circuit according to claim 1, wherein: 5. An n-channel MOS transistor is used as the first and second MOS transistors, and a drain load circuit of the first MOS transistor includes:
A second MOS transistor comprising a p-channel MOS transistor having a gate connected to the drain of the second MOS transistor and a p-channel MOS transistor having a gate to which a clock signal is applied connected in parallel between the drains and the sources; The drain load circuit of the transistor is configured such that a p-channel MOS transistor having a gate connected to the drain of the first MOS transistor and a p-channel MOS transistor to which a clock signal is applied to the gate are connected in parallel between the drain and the source. 5. The device according to claim 1, wherein
The latch circuit according to any one of the above.