JPH1140801A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: A method for forming a semiconductor device capable of forming a shallow and low-resistance junction by suppressing accelerated diffusion of impurities in a silicon semiconductor layer 3 is provided. SOLUTION: In a method of manufacturing a semiconductor device in which a MOS transistor having an LDD diffusion layer 21 is formed in a semiconductor layer 3, a gate electrode 9 is formed on the semiconductor layer 3, and ion implantation is performed on the semiconductor layer 3 to make the semiconductor layer 3 amorphous. The layer 13 is formed. When the first heat treatment is performed, dislocation loops 15 are formed at the interface between the amorphous layer and the crystal layer. Furthermore, LD
A diffusion source insulating film containing an impurity of a D diffusion layer is formed on the semiconductor layer. This insulating film 17 is etched back to form side wall insulating films 19 on both side surfaces of the gate electrode 9. Thereafter, a second heat treatment is performed to diffuse impurities from the sidewall insulating film 19 to the semiconductor layer 3 in a solid phase. Since the interstitial silicon is absorbed by the dislocation loop 15, the enhanced diffusion of impurities is suppressed when the LDD diffusion layer 21 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a dislocation loop in a silicon semiconductor layer to thereby suppress the accelerated diffusion of impurities, which is suitable for fine large-scale integrated circuits (LSI). The present invention relates to a method for manufacturing a diffusion layer having a shallow junction.

[0002]

2. Description of the Related Art Metal-Oxide-Se
LSI having a semiconductor (MOS) type semiconductor device
Has achieved both high integration and high performance by promoting miniaturization. For this reason, the electric field strength has gradually increased in the vicinity of the drain diffusion layer (SD diffusion layer) of the MOS type semiconductor device. In order to reduce the concentration of the electric field, a so-called LDD (Lightly Doped Drain) having a lower concentration than the SD diffusion layer is provided near the channel side surface of the SD diffusion layer.
A diffusion layer is formed.

In a conventional manufacturing method, an LDD diffusion layer is formed as follows. First, a gate electrode is formed on a silicon semiconductor layer. Next, ions are implanted into the gate electrode in a self-aligned manner to introduce impurities into the silicon semiconductor layer. Further, annealing and activation are performed by performing heat treatment to form an LDD diffusion layer. After this,
A sidewall oxide film is formed on the side surface of the gate electrode, and ions are implanted into the gate electrode and the sidewall oxide film in a self-aligned manner to form an SD diffusion layer. By such a method, an LDD diffusion layer is formed near the channel side surface of the SD diffusion layer.

[0004]

As described above, in an LSI having a MOS type semiconductor device, in order to promote further miniaturization and achieve both high integration and high performance, it is necessary to further reduce the depth of the LSI. A technique for forming a low-resistance LDD diffusion layer is required. For example, if the design rule is 0.13μ
In the m-generation MOS LSI, the junction depth Xj is 40 [n].
m] or less, and a sheet resistance ρs of 2 [kΩ / □] or less is required.

However, according to the conventional formation method, the diffusion layer having the above-described characteristics required for miniaturization is formed because impurities in the LDD diffusion layer are diffused at a high speed during heat treatment for activation and annealing. Is becoming more difficult. This phenomenon is particularly remarkable for boron (B), which is the only practical P-type impurity, that is, a P-type dopant.

As a technique for solving this problem, an oxide film containing an impurity for an LDD diffusion layer, for example, a silicon oxide film doped with boron (Boro) is formed on the side wall of the gate electrode.
The BSG solid-phase diffusion method of forming boron (silicate glass: BSG) and diffusing boron from the oxide film into the silicon semiconductor layer by high-temperature, short-time heat treatment has been attracting attention.

However, Miyake's report (J. Electrochem. S.
oc., Vol. 138, No. 10, October 1991, "Diffusion of Bo
ron into Silicon from Borosilicate Glass Using Rap
According to “id Thermal Processing”), B ₂
It has been reported that boron, which is basically contained in the form of O ₃ , diffuses in the silicon semiconductor layer by the following mechanism. First, when heated, B is decomposed and released by the reaction of 2B ₂ O ₃ + 3Si → 4B + 2SiO ₂ (1) and thermally diffused. At this time, the silicon substrate is also oxidized by the released oxygen,
At the same time, silicon atoms (interstitial silicon) are also emitted between crystal lattices. The mechanism is that the interaction between boron and interstitial silicon causes enhanced diffusion of boron.
When the enhanced diffusion of the dopant occurs as described above, there is a problem that it is difficult to form a shallow junction even in the above-mentioned method, which has attracted attention.

In addition, in an actual LSI manufacturing process, since there are a plurality of CVD steps in which the temperature is about 700 ° C. and the growth time is several hours, the reaction proceeds in a similar mechanism in these steps. As a result, accelerated diffusion of boron occurs, and as a result, a junction may not be formed to be shallow.

On the other hand, regarding impurity diffusion in a silicon semiconductor, a report on a simulation model ("A New Boron Diffusion Model Incorporating the
Dislocation Loop Growth ", International Electron
Device Meeting, IEDM94-873, 35.4.1). This report, together with a simulation model of boron rearrangement due to diffusion, discloses that silicon present between crystal lattices is absorbed by dislocation loops at high temperatures.

It is an object of the present invention to provide a method of forming a semiconductor device capable of forming a shallow and low-resistance junction suitable for LSI by suppressing accelerated diffusion of impurities in a silicon semiconductor layer.

[0011]

Means and action for solving the problem
The present invention has the following configuration.

[0012] A method of manufacturing a semiconductor device according to the present invention comprises:
In a method of manufacturing a semiconductor device in which a MIS type semiconductor device having an LDD diffusion layer is formed in a silicon semiconductor layer, a gate electrode forming step of forming a gate electrode on the silicon semiconductor layer, and ion implantation into the silicon semiconductor layer are performed. An amorphized layer forming step of forming a structure in the silicon semiconductor layer; a heat treatment step of performing a first heat treatment for forming dislocation loops in the silicon semiconductor layer after the amorphized layer forming step; Forming an impurity-containing diffusion source insulating film for an LDD diffusion layer on a silicon semiconductor layer,
A side wall forming step of etching the diffusion source insulating film to form a side wall insulating film on the side surface of the gate electrode and a second heat treatment of solid-phase diffusing impurities from the side wall insulating film into the silicon semiconductor layer to form an LDD diffusion layer are performed. And a diffusion step.

As described above, when heat treatment is performed after the crystal structure of the semiconductor layer is changed to an amorphous structure by performing ion implantation, when the crystal structure of the semiconductor layer recovers, the vicinity of the interface between the amorphous semiconductor layer and the crystal portion is formed. A dislocation loop is formed. When a sidewall insulating film is formed on the side surface of the gate electrode and a second heat treatment is performed to diffuse solid-phase impurities from the sidewall insulating film to the semiconductor layer, the impurity is generated as a result of the reaction of the above formula (1). Interstitial silicon is absorbed in the dislocation loop. Therefore, when forming the LDD diffusion layer, it is possible to suppress the accelerated diffusion of the impurity caused by the interaction between the impurity and the interstitial silicon.

A method for manufacturing a semiconductor device according to the present invention comprises:
In the amorphized layer forming step, ion implantation may be performed using at least one ion species of XY _n ⁺ type ions _where X is a group IV element, Y is a VII element, and n = 1, 2, and 3. Good.

When an amorphous layer is formed using such XY _n ⁺ type ion species, the energy of ion implantation is (ion implantation energy) × (ion implantation energy) ×
Since the distribution is performed according to the ratio of (mass number of X or Y atom) and ((mass number of X atom) + (mass number of Y atom) × n), the kinetic energy of each constituent atom can be reduced.
By utilizing this to control the projection range of ions by changing the kinetic energy of each constituent atom, the depth of the silicon layer to be made amorphous can be changed. Therefore, the depth at which the dislocation loop is formed can be changed, so that the depth at which the junction is formed can be controlled. Also, if the ion species is XY
_{Since it is an n} ⁺ type, the range of choice of ion species for this is also widened.

The method for manufacturing a semiconductor device according to the present invention comprises:
The method further includes an element isolation step of forming an isolation insulating film for isolating the MIS type semiconductor device in the element isolation region before the gate electrode formation step. The ion implantation in the layer forming step may be performed in a self-aligned manner with respect to the gate electrode and the isolation insulating film.

As described above, if the ion implantation for forming the amorphous layer is performed in a self-aligned manner with respect to the gate electrode and the isolation insulating film, the region including the portion necessary for forming the LDD diffusion layer can be formed. Dislocation loops can be formed selectively.

In the method of manufacturing a semiconductor device according to the present invention, in the step of forming an amorphized layer, X is a group IV element, Y is a VII element, XY _n ⁺ type ions with n = 1, 2, 3 and X ^The ion projection range is Rp for any ion species of the ⁺ type ion and impurity distribution by ion implantation.
[Nm] and standard deviation as △ Rp [nm], LDD
Assuming that the junction depth of the diffusion layer is Xj [nm], Xj> Rp
+ 4 × △ Rp and 1 × 10 ¹⁴ [cm
⁻² ] to 5 × 10 ¹⁵ [cm ⁻² ] or less, and the ion implantation may be performed depending on the dose of the ion implantation.

If the ion species is selected as necessary, the energy distributed to each constituent atom, that is, the effective ion implantation energy can be changed. For this reason, since the projection range of each ion can be changed, it is easy to realize Xj> Rp + 4 × △ Rp. If Xj> Rp + 4 × △ Rp is realized by performing ion implantation with such energy and dose, an amorphous layer can be formed at a suitable position, and most dislocation loops are included in the LDD diffusion layer. Because you can
A bond with good characteristics can be formed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. In addition, the same portions are denoted by the same reference numerals, and overlapping description will be omitted.

(First Embodiment) FIGS. 1 (a) to 1 (c)
2A to 2C are process cross-sectional views showing one embodiment of a method for manufacturing a semiconductor device of the present invention. Based on these drawings, a case in which a silicon semiconductor substrate (hereinafter, referred to as a substrate) is used as a silicon semiconductor layer and a MOS type P-channel transistor is used as an example of a MIS type semiconductor device to form this LDD diffusion layer (SD extension) Will be described. Note that the silicon semiconductor layer is not limited to a silicon substrate, and a silicon semiconductor layer epitaxially grown on this insulating layer may be used. Also, an N-type substrate is used as the conductivity type, but N-type
A transistor may be formed inside a mold well or the like.

First, an element isolation step of forming an isolation insulating film 5 for isolating a MOS transistor in an element isolation region of the substrate 3 is performed (FIG. 1A). The insulating film 5 formed in this region is formed so as to surround the transistor forming region,
Thereby, the respective transistor regions are electrically separated. As the insulating film 5, for example, LOCOS method, L
A silicon oxide film formed by the OPOS method or the like, and a chemical vapor deposition (CV)
An oxide film or the like formed by the method D) can be used.

Subsequently, an impurity for controlling the threshold value of the MOS transistor and an impurity for preventing punch-through are introduced immediately below the channel (not shown). These can be performed by, for example, an ion implantation method or the like.
Next, the gate insulating film 7 is formed so as to cover the channel portion. As the insulating film 7, for example, a silicon oxide film formed by thermally oxidizing the substrate 3 can be used. Subsequently, a gate electrode 9 is formed on the gate insulating film 7. This electrode is formed by depositing, for example, polysilicon, polycide, or the like on the substrate 3, forming a pattern of the gate electrode 9 using photolithography, and performing anisotropic etching.

Next, the process proceeds to an amorphized layer forming step of forming an amorphized layer 13 in the transistor forming region by performing ion implantation 11 (FIG. 1B). The amorphized layer 13 is formed in a region including at least a portion for forming the LDD diffusion layer. For this purpose, a photolithography technique can be used. Further, it may be formed over the entire transistor formation region. For this purpose, it is preferable to perform the ion implantation 11 on the element isolation region 5 and the gate electrode 9 in a self-aligned manner. When the ion implantation 11 is performed as described above, the amorphized layer 13 is formed in a self-aligned manner, in other words, in a transistor forming region except a channel portion below the gate electrode 9. That is, it is formed on the surface of the substrate along the side surface of the channel portion.
Therefore, the dislocation loop 15 to be formed later is also formed in a self-aligned manner. That is, the dislocation loops 15 are formed in the source / drain diffusion layers (SD diffusion layers) and the LDD diffusion layers without requiring a margin for alignment, so that many dislocation loops 15 are included inside these diffusion layers. This is preferable in that it can be performed. If there is a region where the amorphous layer 13 is not desired to be formed, the region may be covered with a mask material (not shown) such as a resist using a photolithography technique before the ion implantation. As an example, there is a case where the dislocation loop 15 is formed only in one of the P-channel transistor and the N-channel transistor.

The ion implantation energy is selected according to the depth at which the amorphous layer 13 is formed. Ion implantation 1
The one ion species may be any one that does not affect the electrical characteristics of the substrate silicon, such as conductivity type and resistance, and has good manufacturing process consistency. As such, for example, X is a group IV element, Y is a VII element,
It is preferred to use at least one of X ⁺ -type ions of n = 0 in XY _n ⁺ -type ions and XY _n ⁺ -type ions of n = 1, 2, 3. As the element X, germanium (Ge), silicon (Si), or the like is preferable. In particular, Si is optimal because it is the same element as the silicon semiconductor layer. As the element Y, fluorine (F) or the like is preferable. In particular, since fluorine is used as ion species BF ₂ ⁺ for ion implantation for introducing boron impurities, it is considered that the compatibility with the process is good. Examples of the XY _n ⁺ type ions include SiF ₃ ⁺ , SiF ₂ ⁺ , and SiF ^+, which are actually observed as ions in an ion implantation apparatus.

When ion implantation 11 is performed using such XY _n ⁺ type ion species, the energy of ion implantation is (ion implantation energy) × (X or mass number of Y atoms) for each constituent atom. And ((mass number of X atom) + (Y
Atomic mass number) x n).
The kinetic energy of each constituent atom can be changed without changing the acceleration energy itself of the ion implantation apparatus. As an example, the acceleration energy of the device is set to 10 [ke].
When ions are implanted SiF ⁺ in the V], the Si about 6 [keV], the energy of the F approximately 4 [keV] is allocated respectively. However, the silicon mass number was 28 and the fluorine mass number was 19. That is, the total acceleration energy is distributed to each of the constituent atoms, and each atom has a smaller kinetic energy than the total acceleration energy. Therefore, if the XY _n ⁺ type ion species is used, the projection range of the ions can be changed by changing the energy of each atom. Thereby, the depth of the silicon layer to be made amorphous can be selected.

It is preferable to select the ion implantation energy so that the depth of forming the amorphous layer 13 and the depth of the formed junction satisfy the relationship of Xj> Rp + 4 × △ Rp (2). Here, Rp [nm] is the ion projection range of ion implantation, that is, the distance measured from the substrate surface at the position where the number of distributed impurities is the largest, △ Rp [nm] is the standard deviation of the distribution of ion-implanted impurities, and Xj [ [nm] is the junction depth of the LDD diffusion layer. If such Xj is realized, L
The amorphized layer 13 can be formed at a suitable position where many dislocation loops 15 can be included in the DD diffusion layer. Therefore, a junction having good characteristics can be formed.

In particular, if the XY _n ⁺ type ion species is selected as necessary when forming a shallow junction, the projection range R of each ion corresponding to the energy distributed to each constituent atom can be obtained.
Since p, standard deviation △ Rp, and the like can be changed, low-energy ions can be effectively realized without lowering the acceleration energy of the apparatus. In other words, since it is easy to realize a small Rp, Xj> Rp + 4 × △ Rp
Is also easier to satisfy.

The distribution function forms of impurities, Rp and △ Rp, are changed by, for example, various ion species and implantation energies, and an experiment is performed to perform secondary ion mass spectrometry (Secondary Ion Mass Spectrometry).
These may be determined by examining the impurity distribution by the scopy (SIMS) method. LSS (Lindhad, Scharff,
Schott) theory. Further, since the LSS theory can be approximated by a Gaussian distribution having an average Rp and a standard deviation △ Rp, the LSS theory may be easily obtained using a Gaussian distribution. A distribution may be used.

The dose of the ion implantation 11 varies depending on the ion species, but is generally 1 × 10 ¹⁴ [cm ⁻² ] or more.
× 10 ¹⁵ [cm ^-2] The following dose are preferred. Such a range is preferred because the extent required by the 1 × 10 ¹⁴ does not occur sufficiently or does not occur amorphization in a dose of less than [cm ^-2], and 1 × 10 ¹⁴ [cm ^-2] or Becomes amorphous, and further 5 × 10 ¹⁵ [c
This is because there is no practical advantage even if the dose is increased beyond m ^-2 ].

The ion implantation 11 in this step is not limited to only one time, but may be performed a plurality of times as necessary to form the amorphous layer 13 to a predetermined depth or to a predetermined depth. You may.

Next, the process proceeds to a heat treatment step (FIG. 1C).
In this step, a first heat treatment for forming a dislocation loop 15 in the substrate 3 is performed. This heat treatment is performed, for example, in a non-oxidizing atmosphere, and RTA (Rapid Thermal Annealin).
It is preferable to use the g) method. Using the RTA method,
This is because the crystallinity by ion implantation can be recovered in a short time. As an example of the conditions according to this method, a condition of a temperature of 1000 ° C. and a time of 10 seconds is preferable.
Note that, without being limited to this method, annealing may be performed in a non-oxidizing atmosphere in a diffusion furnace. Further, as the non-oxidizing atmosphere, a nitrogen gas (N ₂ ), an argon (Ar) gas, or the like having good compatibility with the LSI manufacturing process is preferable. By this heat treatment, a transition loop 15 is formed near the interface between the amorphized layer 13 and the crystal part of the substrate 3, and the crystal structure destroyed by the ion implantation 11 is recovered and the amorphized layer 13 disappears. As an example of the density of the transition loop formed at this time, ion implantation 11 is performed under the conditions that the ion species is SiF ⁺ , the implantation energy is 10 [keV], and the dose is 3 × 10 ¹⁵ [cm ⁻² ]. When heat treatment was performed under the annealing conditions of 1.times.1
It is about 0 ¹⁰ [cm ^-2 ]. The presence or absence, position, etc. of the dislocation loop is determined by the transmission electron microscope (Transmission electron microscope).
It can be confirmed by analysis using ctron spectroscopy (TEM).

This first heat treatment is preferably carried out in a non-oxidizing atmosphere at a temperature of 700 ° C. to 1100 ° C. and a time of 1 second to 10 hours. . Such a condition is preferable that a dislocation loop is not sufficiently formed when the temperature is less than 700 [° C.] and the time is less than 1 [second], and the dislocation loop is decomposed when the temperature exceeds 1100 [° C.]. Because.

The amorphous layer forming step and the heat treatment step may be performed before forming the gate electrode 9. For example, the gate electrode 9 may be formed after the opening of the mask material is provided by photolithography in the region where the LDD diffusion layer 21 is formed to form the amorphous layer 13.

After the heat treatment step, an insulating film forming step is performed (FIG. 2A). In this step, the diffusion source insulating film 1 containing an impurity for the LDD diffusion layer, a so-called dopant, is formed.
7 is formed on the substrate 3. The insulating film 17 is formed on the entire surface of the substrate 3 and includes a silicon oxide film (SiO ₂ film), a silicon nitride oxide film (SiON film) or the like containing boron (boron), for example, a BSG film (Boro-Silicate). Glas
s) or a boron oxide film (B ₂ O ₃ film) or the like can be used. These films can be formed using, for example, a CVD method, a physical vapor deposition (PVD) method, or the like. An example of growth conditions is as follows.
As a condition for growing 0 [nm], Becomes The substrate surface is cleaned with a predetermined concentration of hydrofluoric acid (HF) before growth.

In the step of forming the insulating film, the concentration of the impurity contained in the insulating film 17 may be not less than 10 [mol%] and not more than 30 [mol%]. This range is preferable because when the impurity concentration is less than 10 [mol%], the influence of the interface oxide film is large and boron diffusion does not sufficiently occur, and when the impurity concentration exceeds 30 [mol%], B ₂ O ₃ decomposition occurs. This is because silicon (Si) is oxidized by oxygen (O) released at that time and the enhanced diffusion becomes so large that it cannot be controlled.

The impurities contained in the insulator 17 may be introduced in a separate step after the formation of the insulating film 17. However, since the insulating film 17 becomes the side wall insulating film 19 for forming the LDD, the impurities are contained as described above. Is a relatively thin insulating film. For this reason, it is preferable that the impurity be contained simultaneously with the growth of the insulating film 17 from the viewpoint of controllability of impurity introduction and reduction in the number of manufacturing steps.
In addition, as a method of separately introducing, there is ion implantation or the like.

Although the case of the P-type impurity has been described above,
Silicon oxide film (SiO ₂ film) for N-type impurities,
A silicon nitride oxide film (SiON film) containing phosphorus (phosphorus), for example, a PSG film (Phospho-Silicate Gla
ss) or a phosphorylated film (P ₂ O ₅ film) or the like can be used. These films can be grown by the same method as the film containing boron.

Next, a side wall forming step is performed (FIG. 2).
(B)). In this step, the insulating film 17 is etched,
Sidewall insulating film 1 on at least the drain side surface of gate electrode 9
9 is formed. As a method for forming the side wall insulating film 19, there is an overall etch-back method. In this method, the insulating film 17 is etched under the condition of anisotropic etching, and the etching is terminated when the film thickness of the flat portion is about the same as the thickness of the flat portion, for example, on both side surfaces of the gate electrode 9. This is a method in which the sidewall insulating film 19 is left. This method is a preferable method for forming the side wall because the side wall insulating film 19 can be formed on both side surfaces of the gate electrode 9 without using photolithography. The formation of the sidewall insulating film 19 is not limited to this. For example, before the etching, a step of forming a mask material using a photolithography technique in a region including at least the drain side surface of the gate electrode 9 is provided, and thereafter, the unnecessary insulating film 17 is removed by etching. Good. Further, a step of forming a mask material in a predetermined region other than the side surface of the drain by using a photolithography technique is provided, and thereafter, if an etch back is performed, a sidewall insulating film which becomes a source of impurities for solid-phase diffusion also in a portion where the mask material remains. 19 can be left. Therefore, a shallow diffusion layer can be simultaneously formed other than on the side wall of the gate electrode 9.

Next, the process proceeds to a diffusion step of performing a second heat treatment on the substrate 3 (FIG. 2B). By this heat treatment, impurities are solid-phase diffused from the side wall insulating film 19 to the substrate 3 to form the LDD diffusion layer 21. This heat treatment is performed, for example, in a non-oxidizing atmosphere, and it is preferable to use the RTA method. RT
This is because the method A can diffuse impurities in a short time and is suitable for forming a shallow junction.
An example of a condition according to this method is as follows.
[° C.] and a time of 10 [seconds] are preferable. The heat treatment method is not limited to the RTA method, and the impurity may be diffused in a non-oxidizing atmosphere in a diffusion furnace. As the non-oxidizing atmosphere, a nitrogen gas, an argon gas, or the like that is compatible with the LSI manufacturing process is preferable. By this heat treatment, impurities are solid-phase diffused from the sidewall insulating film 19 to the substrate 3 through the oxide film, and the LDD diffusion layer 21 is formed.

The second heat treatment may be performed in a non-oxidizing atmosphere at a temperature of 950 ° C. or more and 1050 ° C. or less and a time of 1 second or more and 30 seconds or less. Good. Such a range is preferable when the temperature is 9
If the temperature is less than 50 [° C.] and the time is less than 1 [second], the impurity in the diffusion layer will not have a sufficient concentration. Is 0.
This is because it is larger than about 2 [μm], which is too deep.

As a result of this heat treatment, an LDD diffusion layer 21 having a depth Xj is formed. The second heat treatment may be performed in any step after the formation of the sidewall insulating film 19 and before the deposition of a metal such as aluminum (Al) or titanium (Ti).

FIG. 3 is a schematic diagram for explaining the function of the dislocation loop. The diffusion of impurities in the substrate will be described with reference to FIG. Note that B indicates boron impurity and I indicates interstitial silicon. By performing the ion implantation 31, an amorphous layer 33 is formed on the surface of the substrate 30 (FIG. 3A). When annealing (first heat treatment) is performed to restore the crystallinity of the substrate 30, a transition loop 35 is formed near the interface between the amorphized layer 33 and the crystal part, and the amorphized layer 33 disappears (FIG. 9). 3 (b)). When a BSG film 37 is deposited on the substrate 30 and a second heat treatment is performed, a reaction of 2B ₂ O ₃ + 3Si → 4B + 2SiO ₂ proceeds, and boron is released and diffused during this reaction, and the interstitial silicon I Occurs. It is known that interstitial silicon I causes enhanced diffusion of boron B with the formation of the boron B complex. The generated interstitial silicon I diffuses into the substrate 30 together with boron B as indicated by an arrow 39 in FIG. In the region where the dislocation loop 35 exists, a part of the interstitial silicon I is absorbed by the dislocation loop 35 because it has a property of absorbing the interstitial silicon I (FIG. 3C). For this reason, the formation of a complex of boron B and interstitial silicon I is suppressed, and as a result, the accelerated diffusion of boron can be suppressed as indicated by an arrow 41 in FIG. Therefore, the control of impurity diffusion by the temperature and time of the heat treatment is facilitated, and the junction can be formed with good reproducibility. Further, by changing the formation position of the dislocation loop 35, a diffusion layer having a desired depth can be formed. Therefore, by forming the dislocation loop 35 at a shallow position, a shallow junction can be formed. Although the case where boron is used is described in the present embodiment,
Similar effects can be expected for phosphorus (P), which is an N-type impurity.

As described above, it is possible to introduce boron into the substrate while suppressing diffusion of boron due to enhanced diffusion.
For this reason, impurities can be sufficiently introduced, so that a shallow LDD diffusion layer 21 with reduced resistance can be formed.

It is preferable that the LDD diffusion layer 21 be formed so as to substantially include the dislocation loop 15 inside by the second heat treatment. For example, Xj> Rp + 4 × △ R
This is the case where the relationship of p is satisfied. By forming in this manner, it is possible to form a bond having better characteristics.

Hereinafter, description will be made with reference to FIG. L
After forming the DD diffusion layer 21, a source / drain diffusion layer (SD diffusion layer) 22 is formed. The SD diffusion layer 22
For example, it is formed by ion-implanting the element isolation region 5, the gate electrode 9, and the sidewall insulating film 19 in a self-aligned manner. Since the SD diffusion layer 22 is generally deeper than the LDD diffusion layer 21, the dislocation loop 15 formed in the transistor formation region excluding the channel region is included inside the diffusion layer 22.

Subsequently, an interlayer insulating film 23 is grown on the entire surface of the substrate 3. It is preferable that the interlayer insulating film 23 be planarized in order to form the wiring 27. For example, B
A PSG (Boro-Phopho-silicate Glass) film or the like is laminated, and then chemically mechanically polished (Chemical Mechanical Polishing).
g: CMP). Next, a contact hole is opened in the interlayer insulating film 23 on the SD diffusion layer 22 and the gate electrode 9 by anisotropic etching in order to make electrical connection to the SD diffusion layer 22 and the gate electrode 9. Tungsten (W) is selectively grown and buried in the contact hole to form a buried contact portion 25, and thereafter a metal layer is formed. The metal layer is
For example, a multilayer film made of TiN, Ti, Al, or the like is formed by a sputtering method or the like. A wiring pattern is formed thereon using photolithography, and the wiring 27 is formed by etching. By the wiring 27, electrodes such as MOS transistors can be connected to each other. Next, a passivation film, for example, a plasma SiON film or the like is formed thereon, and the passivation film in the bonding pad portion is removed by etching to provide an opening. Thus, the semiconductor device is completed. In the description of the present embodiment, the case where the number of metal wirings is one has been described, but it goes without saying that the present invention can be applied to a semiconductor device having a plurality of wiring layers.

As described above in detail, in the method of manufacturing a semiconductor device according to the present invention, an amorphous layer is formed on a substrate by performing ion implantation. Interstitial silicon is captured by using dislocation loops formed when the crystallinity of this layer is restored by heat treatment. Since interstitial silicon causes accelerated diffusion when solid-phase diffusion of impurities into a substrate, it is possible to suppress accelerated diffusion accompanying formation of a complex of interstitial silicon and impurities. For this reason, controllability of impurity diffusion at the time of the second heat treatment can be improved. Therefore, impurities can be sufficiently introduced without being affected by the enhanced diffusion, so that a shallow and low-resistance LDD diffusion layer can be formed.

[0049]

As described above in detail, according to the present invention, when heat treatment is performed after ion-implantation to form an amorphized layer, dislocation loops are formed near the interface of the amorphized layer. Thereafter, a side wall insulating film is formed on the side surface of the gate electrode, and a second heat treatment is performed to solid-phase diffuse impurities from the insulating film into the semiconductor layer. Is absorbed by the dislocation loop. Therefore, when forming the LDD diffusion layer,
Accelerated diffusion of impurities caused by the interaction between the impurities and interstitial silicon can be suppressed. Therefore, the controllability of impurity diffusion at the time of the second heat treatment can be improved, so that a shallow and low-resistance LDD diffusion layer can be formed.

[Brief description of the drawings]

FIGS. 1A to 1C are process cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 2A to 2C are process cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic diagram for explaining the operation of a dislocation loop.

[Description of References] 3 ... silicon substrate, 5 ... isolation insulating film (element isolation region),
7: gate insulating film, 9: gate electrode, 11: ion implantation, 13: amorphous layer, 15: dislocation loop, 17
... Diffusion source insulating film, 19 ... sidewall insulating film, 21 ... LDD diffusion layer, 22 ... SD diffusion layer, 23 ... interlayer insulating film, 25 ... buried contact, 27 ... wiring, 29 ... passivation film, 30 ... silicon substrate, 31 ... Ion implantation, 33 ... Amorphized layer, 35 ... Dislocation loop, 37 ... BSG film

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device in which a MIS type semiconductor device having an LDD diffusion layer is formed in a silicon semiconductor layer, wherein: a gate electrode forming step of forming a gate electrode on the silicon semiconductor layer; An amorphized layer forming step of forming an amorphous structure in the silicon semiconductor layer by performing ion implantation; and, after the amorphized layer forming step, a first heat treatment for forming dislocation loops in the silicon semiconductor layer is performed. A heat treatment step; and after this heat treatment step, an insulation film forming step of forming a diffusion source insulation film containing impurities for the LDD diffusion layer on the silicon semiconductor layer; and etching the diffusion source insulation film to form the gate. Forming a sidewall insulating film on the side surface of the electrode; and forming a sidewall insulating film on the silicon semiconductor layer from the sidewall insulating film. Performing a second heat treatment for forming the LDD diffusion layer by solid-phase diffusion of the impurity. 2. The step of forming an amorphized layer, wherein X is a group IV element, Y is a VII element, and at least one ion species of XY _n ⁺ type ions _where n = 1, 2, and 3 is ion-implanted. 2. The method for manufacturing a semiconductor device according to claim 1, wherein: 3. The method according to claim 1, wherein the step of forming the gate electrode comprises:
An element isolation step of forming an isolation insulating film for isolating an S-type semiconductor device in an element isolation region; performing the gate electrode formation step before the amorphization layer formation step; 2. The method according to claim 1, wherein the ion implantation is performed on the gate electrode and the isolation insulating film in a self-aligned manner. 4. The step of forming an amorphous layer, wherein X is a group IV element, Y is a VII element, and any one of XY _n ⁺ type ions and X ⁺ type ions with n = 1, 2, and 3 In the impurity distribution by ion implantation, the ion projection range is Rp [nm], the standard deviation is △ Rp [nm], and the junction depth of the LDD diffusion layer is Xj [nm].
The ion implantation is performed with an implantation energy satisfying j> Rp + 4 × △ Rp and an ion implantation dose of 1 × 10 ¹⁴ [cm ⁻² ] or more and 5 × 10 ¹⁵ [cm ⁻² ] or less. The method for manufacturing a semiconductor device according to claim 1. 5. The first heat treatment is performed in a non-oxidizing atmosphere, the temperature is 700 ° C. or more and 1100 ° C. or less, and the time is 1 second or more and 10 hours or less. The method for manufacturing a semiconductor device according to claim 1, wherein 6. The insulating film forming step, wherein the concentration of the impurity is not less than 10 [mol%] and not more than 30 [mol%], and the element of the impurity is any of boron and phosphorus. The method for manufacturing a semiconductor device according to claim 1, wherein: 7. The second heat treatment is performed in a non-oxidizing atmosphere, the temperature is 950 [° C.] to 1050 [° C.], and the time is 1 [sec] to 30 [sec]. The method for manufacturing a semiconductor device according to claim 1, wherein