JPH1140514A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a contact hole with a good taper shape which does not deteriorate step coverage. SOLUTION: After a photoresist film 15 provided with an opening part 14 on an insulation film formed of a lamination film of a TEOS film 12 and a BPSG film 13 on a semiconductor board 11 is formed, the photoresist film 15 is etched isotropically by combining wet treatment and dry treatment to a middle of a film thickness of the insulation film. Then, a remaining film thickness of the insulation film is completely removed by anisotropic etching by using the photoresist film 15 as a mask. Thereby, a contact hole 17 with a good taper 16 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming a contact hole having a tapered upper portion of the contact hole.

[0002]

2. Description of the Related Art In recent years, the aspect ratio of a contact hole tends to increase with the progress of high integration and multilayer wiring of a semiconductor integrated circuit. For this reason, step coverage of the metal wiring film in the contact hole may be deteriorated, and disconnection or the like may be caused. Therefore, tapering is applied to the contact holes to prevent disconnection and the like.

Hereinafter, a conventional method for forming a contact hole will be described with reference to the drawings. In FIG. 7, a TEOS (tetraexisilane) film 2 having a thickness of about 200 nm and a TEOS
A BPSG film 3 having a thickness of 00 nm (the phosphorus concentration is 4.0
The concentration of boron is 5 wt% and the concentration of boron is 4.60 wt%. Is formed, and a photoresist film 5 having an opening 4 on the contact hole formation region is formed by photolithography.

The contact hole diameter is 0.8 μm.
In the following, taking a contact hole having an aspect ratio of 1 or more as an example, if the contact hole is formed only by anisotropic etching, it is difficult to bury a metal wiring film made of aluminum or the like in the hole. Therefore, a method of forming a contact hole, which is a combination of isotropic etching and anisotropic etching described below, is generally performed.

The contact hole diameter is about 0.7
A method for forming a contact hole with a depth of about 0.7 μm and a thickness of about μm will be described. First, using the photoresist film 5 as a mask, a part of the BPSG film 3 is isotropically etched to form a taper in a contact hole described later. Hereinafter, the tapered shape of the contact hole when the isotropic etching is wet-processed in this step will be described.

For example, according to a wet processing method of etching the BPSG film 3 by about 180 nm using a hydrofluoric acid (HF) solution at a liquid temperature of 26 ° C.,
Since the etching rate (in the horizontal direction with respect to the surface of the film 3) is high, a taper 6a is formed below the resist film 5 in a range much larger than the size of the opening 4 as shown in FIG.

Then, the remaining insulating film (remaining BPSG 3 film and TEOS film 2) after the isotropic etching as described above is completely removed by anisotropic etching as shown in FIG. A hole 7a is formed. In this step, an RIE (Reactive Ion Etching) type etching apparatus is used, and an etching gas composed of a CF4 gas at a flow rate of about 60 sccm, a CHF3 gas at a flow rate of about 60 sccm, and an Ar gas at a flow rate of about 900 sccm is used as a vacuum. Plasma etching is performed under the conditions of a temperature of 173.3 Pa and an RF power of 850 W.

Next, a description will be given of a tapered shape when the above-described isotropic etching is dry-processed. In this case, a CDE (Chemical Dry Etching) type etching apparatus is used, and CF4 having a flow rate of about 210 sccm is used.
Using an etching gas consisting of a gas and an O2 gas at a flow rate of about 90 sccm, a degree of vacuum of 80 Pa and an RF power of 7
Under the condition of 00W, the BPSG film 3 is
By plasma etching, a relatively deep taper 6b shape is obtained in which the diameter of the upper portion of the taper is smaller than that of the taper 6a formed by the above-described wet processing as shown in FIG.

The remaining insulating film (the remaining BPSG3 film and T
The EOS film 2) is completely removed by anisotropic etching as shown in FIG. 11 to form a contact hole 7b. Note that the anisotropic etching conditions in this step are the same as the above-described anisotropic etching conditions.

[0010]

The problems in the above-described isotropic etching will be described below. First, the shape of a contact hole formed by combining isotropic etching and anisotropic etching by wet processing under the above-described conditions is such that the taper 6a of the contact hole 7a is in the lateral direction (the surface of the BPSG film 3) as shown in FIG. (In the horizontal direction with respect to the horizontal axis), and has a relatively thin shape.
As a result of measuring the step coverage when the metal wiring film made of aluminum was formed in the contact hole 7a having such a shape, the step coverage at this time was about 4% on the average on both sides (mostly covered on the flat portion). The thickness ts of the wiring film at the place where the film is thickly applied is defined as 100%, and the thickness tb of the wiring film at the place where the film is thinnest in the contact hole is indicated. The film thickness tb of the wiring film / the film thickness ts of the wiring film at the place where the film was thickest. The contact hole diameter at this time was about 0.73 μm. And the diameter of the upper part of the taper was about 3.19 μm. Here, when step coverage is evaluated, generally, an average of about 10% is required on both sides. Therefore, the step coverage is poor in the contact hole 7a formed by the method combining the isotropic etching and the anisotropic etching by the wet processing described above. This is wider at the tapered portion and seems to contribute to step coverage at first glance, but as described above, since etching in the lateral direction is fast, there is a limitation in the lateral direction, and it cannot be formed deeply. Therefore, since the contact hole formed by anisotropic etching becomes deep, the angle formed when a tangent (dashed line) contacting the insulating film above the opening is drawn from the center of the bottom of the contact hole 7a as shown in FIG. θ1 becomes tight and the step coverage deteriorates.

In a place where contact holes are densely provided (for example, when the distance between hole centers is less than about 3.2 μm), the upper portion of the taper 6a is connected, and the photoresist film 5 floats as shown in FIG. This causes pattern shift and the like. Therefore, in the case of wet processing,
Since the etching is restricted in the lateral direction, it cannot be increased in the depth direction, and it is inevitable that the amount of etching by the subsequent anisotropic etching is increased, thereby causing the step coverage to deteriorate.

On the other hand, the contact hole formed by combining isotropic etching and anisotropic etching by dry processing under the above-described conditions has a taper 6b of the contact hole 7b in the lateral direction (BPSG) as shown in FIG.
It spreads little in the horizontal direction with respect to the surface of the film 3 and has a relatively deep shape. As a result of measuring the step coverage when a metal wiring film made of aluminum was formed in the contact hole 7b having such a shape, the step coverage at this time was about 5% on average on both sides. The diameter of the contact hole at this time is about 0.
It was 78 μm. And the diameter of the taper upper part was about 1.19 μm.

Further, even in a place where the contact holes are densely provided (for example, when the distance between the hole centers is less than about 3.2 μm), the upper portion of the taper 6b is not connected as shown in FIG. Photoresist film 5
There is no problem that the pattern floats to cause a pattern shift or the like. Therefore, although the etching amount can be increased,
As described above, the step coverage was hardly improved as compared with the step coverage during the wet processing. This is because the surface of the BPSG film 3 has an overhang shape as shown in FIG. 14B by extending the etching time to obtain the etching depth, and as shown in FIG. This is because the angle θ2 formed when a tangent line (dashed-dotted line) in contact with the insulating film above the opening is drawn due to the influence of the overhang portion, and the step coverage is rather deteriorated. As described above, even in the case of the dry treatment, only the same step coverage as in the case of the above-described wet treatment was obtained.

Accordingly, an object of the present invention is to form a contact hole having a good taper shape without deteriorating step coverage.

[0015]

Accordingly, the present invention provides a method of forming a photoresist film having a predetermined opening on an insulating film composed of a laminated film of a TEOS film and a BPSG film on a semiconductor substrate. As a mask, isotropic etching is performed by combining the wet treatment and the dry treatment up to the middle of the thickness of the insulating film. Subsequently, by completely removing the remaining film thickness of the insulating film by anisotropic etching using the photoresist film as a mask, a contact hole having a good taper is formed, and a metal wiring film to the contact hole is formed. Is to improve the step coverage.

The present invention also relates to a method of manufacturing a semiconductor device, comprising the step of forming a contact hole in a region having a high step, such as a nonvolatile semiconductor memory device in which a floating gate and a control gate are stacked. When forming a contact hole, first, isotropic etching is performed by wet processing and dry processing.
Is performed, followed by a second etching step for performing anisotropic etching.

[0017]

Next, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
In this embodiment, a method for forming a contact hole having a contact hole diameter of about 0.7 μm and a depth of about 0.7 μm will be described.

In FIG. 1, a reduced pressure C is applied on a semiconductor substrate 11.
The TEOS film 1 having a thickness of about 200 nm is formed by the VD method.
An insulating film made of a BPSG film 13 having a thickness of about 2 nm and about 400 nm is formed, and a photoresist film 15 having an opening 14 on a contact hole forming region is formed by photolithography. Then, oven baking is performed on the semiconductor substrate 11 at about 150 ° C. for 30 minutes. Further, an O2 plasma treatment is performed to remove the scum of the photoresist film 14.

Next, in FIG. 2, the photoresist film 15 is used as a mask to isotropically etch a part of the BPSG film 13. In this step, for example, a wet process of etching the BPSG film 3 by about 60 nm using a hydrofluoric acid (HF) solution at a liquid temperature of 26 ° C. is performed. Then, oven baking is performed at about 120 ° C. for 30 minutes.
Subsequently, using a CDE type etching apparatus, CF4 gas at a flow rate of about 210 sccm and about 90 sccc are used.
Using an etching gas consisting of O2 gas at a flow rate of m
Under the conditions of a vacuum degree of 80 Pa and RF power of 700 W, the above B
A dry process for plasma etching the PSG film 3 by about 200 nm is performed. The total etching amount is 260
nm, and a taper 16 of a contact hole 17 described later is formed.

This step is a characteristic step of the present invention. The isotropic etching for forming the taper 16 in the contact hole 17 is performed by a combination of the wet processing and the dry processing. 6
a (see FIG. 7), hole diameter is smaller and deep taper 1
6 and a taper 6b formed by a conventional dry process.
A taper 16 having a larger hole diameter than that of the BPSG film 13 (see FIG. 9) and having no overhanging surface is obtained. That is, first, since the BPSG film 13 is etched to the inner side below the opening 14 of the photoresist film 15 by wet processing (see the dotted line in FIG. 2), obliquely incident ions cause the photoresist film 15 Since it penetrates into the lower surface, it is possible to form a favorable contact hole having a width in the lateral direction as compared with the conventional dry processing only (see the dashed line in FIG. 2).

According to the method described above, the insulating film remaining after the isotropic etching (the remaining BPSG 13 film and TEOS film 12) is completely removed by anisotropic etching as shown in FIG. 17 are formed. In this step, using a RIE etching apparatus, CF4 gas at a flow rate of about 60 sccm, about 60 sccm
Plasma etching is performed under the conditions of a vacuum degree of 173.3 Pa and RF power of 850 W using an etching gas composed of CHF3 gas at a flow rate of cm and Ar gas at a flow rate of about 900 sccm.

The step coverage when the metal wiring film made of aluminum was formed in the contact hole 17 thus formed was measured. As a result, the step coverage at this time was as shown in FIG. The average was about 15% on both sides, reflecting the angle θ3 (an angle smaller than the conventional θ1 and θ2) formed when a tangent line (dashed line) in contact with the insulating film above the opening was drawn from the center of the bottom. . At this time, the diameter of the contact hole is about 0.73 μm. And the taper 16
The upper diameter was approximately 1.79 μm.

Further, even in a place where the contact holes are densely present (for example, when the distance between the hole centers is 3.0 μm), as shown in FIG.
The conventional problem that the photoresist film 5 floats and causes a pattern shift or the like does not occur. Therefore, in the present invention, a good taper shape was obtained, the step coverage was improved, and the result that the resist film did not float and the problem of pattern shift did not occur was obtained.

Further, the contact hole diameter is about 0.4
Even in the case of forming a contact hole having a depth of about 0.7 μm with a thickness of about μm, by employing the present invention, an average step coverage of 12% was obtained on both sides. FIG. 6 is a cross-sectional view for explaining an embodiment in which the present invention is applied to a nonvolatile semiconductor memory device having a floating gate.

In FIG. 6, a source region 22 and a drain region 23 are formed on a surface layer of a P-type silicon substrate 21 so as to be separated from each other. On the substrate 21 on both sides of the source region 22, a floating gate 25 made of a conductive polysilicon film having a thickness of about 100 nm to 200 nm is formed via an insulating film 24 having a thickness of about 10 nm to 20 nm. ing. On the substrate 21 between the source region 22 and the drain region 23, a polysilicon film having a thickness of about 100 to 200 nm and a polysilicon film having a thickness of about 100 to 200 nm are interposed via an insulating film 26 having a thickness of about 30 to 40 nm. A control gate 27 made of a tungsten silicide (WSix) film having a thickness is formed. The control gate 2
7 is disposed above the floating gate 25 with the insulating film 26 interposed therebetween.

The source region 22 and the control gate 27 both extend in one direction (perpendicular to the plane of the drawing), and a plurality of drain regions 23 and a plurality of control gates 27 are provided on both sides of the source region 22. They are arranged along the one direction. Then, the control gate 27 functions as a word line of the nonvolatile semiconductor memory device.

On the silicon substrate 21, an interlayer insulating film 28 made of a TEOS film having a thickness of about 200 nm and a BPSG film having a thickness of about 400 nm is formed so as to cover the floating gate 25 and the control gate 27. Then, the drain region 23 is contacted through a contact hole 29 formed in the interlayer insulating film 28 to form a wiring film serving as a bit line of the nonvolatile semiconductor memory device.

Here, the contact hole 29 in which the above-described wiring film is formed is formed in a high step portion of the nonvolatile semiconductor memory device in which the floating gate 25 and the control gate 27 are stacked as shown in FIG. For,
It is inevitable that the contact hole 29 becomes deeper.
When a wiring film made of aluminum etc. is formed in
The step coverage will be worse. Therefore, in the step of forming the contact hole 29, as described in the embodiment, the contact hole 2 is formed.
The step coverage of the wiring film 31 can be improved by obtaining a good taper shape by performing a wet process and a dry process in the isotropic etching process for forming the 9 taper 30.

In this embodiment, an example is shown in which the present invention is applied to a so-called split gate type nonvolatile semiconductor memory device in which a control gate 27 is laminated on a part of a floating gate 25 with an insulating film 26 interposed therebetween. But
The present invention may be applied to a so-called stacked gate type nonvolatile memory device in which a control gate is stacked on the entire surface of a floating gate.

Further, in the present invention, in the isotropic etching step for forming the taper of the contact hole, the wet processing is first performed and then the dry processing is performed. However, the present invention is not limited to this. By doing so, the object of the present invention can be achieved. Further, in the present invention, the TEOS film and the B
Although a two-layer film made of a PSG film is used, the present invention can be applied to a single-layer film or a multilayer film having three or more layers.

The present invention is applicable not only to contact holes but also to a case where wiring such as via holes is connected.

[0032]

According to the present invention, isotropic etching for forming a taper in a contact hole is performed by combining wet processing and dry processing, so that conventional wet processing or dry processing, and isotropic etching using a single substance are performed. And a better taper than that obtained by the above. In particular, even in a place where contact holes are densely formed, the upper portion of the taper is not connected, and there is no problem that the photoresist film floats to cause a pattern shift or the like as in the related art. Therefore, according to the present invention, a good taper shape can be obtained, so that step coverage can be improved.

If the present invention is applied to a device having a contact hole formed in a region having a high step portion, such as a nonvolatile semiconductor memory device having a floating gate and a control gate stacked, a favorable tapered shape can be obtained. Since the contact hole having the contact hole can be formed, the step coverage of the wiring film is improved.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a second sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view illustrating a shape of a contact hole formed by the method for manufacturing a semiconductor device according to the embodiment of the present invention;

FIG. 5 is a sectional view showing a shape of a contact hole formed by the method for manufacturing a semiconductor device according to the embodiment of the present invention;

FIG. 6 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention;

FIG. 7 is a first cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 8 is a second cross-sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 9 is a third cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 10 is a first diagram showing another conventional method for manufacturing a semiconductor device.
FIG.

FIG. 11 is a second view showing another conventional method for manufacturing a semiconductor device.
FIG.

FIG. 12 is a cross-sectional view illustrating a shape of a contact hole formed by a conventional method for manufacturing a semiconductor device.

FIG. 13 is a cross-sectional view for describing a problem of a conventional method of manufacturing a semiconductor device.

FIG. 14 is a cross-sectional view for describing a problem of another conventional method for manufacturing a semiconductor device.

FIG. 15 is a cross-sectional view showing a shape of a contact hole formed by another conventional method for manufacturing a semiconductor device.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8247 H01L 29/78 371 29/29/788 29/792

Claims (3)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: forming a contact hole on an insulating film on a semiconductor substrate; forming a photoresist film having a predetermined opening on the insulating film; Using a film as a mask to perform isotropic etching by wet processing and dry processing halfway through the thickness of the insulating film, and completely removing the remaining film thickness of the insulating film by anisotropic etching using the photoresist film as a mask And a method of manufacturing a semiconductor device. 2. The method according to claim 1, wherein the insulating film includes a TEOS film and a BPSG film.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a stacked film composed of a film. 3. A method of manufacturing a semiconductor device, comprising: forming a contact hole in a region having a high step portion, such as a nonvolatile semiconductor memory device in which a floating gate and a control gate are stacked. A method for manufacturing a semiconductor device, characterized in that the forming step comprises a first etching step of performing isotropic etching by wet processing and a dry processing and a second etching step of performing anisotropic etching.