JPH11355285A - Exchange - Google Patents

Abstract

PROBLEM TO BE SOLVED: To exchange a cell with a same system clock signal as before in an equal manner to a conventional manner even in the case that the size of the cell exceeds a previously determined fixed length by converting a header. SOLUTION: This exchange is provided with a header conversion part 130, a switch part 140, a first signal line 173 which transfers a cell in which a header is converted, from the header conversion part to the switch part and further, a second signal line 176 which transfers a part of information transferred from the head conversion part to the switch part instead of the first signal line. The header conversion part outputs the partial information to be had by the cell where the header conversion is finished to the second signal line and outputs the other information than the partial information to the first signal line. The switch part uses the information sent through the first and the second signal lines to perform the exchange.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exchange for routing fixed-length cells, for example, an ATM (Asynchonous).
Transfer Mode) This relates to an exchange.

[0002]

2. Description of the Related Art A conventional exchange of this type is disclosed in, for example, Reference 1 ("Point Graphical Standard ATM Textbook", February 1996).
1st edition, 4th printing issued on March 1, ASCII Corporation). FIG. 7 is a functional block diagram of the conventional exchange 10.

The exchange 10 has an incoming LI (line interface) section 11, a UPC (flow rate monitoring section) 13, an HC
V (header conversion unit) 15, ATM switch unit 17, PL
An L (Phase Locked Loop) 19, an FCV (Format Conversion Unit) 21 and an output LI unit 23 are provided.

In FIG. 7, reference numeral 31 denotes an incoming transmission line,
32 is an outgoing transmission line, 33 to 37 are signal lines in the exchange, 38 to 42a are system clock signal lines, and 43 is a reference clock signal line.

The incoming LI section 11 has a function of terminating the incoming transmission line 31. Generally, signal transmission outside the exchange is performed by an optical signal, and signal transmission inside the exchange is an electric signal and is performed by a plurality of signal lines (parallel signal lines). Therefore, the input side LI unit 11 also has a photoelectric conversion function and a serial-parallel conversion function.

[0006] The flow rate monitor 13 monitors the flow rate of ATM cells input to the exchange 10.

The header conversion unit 15 will be described in detail later.
The header information in the ATM cell is converted.

As will be described in detail later, the ATM switch unit 17 has a function of switching ATM cells and a function of preferentially outputting ATM cells with high priority.

The PLL 19 generates a clock signal (system clock signal) used in the exchange 10 from a reference clock signal input from the outside via a signal line 43. The generated system clock signal is transmitted to each part 11, 13, 15,.
17, 21, and 23.

Note that at present, the incoming and outgoing transmission lines 31,
In each of the 32, serial transmission using a clock signal having a frequency of 155.52 MHz is performed. On the other hand, the signal lines 33 to 37 in the exchange have a frequency of 19.44 MHz.
The parallel transmission using the system clock signal is performed. Each of the signal lines 33 to 37 in the exchange is composed of, for example, nine parallel signal lines.

The FCV 21 deletes output terminal number information (referred to as routing bits in Document 1) and quality class information from the ATM cells that have been routed by the ATM switch unit 17.

The output terminal number information is information for routing an ATM cell to a terminal to which an ATM cell is desired to be output, among a large number of output terminals of the ATM switch unit 17. In addition, the quality class information is information indicating which cell is to be preferentially transmitted to a subsequent stage when a plurality of cells are simultaneously input (congested) to the same switch.

The egress LI unit 23 has a function of terminating the egress transmission line 32, an electrical / optical conversion function, and a parallel-serial conversion function.

Next, the header conversion unit 15 will be described in detail. FIG. 8 is a functional block diagram of the header conversion unit 15. The header conversion unit 15 includes a header reference unit 15a, a table unit 15b, a header writing unit 15c, ATM cell signal lines 15d to 15f, and control signal lines 15g and 15h.

The header reference section 15a has a function of referring to a VPI (virtual path identifier) and a VCI (virtual channel identifier) of an input ATM cell.

The table section 15b has a function of a correspondence table between the input VPI and the input VCI, the output VPI, the output VCI, the output terminal number information and the quality class information, and a function of retrieving the output VPI and the like from the input VPI and the like. Have.

The header writing unit 15c writes the output VPI, output VCI, output terminal number and quality class in the ATM cell.

Specifically, the header conversion is performed as follows. When an input ATM cell arrives at the header reference unit 15a, the header reference unit 15a sets the input V
The PI and the input VCI are transferred to the table unit 15b.
The table unit 15b searches for information on the output VPI, the output VCI, the output terminal number, and the quality class using the transferred information, and stores them in the header writing unit 15c.
Transfer to The header writing unit 15c writes the transferred information into an output ATM cell.

Next, the ATM switch section 17 will be described in detail. There are various configurations of the ATM switch unit 17. FIG. 9 shows an example of such a configuration, and is a configuration diagram of the ATM switch unit disclosed in the above-mentioned document 1. In this example, 2
Input 2 output switch 51 (hereinafter unit switch 51)
Are connected in multiple stages. Each unit switch 51
The information 55 (routing bit) indicating the output terminal number written in the cell 53 input to the switch is 1 or 0
The route is switched depending on the route. In the example of FIG.
Since the switch unit 17 has a three-stage configuration, the information indicating the output terminal number is composed of three bits. The unit switch at the n-th stage of the ATM switch unit 17 is connected to one of the output terminals of the unit switch in accordance with whether the information of the n-th bit in the information indicating the output terminal number of the ATM cell is 1 or 0,
The ATM cell is output.

As a control method when congestion occurs, a method of giving priority to an ATM cell input from a higher-order terminal (pre-ordered) of the ATM switch unit 17 or a method of high quality class. There is a method of preferentially outputting an ATM cell.

As is well known in ATM exchanges,
The ATM cell has a fixed length. FIG.
FIG. 3 is a diagram illustrating an example of a format of a cell (input ATM cell) input to a TM exchange; In the case of this example, the size of the cell is 9 × 54 bits. Further, the 0th to 5th rows of this cell are used as a header, and the rest of the cell is used as an ATM cell payload (information field). In FIGS. 10A and 10B, an area a is an area where a cell head display is written, and an area b is an area where a cell presence / absence flag is written.

The header converting section 15 converts the information of the header of the input ATM cell as described above. FIG.
(B) is a diagram showing an example of a cell format after header conversion. In the case of this example, the quality-class information and the output terminal number information are written in the cells after the header conversion, as shown in FIG.

9-bit data indicated by numbers 0 to 8 in FIG. 10B is transferred in parallel to the ATM switch unit 17 via the signal line 35 inside the exchange.

However, in the ATM exchange, when the header conversion unit 15 converts the information, the cell size may be larger than the fixed length in some cases. For example, when the number of bits of the output terminal number information increases because the number of terminals of the ATM switch unit increases, or when the number of bits of the quality class information increases because the number of quality classes handled increases, etc. Since the information to be written in the header conversion unit increases, the size of the cell becomes larger than the above fixed length (an example is shown in FIG. 4 later).

When the size of the ATM cell is larger than the fixed length, the processing subsequent to the header conversion unit is performed in the same manner as when the size of the ATM cell is fixed (that is, when the frequency of the system clock is 19). .44 MHz), the throughput in the exchange decreases.

Conventionally, in order to prevent this, FIG.
1 has been dealt with by the exchange 60 configured as described with reference to FIG.

That is, the exchange 1 described with reference to FIG.
0: the configuration of the header conversion unit 61, the point that the second PLL 63 is provided, a part of the header conversion unit 61 (details will be described later), and the ATM switch unit 17
The difference is that the switch 60 operates mainly by the system clock signal supplied from the PLL, and that the buffer unit 65 is provided between the FCV 21 and the output side LI unit 23. In FIG. 11,
37a is a signal line in the exchange, and 44 to 47 are second PLL6s.
3 is a clock signal line that is output.

First, the header conversion unit 61 will be described. FIG. 12 is a functional block diagram of the header conversion unit 61.

The header conversion unit 61 includes a header reference unit 6
1a, table section 61b, header writing section 61c, ATM
Cell signal lines 61d to 61g, control signal lines 61h and 61
i, the data line 61j, and the first and second PLLs 1
Clock signal lines 61k and 61l for supplying a system clock signal from 9 and 63.

The difference between the header conversion unit 61 and the header conversion unit 15 described with reference to FIG.
1c. In other words, the data writing unit 61c stores a first-in first-out memory
Cell FIFO memory) 61 ca and header information memory 6
1cb and a selector section 61cc.

The header conversion section 61 operates as follows. A system clock signal (hereinafter, referred to as a first system clock signal) 61k generated by the first PLL 19 (FIG. 1)
2), the header reference unit 61a sends the FIFO memory 6
At the same time, the ATM cell is written in 1ca, and information on the output VPI, output VCI, output terminal number, and quality class is written from the table section 61b to the header information memory 61cb.

The information written in the cell FIFO memory 61ca and the information written in the header information memory 61cb, respectively, are read out by a system clock signal (hereinafter, a second system clock signal) 611 (FIG. 12) generated by the second PLL 63. , To the selector section 61cc. When the cell size becomes, for example, 9 × 64 bits by the header conversion, the frequency of the second clock signal becomes 1
9.44 × 64/54 = 23.04 MHz.

The selector unit 61cc rewrites the header of the ATM cell based on the transmitted information. The ATM cell whose header has been rewritten is transferred to the ATM switch unit 17 by the second system clock signal.

The ATM switch unit 17 switches the transferred ATM cells according to a second system clock signal. The ATM cells routed and output by the ATM switch 17 are input to the FCV 21, where output terminal number information and quality class information are deleted, and then input to the buffer 65.

The buffer section 65 is composed of a first-in first-out memory (hereinafter, buffer FIFO memory). The ATM switch unit 17 writes information into the buffer unit 65 using the second system clock signal. The buffer unit 65 transmits the written information to the output side LI unit 23 using a first system clock signal.

Thus, according to the above exchange 60,
Processing by the second system clock signal was performed between the header conversion unit 61 and the buffer unit 65.

[0037]

However, FIG.
And the conventional exchange 60 described with reference to FIG.
Two types of PLLs 19 and 63 are required. PLLs are generally expensive. Therefore, the cost of the exchange is increased. Further, in this conventional exchange, the transfer of ATM cells is performed by a first system clock signal in a certain section,
Since the second system clock signal is used in another certain section, a plurality of FIFO memories 61ca, 61cb, and 65 are required to match the two sections. This also increases the cost of the exchange.

Therefore, there is a demand for an exchange which can use one PLL to realize the routing of cells in the exchange without lowering the throughput than before.

[0039]

According to the present invention, there is provided an exchange for routing a cell including a header, a header conversion unit for converting a header of an input cell, and a switch unit. A switch unit that has a plurality of output terminals and routes the header-converted cell to any one of the output terminals based on the header, and a transfer unit that transfers the header-converted cell from the header conversion unit to the switch unit. And a second signal line for transferring a part of the information transferred from the header conversion unit to the switch unit instead of the first signal line, in the exchange provided with the header conversion unit and the switch. Between the department. Then, the header conversion unit outputs, to the second signal line, a part of the information of the cell after the header conversion, and outputs information other than the part of the information to the first signal line. And the switch unit is the first unit.
And a switch unit that performs the routing by using information transmitted via the signal line and the second signal line.

According to this exchange, the second signal line is newly provided between the header conversion unit and the switch unit, so that the amount of information that can be transferred in parallel from the header conversion unit to the switch unit increases. Therefore, even if the size of the cell exceeds a predetermined fixed length due to the header conversion in the header conversion unit and the amount of information to be transferred to the switch unit increases, the information of the cell remains in these first and second signals. Can be transferred by line. That is, even if the information amount of the cell is increased by the header conversion, the cell can be transferred while the frequency of the system clock signal remains the same as before.

According to this exchange, the header conversion unit and the switching unit are each adapted to the processing using the first and second signal lines as described above. Cell transfer to the switch unit and cell routing in the switch unit can be realized with the same throughput as in the past.

Note that the number of the second signal lines is an arbitrary number according to the amount of information to be transferred by the second signal lines. However, the capacity of the second signal line may be such that the cell size exceeding the predetermined fixed length can be transferred in parallel instead of the first signal line during header conversion. . Therefore, the number of second signal lines is relatively small, and one or several second signal lines are sufficient.

In practicing the present invention, the second
It is preferable that the information transferred by using the signal line of (1) is information (output terminal number information) for specifying a terminal to output a cell among a large number of output terminals of the switch unit. This is because, if the information transferred on the second signal line is output terminal number information, the switch unit can use the information sent on the second signal line as it is as a switching signal.
If information other than the output terminal number information is included in the information to be transferred on the second signal line, it is necessary to perform signal processing such as signal selection in the switch section, but this preferred example can avoid this. Benefits are obtained.

In practicing the present invention, it is preferable that the header conversion section has a configuration including a header reference section, a table section, a header writing section, and an information extraction section.

However, the header reference section refers to the header of a cell (input cell) input to the header conversion section. The table section holds information for header conversion, and, based on the held information, information for rewriting a header of the input cell based on information obtained by the header reference section referring to the input cell. Search and output. The header writing unit rewrites a header of the input cell based on the rewriting information output by the table unit and outputs the input cell as an output cell to the first signal line.
The information extracting unit extracts information to be output to the second signal line from information held in the table unit and outputs the information to the second signal line.

According to such a header conversion unit, it is possible to easily select information to be output to the first signal line and the second signal line.

Note that the information extracting unit extracts information from the table unit and outputs the information to the second signal line as:
It is preferable that the output terminal number information is extracted.
In this case, as described above, the switch unit can perform the switching operation using the information transferred from the second signal line as it is.

In practicing the present invention, the switch section is constituted by connecting unit switches in multiple stages, and the header conversion section is connected to each input of the first stage unit switch by the first and second signal lines. It is preferable that the switch units are connected to each other through a switch. Of course, each of the unit switches delays the information transferred by the first signal line from the information transferred by the second signal line, and transfers the information by the second signal line. The route is switched according to the information
It is preferable that the switch unit is a unit switch including a selector for transferring information transferred by each of the first signal line and the second signal line in parallel.

According to the switch section of this preferred embodiment, when, for example, output terminal number information is transferred by the second signal line, the following operation can be obtained.

That is, among the information of the cells subjected to the header conversion, the output terminal number information is transferred to the switch section via the second signal line, and the other information (hereinafter, also referred to as information other than the output terminal number). ) Is transferred to the switch section by the first signal line. However, since the unit switch of the switch unit includes a delay unit, the unit switch first receives output terminal number information. Therefore, the selector of the unit switch forms a path according to the output terminal number information. Information other than the output terminal number is input to the selector in such a state with a delay of the delay amount of the delay unit. The information other than the output terminal number and the output terminal number information pass through the unit switch in parallel. Hereinafter, the information other than the output terminal number and the output terminal number information similarly pass through the unit switch of each stage.

In the switch section of this preferred embodiment, the transfer of information is delayed by the delay caused by the delay means. However, the delay time required by the delay means is short, since it is only necessary to secure a time for forming a path state corresponding to the output terminal number information in the selector. Therefore, the throughput of information transfer can be made equal to that of the related art, and using a system clock signal from one PLL.

[0052]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an exchange according to the present invention. However, the drawings used in the description are only schematically shown to the extent that the present invention can be understood. Further, in each of the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted.

FIG. 1 shows an exchange 10 according to an embodiment of the present invention.
FIG. 4 is a functional block diagram for explaining No. 0; This exchange 100
Are the entrance LI unit 110, the UPC (flow rate monitoring unit) 120,
HCV (header conversion unit) 130, ATM switch unit 14
0, a PLL (Phase Locked Loop) 150, an FCV (Format Conversion Unit) 160, and an output LI unit 170.

Further, the exchange 100 has internal signal lines 171 to 177 and system clock signal lines 181 to 181.
186 and a reference clock signal line 187. In FIG. 1, reference numeral 191 denotes an incoming transmission line, and 192 denotes an outgoing transmission line.

As many systems as the input LI unit 110, the flow rate monitoring unit 120, and the header conversion unit 130 are provided in the same number as the input terminals of the ATM switch unit 140, and are connected to these input terminals. The same number of systems as the number of output terminals of the ATM switch unit 140 are prepared, and the system including the FCV 160 and the output side LI unit 170 is connected to these output terminals.

Next, each component of the exchange 100 will be described in order.

First, the signal line 173 of the in-device signal lines 171 to 177 corresponds to the first signal line according to the present invention, and the signal line 176 corresponds to the second signal line according to the present invention.

The signal lines 171 to 175 of the in-device signal lines 171 to 177 correspond to the conventional in-device signal lines 3.
Configurations similar to 3-37 can be made. For example, 9
A parallel signal line having the signal lines in parallel can be used.

Each of the signal lines 176 and 177 among the signal lines 171 to 177 in the apparatus is one or several (one in this embodiment) signal lines. Then, the signal line 176 (that is, the second signal line 176)
Are provided between the header conversion unit 130 and the switch unit 140 in a parallel relationship with the first signal line 173.

The system clock signal lines 181 to 1
86 correspond to the conventional system clock signal lines 38 to
A configuration similar to that of 42a can be adopted.

The incoming LI section 11 of the exchange 100
0 can have the same configuration as that of the conventional entrance LI unit 11. That is, it can have a function of terminating the input-side transmission line 191, a photoelectric conversion function, and a serial-parallel conversion function. Further, the incoming transmission line 191 can have the same configuration as the conventional incoming transmission line 31.

The flow monitoring unit 120 is provided with the exchange 100
Monitor the flow rate of the ATM cells input to. The flow monitoring unit 120 can have the same configuration as the conventional flow monitoring unit 13.

The header conversion unit 130 outputs a part of the cell information transferred from the header conversion unit 130 to the ATM switch unit 140 to the second signal line 176 in addition to the function of the conventional header conversion unit 15. Then, it has a function of outputting the remaining information to the first signal line 173.

FIG. 2 is a functional block diagram showing an example of the configuration of the header conversion unit 130. This header conversion unit 13
0 includes a header reference section 130a, a table section 130b, and a header writing section 130c. Further, the header conversion unit 130 includes an information extraction unit 130d as a characteristic part according to the present invention.

Header reference section 130a, table section 130
b and the header writing unit 130c can have the same configuration as the conventional header reference unit 15a, table unit 15b, and header writing unit 15c.

The information extraction unit 130d
b, a predetermined part is extracted from the information to be written in the header stored in the header b, and this is extracted to the second signal line 17.
6 is output.

The information extracting unit 130d is connected to the table unit 130b
The information to be extracted from is arbitrary, but is preferably output terminal number information (routing bits) required for routing in the ATM switch unit 140. The table section 130b has a format as shown in FIG. 3, for example. Conventionally, based on an input VPI or an input VCI included in an input ATM cell, the table unit 130b
The output VPI, output VCI, quality class, and output terminal number are extracted and output to the header writing unit 130c. However, in the present invention, the table unit 130b extracts the output VPI, the output VCI, and the quality class from the table and outputs them to the header writing unit 130c, but the output terminal number information written in the table is Not output to the input unit 130c. The output terminal number information in the table is extracted by the information extraction unit 130d and output to the second signal line 176.

FIG. 4 shows that the header conversion unit 130 supplies the first and second signal lines 173 and 176 to the switch unit 140.
FIG. 5 is a diagram showing an example of information transferred by the STA.

In the case of the example shown in FIG.
It is the size of a bit. In the case described with reference to FIG. 10, since the size is 9 × 54 bits, in the case of the example of FIG. 4, the size of the cell exceeds a predetermined fixed length.

In the example of FIG. 4, the quality class information is represented by 8 bits, the VPI, VCI, PT and CLP are represented by a total of 24 bits, and the output terminal number information is represented by 54 bits.

In the example shown in FIG. 4, one bit numbered A is used as a bit indicating output terminal number information, and this output terminal number information is stored in the second signal line 17.
6 allows the header conversion unit 130 to switch unit 140
Transfer to Further, 9-bit information (hereinafter, information other than output terminal number information) numbered from 0 to 8 is transferred from the header conversion unit 130 to the switch unit 140 via the first signal line 173.

The information transferred by the first signal line 173 and the information transferred by the second signal line 176 are transmitted in parallel to the ATM switch 140 by the system clock signal from the PLL 150. Forward. In addition, out of the 9 bits numbered from 0 to 8, 8
Are information indicating the cell head display.

Next, the ATM switch section 140 will be described. This ATM switch section 140 is a conventional ATM switch section.
In addition to the function of the switch section 17, it has a new function according to the present invention described below.

FIG. 5 is a functional block diagram focusing on an arbitrary one of the unit switches 141 in the first stage of the ATM switch unit 140. Of course,
In the example of FIG. 5, an example is shown in which the unit switch 141 is configured by a two-input two-output switch. If the unit switches 141 are arranged in multiple stages as shown in FIG. 9 instead of, for example, the unit switches 51 shown in FIG. 9, the switch unit 141 is realized.

However, each unit switch 141 has two delay means 141a and 141b and two selectors 141
c and 141d. Regarding the respective functions of the delay means and the selector, the delay means 14
1a and the selector 141c.

The delay means 141 a
(Hereinafter, also referred to as main information) transferred from the first signal line 173 to the second signal line 176.
Delay from the information transferred by Specifically, information (output terminal number information in this example) transferred by the second signal line 176 is transmitted to the selector 141.
c, 141d, and these selectors 141c, 141c
The signal transferred via the first signal line 173 is delayed until the signal 41d is controlled to a state corresponding to the output terminal number information. The delay means 141a can be constituted by any suitable means, for example, by a memory.

Each of the selectors 141c and 141d
The selector switches the path according to the output terminal number information transferred via the second signal line 176.
Of course, after such path switching is completed, the information transferred via the first signal line 173 and delayed by the delay means and the information transferred via the second signal line 176 are
A selector that outputs in parallel to the switched path. Such selectors 141c and 141d are configured by, for example, an electronic circuit, and can be configured by a suitable circuit having a plurality of signal lines.

Further, the PLL 150 generates a system clock signal used in the exchange from the external reference clock signal. For example, a system clock signal of 19.44 MHz is output as in the conventional case.

The FCV 160 has a function of deleting output terminal number information and quality class information from the cells routed by the ATM switch unit 140.

The configuration of the FCV 160 can be optional.
FIG. 6 is a functional block diagram showing one example.

In the example shown in FIG. 6, the FCV 160
Is composed of a first deleting unit 160a and a second deleting unit 160b. Further, two signal lines 174 and 177 are connected between the FCV 160 and the ATM switch unit 140.
Connected by

After the information transferred by the first signal line 173 and the information transferred by the second signal line 176 are routed in parallel by the ATM switch unit 140 as described above, the former information is The information is input to the FCV 160 via a signal line 174, and the latter information is input to the FCV 160 via a signal line 177.

The information input to the FCV 160 via the signal line 174 is processed by the first deletion unit 160a, and the information input to the FCV 160 via the signal line 177 is processed by the second deletion unit 160b.

Specifically, in this example, the second deletion unit 1
Output terminal number information is input to 60b. And
The second deletion unit 160b deletes this output terminal number information. Further, information other than the output terminal number information (the information of the bits numbered 0 to 8 described with reference to FIG. 4) of the cell information is input to the first deletion unit 160a. Then, the first deletion unit 160a deletes the cell presence / absence flag information and the quality class information from this information.

The output side LI section 170 is a conventional output side L.
A configuration similar to that of the I unit 23 can be adopted. That is,
The output side transmission line 192 may have a terminal function, an electric-optical conversion function, and a parallel-serial conversion function. Further, the outgoing transmission line 192 can have the same configuration as the conventional outgoing transmission line 32.

In this exchange 100, cells can be exchanged as follows.

The cell input from the incoming transmission line 191 is
After being processed in the same manner as in the related art by the entry-side LI unit 110 and the UPC 120, it is input to the header conversion unit 130.

The header conversion unit 130 includes a switch unit 140
Of the information to be transferred to the ATM switch unit by the second signal line 176 and the information other than the output terminal number information by the first signal line 173 using the same system clock signal. Transfer to 140.

The ATM switch unit 140 routes the information transferred from the header conversion unit 130 via the first and second signal lines 173 and 176 as already described with reference to FIG. The routed information is input to the FCV 160.

F where information is input from the ATM switch unit
As described with reference to FIG. 6, the CV 160 deletes unnecessary information from the input information and outputs the remaining information to the output LI unit 1.
70.

The output side LI section 170 converts the input information into electrical-optical conversion and parallel-serial conversion, and then outputs the information to the output side transmission line 192.

As is clear from the above description, even when the cell size exceeds a predetermined fixed length, according to the exchange 100 of the present invention, the incoming LI unit 110, the UPC1
20, a header conversion unit 130, an ATM switch unit 140,
The FCV 160 and the outgoing LI unit 170 each have a PL
It can operate with a system clock signal output from L150 (for example, a system clock signal with a frequency of 19.44 MHz).

In the above, the embodiments of the exchange of the present invention have been described. However, the present invention is not limited to the above-described embodiment, and many modifications or changes can be made.

In the embodiment, an example has been described in which information transmitted on the second signal line is output terminal number information, and information transmitted on the first signal line is information other than output terminal number information. However, how the information is shared and transmitted by the first and second signal lines can be arbitrarily changed. Accordingly, each configuration of the header conversion unit and the switch unit is also changed. For example, the information sent on the second signal line may be, for example, quality class information.

In the above description, the header conversion unit 13
The example shown in FIG. 4 has been described as an example of the format of information sent from 0 to the switch unit 140. However, the format is not limited to the example of FIG. For example, the number of bits corresponding to the width in FIG. 4 may be extended to 11 or more. In that case, the number of second signal lines is increased accordingly.

Further, the configurations of the header conversion unit 130 and the ATM switch unit 140 are not limited to the above-described example, but can be arbitrarily and suitably changed.

In the above-described embodiment, an example in which the present invention is applied to an ATM exchange has been described. However, the present invention can be applied to an exchange for exchanging fixed-length cells including a header. For example, the present invention can be applied to a packet switch.

[0098]

As is clear from the above description, according to the exchange of the present invention, the header-converted cell is added to the first signal line for transferring the header-converted cell to the switch unit.
A second signal line for transferring a part of information transferred from the header conversion unit to the switch unit instead of the first signal line is provided between the header conversion unit and the switch unit. Of course, as a header conversion unit, a header conversion unit that outputs a part of the information of the cell after the header conversion to the second signal line and outputs information other than the part of the information to the first signal line. And a switch unit for routing cells using information transmitted via the first signal line and the second signal line.

Therefore, the size of the cell (specifically, the header length) becomes larger (longer) than the cell size (header length) specified by the exchange method by writing in the header conversion unit. Also, this large (long) information is
Can be transferred on the signal line. Therefore, only one type of frequency of the system clock signal in the exchange is required. Therefore, PL
Since only one type of L is required, an economical exchange is realized.

The header conversion section sends a part of the header conversion information via the second signal line. Therefore, the required number of the second signal lines is minimized, and the increase in the wiring cost is slight.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an exchange according to an embodiment.

FIG. 2 is a diagram illustrating a header conversion unit according to the embodiment.

FIG. 3 is a diagram illustrating a configuration example of a table unit.

FIG. 4 is an explanatory diagram of the embodiment and is a diagram for describing an example of information transfer from a header conversion unit to a switch unit;

FIG. 5 is a diagram showing an example of a switch unit for a part thereof;

FIG. 6 is a diagram illustrating a configuration example of an FCV (format conversion unit).

FIG. 7 is an explanatory diagram of a conventional technique and a problem, and is a diagram illustrating an example of a conventional exchange.

FIG. 8 is an explanatory diagram of a conventional technique and a problem, and is a diagram illustrating an example of a conventional header conversion unit.

FIG. 9 is an explanatory diagram of a conventional technique and a problem, and is a diagram illustrating a conventional switch unit.

FIG. 10 is an explanatory diagram of a conventional technique and a problem, and is an explanatory diagram of a format example of a cell.

FIG. 11 is an explanatory diagram of a conventional technique and a problem, and is a diagram illustrating another example of a conventional exchange.

FIG. 12 is an explanatory diagram of a conventional technique and a problem, and is a diagram illustrating another example of a conventional header conversion unit.

[Explanation of symbols]

 100: Exchange of the embodiment 110: Incoming LI (Incoming Line Interface) Unit 120: UPC (Flow Monitoring Unit) 130: HCV (Header Conversion Unit) 140: Switch Unit (ATM Switch Unit) 150: PLL (Phase Locked) Loop) 160: FCV (format conversion unit) 170: outgoing LI (outgoing line interface) unit 171 to 177: signal line in exchange 173: first signal line 176: second signal line 181 to 186: system clock Signal line 187: reference clock signal line 130a: header reference unit 130b: table unit 130c: header writing unit 130d: information extraction unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hidehiko Mihori 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Yoshinori Aoshima 3-19, Nishi-Shinjuku, Shinjuku-ku, Tokyo No. 2 Nippon Telegraph and Telephone Corporation

Claims (5)

[Claims] 1. An exchange for routing a cell including a header, comprising: a header conversion section for converting a header of an input cell; and a switch section having a plurality of output terminals and converting the header-converted cell to the header. A switch unit for routing to any one output terminal based on the header,
A first signal line for transferring the header-converted cell from the header conversion unit to the switch unit. A first signal line for transferring a part of information transferred from the header conversion unit to the switch unit. A second signal line to be transferred instead of
The header conversion unit is provided between the header conversion unit and the switch unit. The header conversion unit outputs, to the second signal line, a part of information of the cell after the header conversion, and information other than the part of the information. As a header conversion unit that outputs the signal to the first signal line, and the switch unit as a switch unit that performs the routing using information sent via the first signal line and the second signal line. An exchange characterized by the following. 2. The exchange according to claim 1, wherein information to be transferred using said second signal line is information (output terminal number information) for specifying said one output terminal. switch. 3. The exchange according to claim 1, wherein the header conversion unit holds a header reference unit for referring to a header of an input cell, and information for header conversion, and, based on the held information, A table unit that searches and outputs information for rewriting the header of the input cell based on information obtained by the header reference unit by referring to the input cell; and, based on the rewrite information output by the table unit. A header writing unit that rewrites a header of an input cell and outputs it as an output cell to the first signal line; and extracts information to be output to the second signal line from information held in the table unit. An exchange comprising a header conversion unit including an information extraction unit for outputting to the second signal line. 4. The exchange according to claim 1, wherein the switch unit is configured such that a unit switch is connected in multiple stages, and the header conversion unit is connected to each input of a unit switch in a first stage by the header conversion unit.
And a switch unit connected via a second signal line, wherein each unit switch converts the information transferred by the first signal line from the information transferred by the second signal line. Delay means for delaying, and a selector for switching a path by information transferred by the second signal line, and transferring the information transferred by each of the first signal line and the second signal line in parallel. An exchange characterized by being provided as a switch unit, which is a unit switch. 5. The exchange according to claim 1, wherein the header conversion unit includes: a header reference unit that references a header of an input cell; and information for header conversion. A table unit that searches and outputs information for rewriting the header of the input cell based on information obtained by the header reference unit by referring to the input cell; and, based on the rewrite information output by the table unit. A header writing unit that rewrites a header of an input cell and outputs it as an output cell to the first signal line; and information (output terminal number information) that specifies the one output terminal from information held in the table unit. ) As a header conversion unit having an information extraction unit for extracting the information to the second signal line and outputting the information to the second signal line. Each respective input of switch, the header converting portion, the first
And a switch unit connected via a second signal line, wherein each unit switch converts the information transferred by the first signal line from the information transferred by the second signal line. Delay means for delaying, and a selector for switching a path by information transferred by the second signal line, and transferring the information transferred by each of the first signal line and the second signal line in parallel. An exchange characterized by being provided as a switch unit, which is a unit switch.