JPH11338954A - Operational amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an operational amplifier short in calibration time without generating shock noise before and after a self calibration operation. SOLUTION: In this operational amplifier, by cutting off a voltage amplifier 106 constituting the operation amplifier and a capacitor 109 and a current amplifier 110 by an analog switch 107 at the time of self calibration and short- circuiting both input terminals of the voltage amplifier by the analog switch 105, the output of the voltage amplifier is turned to an offset voltage, an offset adjustment part inside the voltage amplifier is adjusted corresponding to the value and an offset is reduced. Since the voltage of the input terminal of the current amplifier is held by the capacitor, the change of the voltage of the input terminal of the current amplifier before and after the self calibration is small and the large shock noise is not generated at an output terminal 111. Also, since the capacitor is cut off from the voltage amplifier and becomes unrelated to a calibration operation, the voltage amplifier obtains a desired voltage amplification factor at a high frequency and the calibration time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier, and more particularly to a circuit configuration of a self-calibrating low offset operational amplifier.

[0002]

2. Description of the Related Art As a conventional operational amplifier for performing self-calibration, there is, for example, TLC4502 of Texas Instruments Inc. described in "Monthly Magazine" Transistor Technology ", August 1997 Issue (CQ Publishing Co.). FIG. 7 is a block diagram showing a schematic configuration of the conventional example. 7, the operational amplifier 506 includes a voltage amplifier 561, a phase compensation capacitor 562, and a current amplifier 563, and this portion corresponds to a normal operational amplifier. Also, 512 is an offset detecting means for self-calibration, 501 is an inverting input terminal,
502 is a non-inverting input terminal and 511 is an output terminal. 503, 504, 505, 507, and 508 are analog switches, 503, 504, and 507 are turned on and off in the same phase, 505 and 508 are turned on in the opposite phase, and
Turn off.

The operation of the conventional operational amplifier shown in FIG. 7 is as follows. First, during normal operation, the analog switches 503, 504, and 507 are turned on, and the analog switches 505 and 508 are turned off. As a result, the input / output terminal of the operational amplifier 506 is connected to an external circuit, and the offset detecting means 512 is disconnected, so that the operational amplifier operates as a normal operational amplifier.

Next, at the time of self-calibration, the analog switches 503, 504, 507 are turned off and the analog switches 505, 508 are turned on. As a result, the operational amplifier 5
The input / output terminal 06 is disconnected from the external circuit, the inverting input terminal (-) and the non-inverting input terminal (+) of the operational amplifier 506 are short-circuited, and the offset detecting means 512 is connected. Therefore, the operational amplifier 506 is in an open-loop non-feedback state. Since the inverting input terminal (-) and the non-inverting input terminal (+) of the operational amplifier 506 are short-circuited, the output of the operational amplifier 506 is obtained by amplifying the input offset voltage. The output voltage is input to the offset detection means 512, a control signal for reducing the offset voltage is sent to the operational amplifier 506, and the resistance (not shown) in the operational amplifier 506 is switched in accordance with the control signal, thereby providing an offset. Perform self-calibration to reduce voltage. The self-calibration operation is performed, for example, when the power is turned on.

[0005]

However, the above conventional example has the following problems. First, in the above configuration, the output terminal 51 is used during the period when the self-calibration is being performed.
Since 1 is in the open state, the potential of the output terminal becomes a value greatly different from that in the normal operation state by the subsequent external circuit. For example, if a pull-down resistor is added to the output terminal 511, the output voltage will change to 0 V during self-calibration regardless of the voltage during normal operation. As a result, a large shock noise may be generated before and after the self-calibration.

Second, there is the problem of calibration time and calibration accuracy. The calibration time and calibration accuracy in this type of operational amplifier greatly depend on the voltage amplification factor of the operational amplifier 506. Hereinafter, the operation of the operational amplifier 506 during self-calibration will be described. The operational amplifier 506 operates as a voltage comparator of the voltage amplification factor AV because the input and output terminals are open. Further, both input terminals (−) and (+) of the operational amplifier 506 are short-circuited, and as a result, the input signal becomes the input offset voltage VOS of the operational amplifier 506. Therefore, an output offset voltage of VOS × AV is generated at the output of the operational amplifier 506. This output offset voltage is input to the offset detection means 512.

The offset detecting means 512 is provided, for example, in FIG.
As shown in FIG. 5, a successive comparator 201 for successively comparing and outputting an input output offset voltage, and the successive comparator 201
During the calculation of the above, the output is held and output as a control signal 113, a register 202, a CONT signal 114 (a signal for switching each analog switch) for performing a self-calibration operation when the power is turned on, and a successive comparator 20.
1. It comprises a signal generation circuit 203 for outputting a clock signal of the register 202.

For example, when the power supply voltage VCC is 5 V,
In order for the successive comparator 201 to operate normally, it is necessary that the operational amplifier 506 saturates the “L” output to 0 V and the “H” output to 5 V and operate as a voltage comparator. Normally, the input offset voltage VOS is ± 25 mV and the voltage amplification factor AV is 60 dB or more, that is, about 1000 times. Therefore, the output offset voltage is theoretically ± 25 volts or more with respect to the center voltage obtained by halving the power supply voltage VCC. However, in actuality, the power supply voltage saturates and the “L” output becomes 0 V,
The "H" output operates as a 5V voltage comparator.

The input voltage required to saturate the output is
It can be represented by the output voltage range / AV. In the case of this example, 5V / 1000 = 5mV. Therefore, the voltage can be compared to the input offset voltage VOS of ± 25 mV (therefore, the vertical width is 50 mV) up to an accuracy of 1/10. For example, if the successive comparator 201 operates with 3-bit precision, this condition is satisfied by 1/8, and VO
S can be reduced to 3.125 mV from ± 25 mV.

The calibration time for performing the above-mentioned calibration operation is at least 3 if the successive comparator 201 is a successive approximation type of 3-bit accuracy.
If the comparison operation is required twice and a voltage amplification rate of 60 dB is obtained at 100 Hz, at least 3/100
A second calibration time is required. In the case of the conventional example, since the phase compensation capacitor 562 is present, the voltage gain of the open loop is reduced from a low frequency range, so that the calibration time is relatively long. When the calibration time is lengthened in this way, there is a problem that the start-up time of the entire device including the operational amplifier is lengthened, which causes inconvenience in use.

The present invention has been made in order to solve the problems of the prior art as described above, and does not generate a shock noise before and after the self-calibration operation, and has a short calibration time or a higher precision. An object of the present invention is to provide an operational amplifier capable of performing offset calibration.

[0012]

In order to achieve the above object, the present invention is configured as described in the appended claims. That is, in the first aspect of the present invention, the voltage amplifier constituting the operational amplifier is disconnected from the capacitance and current amplifiers during self-calibration, and both input terminals of the voltage amplifier are short-circuited. The output is an offset voltage, and an offset adjusting unit in the voltage amplifier is adjusted in accordance with the output to reduce the offset.

With the above configuration, during the self-calibration, of the voltage amplifier, the capacitance and the current amplifier constituting the operational amplifier, the capacitance and the current amplifier are separated, and the self-calibration of the offset is performed by the voltage amplifier alone. Done. Therefore, since the voltage at the input terminal of the current amplifier is held by the capacitance, a change in the voltage at the input terminal of the current amplifier is small before and after the self-calibration, so that there is no possibility that a large shock noise occurs in the output of the output terminal. .

In addition, since the capacitance which causes the calibration time to be longer is separated from the voltage amplifier and becomes independent of the calibration operation, the voltage amplifier can obtain a desired voltage amplification factor at a high frequency, so that the calibration time is shortened. be able to. Also,
If the calibration time is the same, more accurate calibration can be performed.

[0015]

According to the present invention, before and after the self-calibration, the change in the voltage at the input terminal of the current amplifier is small, so that there is no danger of generating a large shock noise at the output terminal. Further, if the calibration time can be shortened or the calibration time is made the same, an effect that higher-precision calibration can be performed can be obtained.

[0016]

1 to 4 are diagrams showing an embodiment of an operational amplifier according to the present invention. FIG. 1 is a block diagram showing the overall configuration, and FIG.
FIG. 3 is a block diagram showing an example of a voltage amplifier 106 having an offset adjustment unit, and FIG. 4 is a block diagram showing another example of the voltage amplifier 106 having an offset adjustment unit.

In FIG. 1, reference numeral 106 denotes a voltage amplifier, 10
Reference numeral 9 denotes a capacity, 110 denotes a current amplifier, and this portion corresponds to a normal operational amplifier. However, the voltage amplifier 106 includes an offset adjustment unit that switches resistance and the like so as to reduce the offset voltage (details will be described later). Also,
An analog switch 103 is connected between the inverting input terminal 101 and the inverting input terminal (-) of the voltage amplifier 106,
An analog switch 104 is connected between the non-inverting input terminal 102 and the non-inverting input terminal (+) of the voltage amplifier 106. The inverting input terminal (-) and the non-inverting input terminal (+)
Is connected to the analog switch 105. An analog switch 107 is connected between the output terminal of the voltage amplifier 106 and the input terminal of the current amplifier 110.
The output terminal of the current amplifier 110 is connected to the output terminal 111. Further, the output terminal of the voltage amplifier 106 is connected to the input of the offset detection means 112 via the analog switch 108, and a control signal 113 (digital signal) output from the offset detection means 112 is output from the voltage amplifier 106.
And a CONT signal 114 for opening and closing each analog switch is sent to each analog switch.
The analog switches 103, 104, and 107 are turned on and off in the same phase, and the analog switches 105 and 108 are turned on and off in the opposite phase.

FIG. 2 shows the above-mentioned offset detecting means 112.
FIG. 3 is a block diagram showing the configuration of FIG. The circuit shown in FIG. 2 includes a successive comparator 201 that successively compares and outputs an output offset voltage input to IN from the voltage amplifier 106 of FIG. 1 via the analog switch 108, and outputs the same during the operation of the successive comparator 201. A register 202 which holds an output and outputs it as a control signal 113, a CONT signal 114 (a signal for switching each analog switch) for performing a self-calibration operation at power-on, and a clock signal for the successive comparator 201 and the register 202 Signal generating circuit 2 that outputs
03.

FIG. 3 is a block diagram showing an example of the voltage amplifier 106 of FIG. In FIG. 3, the first-stage differential amplifier 304 includes a constant current source and two transistors.
The gates of the two transistors serve as the inverting input terminal (-) and the non-inverting input terminal (+), respectively. Also 30
3 is a current mirror circuit, 302 is a resistor group, and 301 is an analog switch group. In this circuit, the analog switch group 301 is switched according to the control signal 113 of the digital data sent from the offset detection means 112 to the control signal input terminal 305, and the combined resistance value of the resistor group 302 (4R on the left) By changing the 2R and R combined resistance values), the offset voltage can be adjusted by balancing the differential amplifier 304. Note that the output of the differential amplifier is output as the output of the voltage amplifier 106 via a voltage amplification stage (not shown).

FIG. 4 is a block diagram showing another example of the voltage amplifier 106. In place of the resistor group 302 and the current mirror circuit 303 in FIG. Is provided. Also in this case, by changing the analog switch group 301 and changing the combined value of the transistor group of the current mirror circuit 403, the offset voltage can be adjusted by balancing the differential amplifier 304.

Next, the operation will be described. First, the operation as a normal operational amplifier will be described. In this case, the analog switches 103, 104, and 107 are turned on, and the analog switches 105 and 108 are turned off.
As a result, the input signal input to the inverting input terminal 101 is transmitted to the inverting input terminal (-) of the voltage amplifier 106. on the other hand,
The input signal input to the non-inverting input terminal 102 is the voltage amplifier 1
06 to the non-inverting input terminal (+). Voltage amplifier 1
The output signal 06 is input to the input terminal of the current amplifier 110. The capacitor 109 connected to the input terminal of the current amplifier 110
Operate as a phase compensation capacitor, which is indispensable as an operational amplifier. The output of the current amplifier 110 is output to an output terminal 111. The above operation is exactly the same as that of a general operational amplifier.

At this stage, the control signal 113 output from the offset detecting means 112 has an initial value in which the combined value of the resistor group 302 makes the loads of both transistors of the differential amplifier 304 substantially equal. Set as follows.
For example, in the resistor group 302 of FIG.
The combined resistance value of R and R is set to be the same as 2R on the right. In order to set in this way, for example, if a 3-bit offset adjustment unit is used as shown in the figure, the initial value is set to "010" at the approximate center as shown in the timing chart of FIG. In this state, the entire operational amplifier operates as an operational amplifier having an initial offset.

Next, the operation in the self-calibration mode will be described. Signal generation circuit 203 of offset detection means 112
Outputs the CONT signal 114 when the power is turned on, turns off the analog switches 103, 104 and 107, and turns on the analog switches 105 and 108. Therefore, both the inverting input terminal 101 and the non-inverting input terminal 102 are shut off, and the inverting input terminal (-) and the non-inverting input terminal (+) of the voltage amplifier 106 are short-circuited. Then, the current amplifier 109 is separated from the voltage amplifier 106, and the output of the voltage amplifier 106 is supplied to the offset detecting means 112.

The operation of the preceding stage centering on the voltage amplifier 106 at this time will be described with reference to the timing chart of FIG. First, when the self-calibration mode is entered when the power is turned on, first, the CONT signal 114 of the offset detection means 112 becomes "L", whereby the analog switch 107 is turned off. As a result, the current amplifier 110 and the capacitor 109 are separated from the voltage amplifier 106 and operate as a sampling and holding circuit. In this state, the voltage at the input terminal of the current amplifier 110 (terminal voltage of the capacitor 109)
Keeps the value at the time of disconnection substantially unchanged, so that a substantially constant output voltage is output to the output terminal 111 during the self-calibration operation.

When the CONT signal 114 becomes "L" as described above, the analog switches 103 and 104 are also turned off, and the analog switches 105 and 108 are turned on. As a result, since the input and output of the voltage amplifier 106 are opened, the voltage amplifier 106 operates as a voltage comparator of the voltage amplification factor AV. Further, since the input of the operational amplifier 106 is short-circuited, the input signal eventually becomes the input offset voltage V
OS. Therefore, the output of the voltage amplifier 106 is VOS
A × AV output offset voltage is generated. This output offset voltage is input to the offset detection means 112.

As shown in FIG. 2, the offset detecting means 112 comprises a successive comparator 201, a register 202 for holding its output, and a signal generating circuit 203. In order to operate the successive comparator 201 normally, it is necessary to saturate the voltage amplifier 106 so that the “L” output is 0 V and the “H” output is 5 V, and operate the voltage amplifier 106 as a voltage comparator. Normal,
Input offset voltage VOS is ± 25 mV, voltage amplification factor A
Since V is 60 dB or more, that is, about 1000 times, the output offset voltage becomes theoretically ± 25 volts or more with respect to the center voltage obtained by halving the power supply voltage VCC. The "L" output operates as a voltage comparator with 0V and the "H" output with 5V. The input voltage required to saturate the output is represented by the output voltage range / AV. In the case of this example, 5V / 1000 = 5mV. Therefore, the voltage can be compared up to an accuracy of 1/10 with respect to VOS of ± 25 mV. Therefore, if the successive comparator 201 has 3-bit accuracy, this condition is satisfied by 1/8, and the input offset voltage VOS is 3.12 with respect to ± 25 mV.
It can be reduced to 5 mV. If the successive comparator 201 is a successive approximation type with 3-bit accuracy as shown in FIG.
It is necessary to perform the comparison operation twice. It should be noted here that the capacitor 109 is not included in this operation. Therefore, voltage amplifier 106 operates as a comparator that does not require phase compensation, rather than an operational amplifier that requires phase compensation.

Here, the above-described successive approximation operation is described with reference to FIG.
This will be described in detail with reference to the timing chart of FIG. In FIG. 5, the uppermost characteristic indicates the potential of the CONT signal 114. When the potential of the CONT signal 114 is "H", the analog switches 103, 104, and 107 are turned on, and the analog switches 105 and 108 are turned off. On the other hand, when it is "L", the analog switches 103, 104 and 107 are turned off, and the analog switches 105 and 108 are turned on. The second characteristic indicates the potential of the output terminal 111. The third characteristic indicates a signal in which the potential at the input terminal IN of the successive comparator 201, that is, the offset voltage is amplified to “H” or “L” by the voltage amplifier 106. The fourth characteristic indicates the output of the successive comparator 201. In the present embodiment, it is a 3-bit digital code. The fifth characteristic indicates the output 113 of the latch circuit 202, that is, the control signal of the voltage amplifier 106. In the present embodiment, it is a 3-bit digital code.

The first step is to connect the CON as described above.
When the T signal 114 is "H", it operates as a normal operational amplifier. At this time, the output code 113 is set to "010" which is close to the center of the 3-bit digital code. This is for setting the offset voltage of the operational amplifier in the standard state to the setting center.

In the next step, as described above, CONT
The signal 114 is set to "L" to enter the self-calibration mode. In the self-calibration mode, the successive approximation operation is performed to calibrate the offset voltage. First, in the first comparison, the value of the most significant bit (MSB) is determined. That is, the output code of 113 is set to “100”, and the value of the most significant bit (MSB) is determined by reading the potential of the input terminal IN of the successive comparator 201 at that time, that is, the value obtained by amplifying the offset voltage by the voltage amplifier 106. I do. In the case of this embodiment,
In the voltage amplifier shown in FIG. 3 or FIG. 4, when "100" is input as the control signal, the current flows more easily in the left circuit in the internal differential amplifier. For example, in the case of FIG. 3, the three combined resistance values on the left side of the resistor group 302 are R, the resistance value on the right side is 2R, the resistance on the left side is low, and the current easily flows. Although not shown in FIG. 3 or FIG. 4, the output of the differential amplifier is output as the output of the voltage amplifier 106 through the voltage amplification stage. As described above, the current flows through the circuit on the left side of the differential amplifier. When the output voltage of the voltage amplifier increases when it becomes easier, it is understood that a digital code that reduces the output voltage of the voltage amplifier should be set to cancel the offset.
That is, when the potential of the input terminal of the successive comparator 201 is “H”, the most significant bit (MSB) is “L”, and when it is “L”, the most significant bit (MSB) is “H”. In the example of FIG. 5, since the potential at the input terminal of the successive comparator 201 is "L", the most significant bit (MSB) is determined to be "H", that is, "1xx" and a digital code of 4 or more and 7 or less.

Similarly, in the second comparison, the value of the second bit is determined. That is, the output code of 113 is set to “110” since the most significant bit (MSB) is “H”, and by reading the potential at the input terminal of the successive comparator 201 at that time, that is, the value obtained by amplifying the offset voltage by the voltage amplifier 106, Determine the value of the second bit. In the example of FIG. 5, since the potential at the input terminal of the successive comparator 201 is "H", it is determined that the second bit is "L", that is, "10x" and is a digital code of 4 or more and 5 or less.

Finally, in the third comparison, the value of the third bit [least significant bit (LSB)] is determined. That is, 11
The output code of “3” is “10” because the upper two bits are “10”.
1 ", the potential of the input terminal of the successive comparator 201 at that time,
That is, the value of the third bit is determined by reading the value obtained by amplifying the offset voltage by the voltage amplifier 106.
In the example of FIG. 5, the potential of the input terminal of the successive comparator 201 is “L”.
Therefore, the third bit becomes “H”, that is, “101”, and
5 digital code. As described above, in the example shown in FIG. 5, when the digital code of “101” is given as the control signal of the voltage amplifier 106, the offset can be canceled most. When the digital code is determined in this way, the CONT signal 114 is returned to "L" to operate as a normal operational amplifier.

FIG. 6 is a characteristic diagram showing an open loop voltage gain characteristic of the operational amplifier. In the case of the conventional example, since the phase compensation capacitor 562 is included in the operation of the operational amplifier 506, the voltage gain of the open loop is reduced from a low frequency range, and the frequency characteristic is as shown by a broken line in FIG. .
For example, assuming that the voltage amplification factor of the open loop of the operational amplification unit 506 is 60 dB at 100 Hz, if the voltage amplification factor of 60 dB is required for the process for calibration, the process can be performed 100 times per second. Since three bits require a total of three processes, one calibration time is at least 3/1.
00 seconds are required.

On the other hand, in the case of the present embodiment, since the capacitance 109 is not included in the operation of the voltage amplifier 106, the frequency characteristic becomes as shown by the solid line in FIG. In the case of this example, a voltage amplification factor of 60 dB is obtained at 1 kHz, so that three processes require a minimum calibration time of 3/1000 seconds. Thus, the same offset performance can be obtained in 1/10 the processing time as compared with the conventional example.

Next, when the calibration operation is completed, the CONT signal 114 automatically returns to the normal operation state in response to the completion of the self-calibration operation (the predetermined number of successive approximation calculations is completed). That is, the CONT signal 114 becomes "H", the analog switches 103, 104, and 107 are turned on, and the analog switches 105 and 108 are turned off. As a result, the connection state returns to the normal operation state again, the input signal input to the inverting input terminal 101 is transmitted to the inverting input terminal (-) of the voltage amplifier 106, and the input signal input to the non-inverting input terminal 102 is The signal is transmitted to the non-inverting input terminal (+) of 106. Also,
The output signal of the voltage amplifier 106 is input to the input terminal of the current amplifier 110, and the capacitor 109 connected to the input terminal of the current amplifier 110 operates as a phase compensation capacitor. The output of the current amplifier 110 is output to an output terminal 111.

The subsequent operation is the same as before self-calibration,
The difference is that the voltage amplifier 106 is self-calibrating and has a reduced offset voltage. Also, during the self-calibration, the voltage at the input terminal of the current amplifier 110 is held by the capacitor 109.
The change in the voltage at the input terminal of the current amplifier 110 is small, so that there is no possibility that a large shock noise is generated in the output of the output terminal 111.

Hereinafter, the offset voltage will be described in detail. Output offset voltage VO as operational amplifier as a whole
Sout is as shown in the following equation (1). VOSout = [(Input offset voltage of voltage amplifier × Voltage amplification rate of voltage amplifier) + Input offset voltage of current amplifier] × Voltage amplification rate of current amplifier ... (Equation 1) Normally, voltage amplification rate of voltage amplifier >> Current amplifier Since the voltage amplification factor of the current amplifier is substantially 1, the above equation (1) can be expressed as the following equation (2). VOSout = (input offset voltage of voltage amplifier × voltage amplification rate of voltage amplifier) + input offset voltage of current amplifier (2) Therefore, (input offset voltage of voltage amplifier × voltage amplification rate of voltage amplifier) >> current amplification VOSout = input offset voltage of voltage amplifier × voltage amplification factor of voltage amplifier = VOS × AV (Equation 3), and output offset voltage V of the entire operational amplifier
OSout is the same as the output offset equation of the voltage amplifier alone.

Normally, the input offset voltage of the current amplifier is a substantially constant value of about 0 to 600 mV, and it is easy to set it near 0 mV by using a level shift together. Therefore, the output offset of the operational amplifier can be approximated by the expression of the output offset of the voltage amplifier alone.

The input offset voltage VOS of the operational amplifier as a whole can be expressed by the following equation (4). VOS = [(output offset voltage of operational amplifier / voltage amplification factor of current amplifier) −input offset voltage of current amplifier] ÷ voltage amplification factor of voltage amplifier (Equation 4) Normally, output offset voltage of operational amplifier >> current amplifier And the voltage amplification factor of the current amplifier is almost 1, the above equation (4) can be expressed as the following equation (5). VOS = the output offset voltage of the operational amplifier / the voltage amplification factor of the voltage amplifier (5) Since the output offset voltage of the operational amplifier is substantially equivalent to the output offset voltage of the voltage amplifier, VOS = the output offset voltage of the voltage amplifier ÷ voltage. It becomes the voltage amplification factor of the amplifier, and the input offset voltage V as the entire operational amplifier
OS can be approximated by the expression of the input offset of the voltage amplifier alone.

As described above, the output offset and input offset of the entire operational amplifier can be approximated by the output offset and input offset of the voltage amplifier alone. Therefore, as described in the above embodiment, the voltage amplifier 106
Voltage amplifier 1 by self-calibrating the offset of
06, the phase compensation capacitor 109, and the offset of the entire operational amplifier including the current amplifier 110 can be calibrated.

Next, the offset detecting means 1 shown in FIG.
12 and the case where the offset adjuster of the voltage amplifier 106 shown in FIGS. 3 and 4 has 6-bit precision.
Although a circuit in this case is not shown, a control signal 113 of 6-bit digital data is output from the offset detection means 112 in FIG. 2, and the number of switches of the analog switch group 301 is 6 in FIGS. 6 equivalent to a bit
4 in that the number of combined resistors of the resistor group 302 or the number of current mirror resistors 403 in FIG.

In this case, the offset detecting means 112
The input offset voltage VOS is ± 25 mV since the offset adjustment unit in the voltage amplifier 106 has 6 bits.
Can be reduced to 1/64 ± 0.4 mV. However, if the successive comparator 201 in FIG. 2 has 6-bit precision, at least six comparison operations are required. Further, the voltage amplification factor AV of the voltage amplifier 106 needs to be one that only saturates the output at ± 0.4 mV, which is 60 dB in 3-bit accuracy, but 8 times that, ie, 60+
6 × 3 = 78 dB is required. In this case, since the voltage amplification rate of 78 dB is obtained at 125 Hz from FIG. 6, the calibration time of 6/125 = 0.048 seconds is sufficient for six comparison operations.

When the precision is 6 bits in the conventional example, a voltage amplification rate of 78 dB is required in the same manner as described above. However, according to the characteristics of the conventional example shown by the broken line in FIG. Obtained at a frequency of 12.5 Hz. Therefore, the processing is performed 12.5 times per second, and the calibration time is 6 / 12.5 =
It takes 0.48 seconds.

As described above, when the present invention is compared with the conventional example, if the calibration accuracy is the same at the 3-bit accuracy or the 6-bit accuracy, the calibration time can be reduced to about 1/10. Further, if the conventional example is set to 3-bit accuracy and the present invention is set to 6-bit accuracy, it is possible to perform the offset calibration with 8 times accuracy in about twice the calibration time as the conventional example. Therefore, if the calibration time is made the same, it is possible to greatly improve the calibration accuracy. Conversely, if the calibration accuracy is made the same, the calibration time can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of an operational amplifier according to the present invention.

FIG. 2 is a block diagram illustrating an example of an offset detection unit.

FIG. 3 is a block diagram showing an example of a voltage amplifier having an offset adjustment unit.

FIG. 4 is a block diagram showing another example of the voltage amplifier having an offset adjusting unit.

FIG. 5 is a timing chart of the operation in FIG. 1;

FIG. 6 is a characteristic diagram showing an open loop voltage gain characteristic of the operational amplifier.

FIG. 7 is a block diagram showing a schematic configuration of a conventional operational amplifier.

[Explanation of symbols]

Reference Signs List 101 inverting input terminal 102 non-inverting input terminal 103, 104, 105, 107, 108 analog switch 106 voltage amplifier 109 capacitance 110 current amplifier 111 output terminal 112 offset detection means 113 control signal 114 CONT Signal 201: Successive comparator 202: Latch circuit 203: Signal generation circuit 301: Analog switch group 302: Resistor group 303: Current mirror circuit 304: First stage differential amplifier 403: Current mirror transistor group 501: Inverting input terminal 502: Non Inverting input terminal 503, 504, 505, 507, 508 Analog switch 506 Operational amplifier 511 Output terminal 512 Offset detection means 561 Voltage amplifier 562 Phase compensation capacitance 563 Current amplifier

Claims (4)

[Claims] A first analog switch connected between an inverting input terminal and an inverting input terminal of a voltage amplifier; and a first analog switch connected between a non-inverting input terminal and a non-inverting input terminal of the voltage amplifier. 2 analog switches, a third analog switch connected between the inverting input terminal and the non-inverting input terminal of the voltage amplifier, and a third analog switch connected between the output terminal of the voltage amplifier and the input terminal of the current amplifier. A fourth analog switch connected between the output terminal of the voltage amplifier and the input terminal of the control means; and a fourth analog switch connected between the input terminal of the current amplifier and a ground or power supply terminal. And an output terminal connected to an output terminal of the current amplifier; turning on the first, second, and fourth analog switches during normal operation; turning off the third and fifth analog switches; Self-calibration Sometimes, the first, second, and fourth analog switches are controlled to be turned off, and the third and fifth analog switches are controlled to be turned on.
Sending a signal corresponding to the offset voltage of the voltage amplifier input through the analog switch to the voltage amplifier,
An operational amplifier comprising: a control unit that controls an offset adjusting unit in the pre-voltage amplifier to reduce the offset. 2. A control system comprising: a comparator for sequentially comparing input offset voltages of the voltage amplifier; a register for temporarily holding an output of the comparator and sending the output to the voltage amplifier;
The operational amplifier according to claim 1, further comprising: a signal generation circuit that outputs a signal for switching each of the analog switches in order to perform a self-calibration operation when power is turned on. 3. The voltage amplifier according to claim 1, wherein a plurality of resistors connected in series or in parallel and a plurality of analog switches are connected in series or in parallel, and a total input resistance is changed by a control input to the analog switches. The operational amplifier according to claim 1, further comprising an offset adjustment unit that adjusts the offset. 4. The voltage amplifier according to claim 1, wherein a plurality of transistors connected in series or in parallel and a plurality of analog switches are connected in series or in parallel, and the size of the overall combined transistor is changed by a control input of said analog switch. 2. The operational amplifier according to claim 1, further comprising an offset adjusting unit for adjusting an offset.