JPH11330279A - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [Problem] Control gate 104 and gate electrode 10
A method for manufacturing a nonvolatile semiconductor memory device capable of reducing the distance between the semiconductor device and the nonvolatile semiconductor memory device. SOLUTION: A silicon oxide film 77 is formed on a polysilicon film 24, the polysilicon film 24 is selectively removed by etching using the silicon oxide film 77 as a mask, and a control gate 104 and a gate electrode 102 are simultaneously formed. . Then, the polysilicon film 14 is selectively etched away using the silicon oxide film 77 on the control gate 104 as a mask, and the floating gate 110 is removed.
To form

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device which stores information by accumulating electric charges and a method of manufacturing the same. More particularly, the present invention relates to a nonvolatile semiconductor memory device in which a memory element is selectively operated by a field effect transistor. The present invention relates to an apparatus and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a nonvolatile semiconductor memory device having a memory element having a floating gate and a control gate, for example, there is a flash memory. There are various types of flash memories, and there is a type in which a storage element is selectively operated by a field effect transistor. Such a type of flash memory is disclosed in, for example, JP-A-6-275847. Hereinafter, JP-A-6-275847
A method of manufacturing a flash memory disclosed in Japanese Patent Application Laid-Open No. H11-260, will be described with reference to FIGS.

As shown in FIG. 23, on a main surface of a semiconductor substrate 200, a silicon oxide film 202 serving as a tunnel oxide film and a polysilicon film 204 serving as a floating gate are formed in this order. As shown in FIG. 24, the polysilicon film 204 on the select transistor formation region 232 is selectively etched away to leave the polysilicon film 204 on the storage element formation region 234. This polysilicon film 204
Hereinafter, this is referred to as a polysilicon film 204a. As shown in FIG. 25, the ONO film 20 is formed on the polysilicon film 204a.
6. A silicon oxide film 208 serving as a gate oxide film is formed on the select transistor formation region 232, respectively. Then, a polysilicon film 210 is formed on the ONO film 206 and the silicon oxide film 208.

As shown in FIG. 26, a polysilicon film 21 is formed.
, A polysilicon film 210 is selectively removed by etching using the resist 212 as a mask, and the polysilicon film 2 on the storage element formation region 234 is formed.
10, the select transistor formation region 232 is left.
A gate electrode 214 is formed thereover. Storage element formation area 2
Hereinafter, the polysilicon film 210 on the reference numeral 34 is referred to as a polysilicon film 210a. By this etching, the gate electrode 2
The silicon oxide film 208 on the main surface 236 of the semiconductor substrate 200 between the semiconductor device 14 and a floating gate to be formed later is exposed. As shown in FIG.
12 is removed, and a resist 216 is formed in the storage element formation region 23.
4 and the select transistor formation region 232.
As a mask for forming the control gate,
The resist 216 is patterned.

Incidentally, the resist 216 is formed on the gate electrode 21.
4 and the end face 216a of the polysilicon film 20
4a and 210a are patterned so as not to overlap. The gate electrode 214 covers the gate electrode 21.
4 is made of the same material as the control gate and the floating gate, that is, polysilicon,
This is to prevent the gate electrode 214 from being etched in the subsequent etching for forming the control gate and the floating gate. The patterning is performed so that the end surface 216a does not overlap the polysilicon films 204a and 210a. When the end surface 216a overlaps the polysilicon films 204a and 210a, the polysilicon is formed for forming the control gate and the floating gate thereafter. This is because unnecessary portions of the polysilicon films 210a and 204a remain on the main surface of the semiconductor substrate 200 when the silicon films 210a and 204a are etched. Therefore,
The silicon oxide film 20 on the main surface 236 between the gate electrode 214 and the floating gate formed later
The resist 216 will be patterned while leaving the exposed portion 8.

Using the resist 216 as a mask, the polysilicon film 210a is first selectively etched away to form a control gate 218. As shown in FIG. 28, using the resist 216 as a mask,
6 is selectively removed by etching. By this etching, the exposed silicon oxide film 208 is also etched, and the main surface 236 between the gate electrode 214 and a floating gate formed later is exposed.

As shown in FIG. 29, using the resist 216 as a mask, the polysilicon film 204a is selectively etched away to form a floating gate 220. Since the main surface 236 is exposed, the main surface 236 is also etched by this etching, and the main surface 236 is exposed.
6, a groove 222 is inevitably formed. Resist 21
Then, using the mask 6 as a mask, ions are implanted into the main surface of the semiconductor substrate 200 to form a source / drain 224 in the memory element formation region 234 and an impurity region 226 electrically connected to the source / drain 224 in the groove 222. Form.

As shown in FIG. 30, a silicon oxide film 228 is formed on the main surface of the semiconductor substrate 200, and a contact hole 238 exposing the source / drain 224 is formed in the silicon oxide film 228. As shown in FIG. 31, aluminum wiring 230 is formed on silicon oxide film 228. Aluminum wiring 230 is also formed in contact hole 238 and is electrically connected to source / drain 224. The storage element 242 includes the control gate 21
8, a floating gate 220 and a source / drain 224. The selection transistor 244 includes a gate electrode 214 and a source / drain 240.

[0009]

As described above,
Conventionally, the control gate 218 and the gate electrode 214
And had been made in a separate process. Therefore, a mask for forming the control gate 218 and the gate electrode 214
It is necessary to consider the margin of mask alignment with the mask for formation, and the control gate 218 and the gate electrode 2
This is the reason why the distance between the two cannot be reduced.

The present invention has been made to solve such a conventional problem, and provides a nonvolatile semiconductor memory device capable of reducing the distance between a control gate and a gate electrode, and a method of manufacturing the same. That is.

[0011]

A method of manufacturing a nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate having a main surface including a first region and a second region, and a semiconductor substrate formed on the first region. A storage element including a floating gate and a control gate formed on the floating gate, and a select gate transistor including a gate electrode formed on the second region and selectively operating the storage element. A method for manufacturing a nonvolatile semiconductor memory device includes the following steps.

Forming a tunnel insulating film on the first region, forming a first conductive film serving as a floating gate on the tunnel insulating film, forming a first conductive film on the first conductive film; Forming a dielectric film, forming a gate insulating film on the second region, forming a second conductive film on the dielectric film and the gate insulating film. ,
Forming, on the second conductor film, a mask film serving as a mask when the first conductor film has a different etching rate from that of the first conductor film and is selectively etched away;
Selectively etching away the mask film and the second conductor film to simultaneously form a control gate and a gate electrode. The mask film remains on the control gate. Forming a first resist so as to cover the gate electrode; selectively etching away the first conductor film using the mask film above the control gate and the first resist as a mask; And forming a.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, since the control gate and the gate electrode are formed simultaneously, the mask for forming the control gate and the mask for forming the gate electrode are aligned. There is no need to consider the margin. Therefore, the distance between the control gate and the gate electrode can be reduced.
The reason why they can be formed at the same time is that the floating gate can be formed using the mask film as a mask because the mask film is provided on the control gate. Therefore, in the step of forming the first resist so as to cover the gate electrode,
This is because it is not necessary to form the first resist on the second conductive film in the first region. Conventionally, using the first resist as a mask, the second and first conductor films are selectively etched away to form a control gate and a floating gate.

As a preferable step of simultaneously forming a control gate and a gate electrode from the step of forming a mask film, a step of forming a second resist on the mask film, and a step of forming a mask film and a second resist using the second resist as a mask. And forming a control gate and a gate electrode simultaneously by selectively etching away the second conductive film.

As a more preferable step of simultaneously forming a control gate and a gate electrode from the step of forming a mask film, a step of forming a third resist on the mask film, and a step of forming a mask film using the third resist as a mask There is a step including a step of selectively etching and removing, and a step of selectively etching and removing the second conductor film using the mask film as a mask to simultaneously form a control gate and a gate electrode.

It is preferable that the mask film includes an insulating film. Preferably, the mask film includes a silicon oxide film. The thickness of the mask film is preferably 200 to 300 nm.

According to a method of manufacturing a nonvolatile semiconductor memory device according to the present invention, there is provided a nonvolatile semiconductor memory device in which a plurality of storage elements and select gate transistors are provided, and one select gate transistor selectively operates only one memory element. Preferably applied to the method.

A non-volatile semiconductor memory device according to the present invention is a non-volatile semiconductor memory device that stores information by accumulating electric charges, comprising: a semiconductor substrate having a main surface including a first region and a second region; A storage element including a floating gate formed on the first region and a control gate formed on the floating gate, and a gate electrode formed on the second region, for selectively operating the storage element A first film having the same width as the select gate transistor, the control gate, and a different etching rate from the floating gate, and being located on the control gate, and having the same width as the gate electrode; A second film including the same material and located on the gate electrode.

In a preferred embodiment of the nonvolatile semiconductor memory device according to the present invention, the thickness of the first film is smaller than the thickness of the second film.

In another preferred embodiment of the nonvolatile semiconductor memory device according to the present invention, the storage element includes a first source / drain formed in a first region, a first source / drain formed between the first source / drain and a control gate. A second region formed in the first region at an interval from the source / drain;
The select gate transistor includes a third source / drain formed in the second region and a second source / drain spaced from the third source / drain so as to sandwich the gate electrode. And a fourth source / drain formed in the region, a groove is inevitably formed in a main surface between the floating gate and the gate electrode,
The non-volatile semiconductor memory device is further formed on the main surface so as to cover the trench, and has the second source / drain and the third
Impurity region electrically connecting the source / drain of the semiconductor device.

In still another preferred embodiment of the nonvolatile semiconductor memory device according to the present invention, the impurity region has a higher impurity concentration than the first and fourth source / drain.

In still another preferred embodiment of the nonvolatile semiconductor memory device according to the present invention, the first and second films include an insulating film.

As still another preferred embodiment of the nonvolatile semiconductor memory device according to the present invention, the first and second films include a silicon oxide film.

In still another preferred embodiment of the nonvolatile semiconductor memory device according to the present invention, the first film has a thickness of 80%.
To 200 nm, and the thickness of the second film is 200 to 300 nm.

In still another preferred embodiment of the nonvolatile semiconductor memory device according to the present invention, there are a plurality of storage elements and a plurality of selection gate transistors, and one selection gate transistor selectively operates only one storage element.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention, which will be described below, has a plurality of storage elements and includes a plurality of selection transistors for selecting and operating the storage elements, and each selection transistor uses only one storage element. The present invention is applied to a nonvolatile semiconductor memory device to be selectively operated. However,
The present invention is not limited to this.
The present invention can be applied to a nonvolatile semiconductor memory device in which a storage element is selectively operated by a selection transistor such as an R type, a NAND type, and a DINOR type.

First, a nonvolatile semiconductor memory device having a plurality of storage elements, a plurality of selection transistors for selecting and operating the storage elements, and each selection transistor for selectively operating only one storage element will be described with reference to FIGS. This will be described with reference to FIGS. FIG. 3 is a schematic diagram of a memory cell 400 of the flash memory. The memory cell 400 includes a selection transistor 401 and a memory transistor 402 which is a storage element. The selection transistor 401 has a gate 401A, and the memory transistor 402 has a floating gate 403 and a control gate 404. The selection transistor 401 is an N-channel MO
It is an SFET and its threshold voltage is about 0.7V.

To program the memory cell 400 by channel hot electrons, a positive program high voltage V _pp , for example, 5 to 12 V, is applied to the selection transistor 401.
12V is applied to the memory transistor 40
2 and the source 408 of the memory transistor 402 is held at the ground potential V _ss at the same time, and a positive programming pulse is applied to the drain 406 of the selection transistor 401. For example, a programming pulse of about 5 V is applied for 100 microseconds. In FIG. 4, the memory transistor 402
(Which is also the source of the select transistor 401) is formed by heavily doping 510 the substrate. This ion implantation of the drain enhances the electric field in the portion of the channel region 511 near the drain 407. This accelerates the electrons and creates a distribution of high-energy electrons that is active enough to overcome the potential energy barrier, where the electrons move through the thin tunnel film to the floating gate 403 (eg, hot electron injection). . The speed of the program is increased by an order of magnitude by the ion implantation for heavily doping the drain 407. The width of the memory transistor 402 is 0.2
Since the width of the select transistor 401 is typically 1.0 to 5.0 μm, as compared to 5 to 1.5 μm, the select transistor 401 can reduce a small portion of the applied drain pulse voltage. use.

Erasing the memory cell 400 is accomplished by applying 5 V to the source 408 of the memory transistor 402, while holding the control gate 404 at -7V. Tunnel oxide film 405 shown in FIG.
A high electric field is generated at the floating gate 40
The electrons collected at 3 overcome the potential energy barrier and move through the tunnel oxide 405 (eg, via a Fowler-Nordheim tunnel) to the source 408 of the memory transistor 402. During erasing, the gate 401A
, A voltage of 5 to 12 V is applied, and the drain 406 is kept in a floating state.

The source 408 of the memory transistor 402
Is formed by heavily doping 512 the substrate. This heavy doping increases junction breakdown, thereby significantly accelerating the transfer of electrons from the floating gate during erasure. In this manner, the erase operation of the memory transistor 402 proceeds to the extent that the threshold voltage of the memory transistor 402 becomes negative during the erase operation. Therefore, the memory transistor 402 is connected to the control gate 4
Can't be turned off by 04. However, select transistor 401 prevents this over-erase from affecting the operation of the cell. Specifically, since the selection transistor 401 is not controlled by the state of the floating gate, the selection transistor 4
The threshold voltage of 01 is maintained at about 0.7V.

In addition to the program / erase operation described above, various operating conditions can be set. For example, when both the program and erase operations are based on Fowler-Nordheim tunneling, the following conditions may be satisfied. During programming, the control gate is -8V, the source is floating,
The drain is 8 V, and the gate of the selection transistor is 8 V. At the time of erasing, the control gate is 8 V, the source is -8 V, the drain is in a floating state, and the gate of the selection transistor is 8 V.

FIG. 5 shows a schematic diagram of a memory array 600 including memory cells 400A-400D. Each memory cell is the same as the memory cell 400. Cell 400
A, drain 40 of 400B select transistor 401
6 is coupled to the metal drain bit line 631 and is connected to the memory transistor 40 of the cell 400A, 400B.
The two sources 408 are coupled to a metal source bit line 630. Memory cell 400A and memory cell 400
The gate 401A of the D select transistor 401 is coupled to a word line 520, and the control gates 404 of the memory cells 400A and 400D are coupled to a control line 521.

In FIG. 5, in order to read data from the memory cell 400, for example, the memory cell 400A, the word line 5
20 through the gate 401A, the control line 52
1, a standard voltage _Vcc (typically 5 V) is applied to the control gate 404, and at the same time, a read current flowing through the memory cell 400A by a conventional sense amplifier (not shown) connected to the drain bit line 631. Can be achieved by detecting If the memory cell 400A is erased (that is, the charge of the floating gate 403 is 0 or relatively positive), the selection transistor 401
And the memory transistor 402 are both turned on, and a current that can be detected by the sense amplifier flows through the memory cell 400A. If the memory cell 400A is programmed (ie, if the floating gate 402 has a relatively negative charge), the threshold voltage of the memory transistor 402 will increase until it exceeds the supply voltage _Vcc , This prevents a current from flowing through the memory cell 400A.

According to this configuration, the sense amplifier receiving the voltage of the drain bit line generates a feedback voltage to the source bit line 630. Accordingly, the voltage of the source bit line 630 during the read operation is increased. In this way, the voltage drop on the drain bit line 631 is reduced. Therefore, according to this memory cell array, compared with the conventional memory cell array, the time required for the bit line to return to the original state so that the detection can be performed during the next logic state cycle is significantly reduced.

A major limitation in scaling memory transistor 402 is the requirement for punch-through. Drain 407 and floating gate 40
With a capacitive junction of 3, the memory transistor 402 is typically turned on by coupling to the drain 407. This capacitive junction limits the scalability of the channel length 511 (FIG. 4), thereby limiting the programming speed required for 5V programming performance. Specifically, the capacitive junction from the drain 407 to the floating gate 403 degrades the tolerance of the memory transistor 402 for punch-through, thereby limiting the ability of the memory transistor 402 to handle the drain voltage. The effect of the capacitance junction is not proportional to the gate line width of the memory transistor 402 due to the strong effect of the fringing capacitance, that is, the capacitance other than the parallel plane capacitance. Therefore, the effect of this drain junction becomes more dominant as the structure becomes smaller, and in a conventional EEPROM or flash memory without an access gate, it becomes a serious scaling constraint. By the way, the programming speed increases exponentially with the reciprocal of the effective channel length.

This memory cell solves this scaling problem by inserting a select transistor 401 into the memory cell 400. According to this memory cell, punch-through of the memory transistor 402 in the program mode is removed, so that the channel length 51
One can be scaled. Due to this scalability, the channel length 511 can be shortened, so that the programming speed of the memory cell can be remarkably improved as compared with the related art. Further, by doping the drain 407, the memory cell 400
Can sufficiently achieve the program performance at 5V.

(First Embodiment) FIG. 1 is a partial cross-sectional view of a nonvolatile semiconductor memory device manufactured by a first embodiment of a method of manufacturing a nonvolatile semiconductor memory device according to the present invention. A main surface of a silicon substrate 10 as an example of a semiconductor substrate has a first region 11 in which a memory cell 15 as an example of a storage element is formed and a second region 11 in which a select gate transistor 17 is formed.
Area 13. On the first region 11, a silicon oxide film 12, which is an example of a tunnel insulating film,
On the silicon oxide film 12, a floating gate 8
8. On the floating gate 88, an ONO film 16 which is an example of a dielectric film, and on the ONO film 16, a control gate 84 is formed. On the control gate 84, a silicon oxide film 76 (thickness: 80 to 200 nm), which is an example of a mask film, is formed. First
In the region 11 of the source / drain, the source / drain is spaced apart so as to sandwich the control gate 84 and the floating gate 88.
Drains 96 and 97 are formed.

A gate oxide film 20 which is an example of a gate insulating film is formed on the second region 13, and a gate electrode 82 is formed on the gate oxide film 20. Gate electrode 82
A silicon oxide film 76 (200 to 300 n thick)
m) is formed. In the second region 13, the source / drain 9 is spaced apart so as to sandwich the gate electrode 82.
9, 100 are formed.

Floating gate 88 and gate electrode 8
On the main surface of the silicon substrate 10 between the two, there is a groove 90 unavoidably formed. N to cover the groove 90
⁺ Type regions 94 and 98 are formed, and N ⁺ type regions 94 and N ⁺
The mold region 98 is formed so as to overlap with the groove 90. N ⁺ type region 94 is formed deeper in silicon substrate 10 than N ⁺ type region 98. The source / drain 97 is formed by the N ⁺ -type regions 94 and 98 on the first region 11 side. N ⁺ -type region 98 on the second region 13 side
Constitute the source / drain 99. The impurity region constituted by the N ⁺ type region 94 and the N ⁺ type region 98 has a higher concentration than the source / drain 96, 99, 100.

A silicon oxide film 44 is formed on the main surface of silicon substrate 10 so as to cover memory cell 15 and select gate transistor 17. Silicon oxide film 4
4, a contact hole 46a exposing the source / drain 96 and a contact hole 46b exposing the source / drain 100 are formed. On the silicon oxide film 44, aluminum wirings 48a and 48b are formed. Aluminum wiring 48a is in contact hole 4
6a, and is electrically connected to the source / drain 96. Similarly, an aluminum interconnection 48b is also formed in the contact hole 46b, and the source / drain 1
00 and is electrically connected.

FIG. 2 is a plan view of the nonvolatile semiconductor memory device at a portion 400A in FIG. 5, and FIG. 1 is a cross-sectional view of FIG. 2 taken along the line AA. The control gate 37 and the aluminum wiring 4 are spaced apart in the vertical direction.
8a, a control gate 84, a trench 90, a gate electrode 82, and an aluminum wiring 48b are formed. The control gate 84 and the gate electrode 82 correspond to the control gate 404 and the gate 401A shown in FIG. 5, respectively.

Next, a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention will be described. As shown in FIG. 6, a silicon oxide film 12 serving as a tunnel insulating film having a thickness of 7 to 10 nm is formed on the main surface of the silicon substrate 10 by, for example, a thermal oxidation method. On the silicon oxide film 12, a polysilicon film 14 having a thickness of 100 to 200 nm, which is an example of a first conductor film, is formed by, for example, a CVD method.

As shown in FIG. 7, the polysilicon film 14 on the second region 13 is formed by, for example, photo etching.
Is selectively removed by etching. And the first area 1
ONO so as to cover the polysilicon film 14 on
The film 16 is formed on the main surface of the silicon substrate 10. ON
The O film portion of the O film 16 is formed by, for example, a CVD method or a thermal oxidation method, and the N film portion is formed by, for example, a CVD method.

As shown in FIG. 8, a resist 18 is formed on the main surface of the silicon substrate 10. Then, the resist 18 on the second region 13 is removed. By using the resist 18 as a mask, the ONO film 16 and the silicon oxide film 12 on the second region 13 are removed by etching.
0 main surface is exposed. As shown in FIG. 9, a thickness of 5 to 20 is formed on the second region 13 by, for example, a thermal oxidation method.
A gate oxide film 20 of nm is formed.

As shown in FIG. 10, a polysilicon film 24 having a thickness of 200 to 400 nm, which is an example of the second conductor film, is formed on the entire main surface of the silicon substrate 10 by using, for example, the CVD method. As another example of the second conductor film, a polysilicon film having a thickness of 80 to 200 nm and WSi ₂ and MoS having a thickness of 80 to 200 nm formed thereon are provided.
There is a laminated structure of silicide made of i ₂ , CoSi ₂ , TiSi ₂ or the like. On the polysilicon film 24, for example, C
A silicon oxide film 76 having a thickness of 200 to 300 nm is formed by using the VD method. This silicon oxide film 76 is an example of a mask film. A resist 80 is formed on the silicon oxide film 76. The resist 80 is a second resist. Then, the resist 80 is patterned into a pattern of a control gate and a gate electrode.

As shown in FIG. 11, using the resist 80 as a mask, the silicon oxide film 76 and the polysilicon film 24 are formed.
Are sequentially removed by etching to form a control gate 84 and a gate electrode 82 at the same time. Then, the resist 80 is removed.

As shown in FIG. 12, a resist 86 is formed on the main surface of the silicon substrate 10. Resist 86
Is patterned into a pattern covering the gate electrode 82. This resist 86 is the first resist.

As shown in FIG. 13, the ONO film 16 is selectively removed by etching using the silicon oxide film 76 and the resist 86 on the control gate 84 as a mask.
The ONO film 16 located below the control gate 84 is left. By selectively removing the ONO film 16 by etching, the silicon oxide film 20 on the main surface of the silicon substrate 10 between the floating gate and the gate electrode is removed.
Is also etched, and the main surface of the silicon substrate 10 is exposed. Subsequently, the polysilicon film 14 is selectively removed by etching to form a floating gate 88. By this etching, the exposed portion of the main surface of the silicon substrate 10 is also etched, and a groove 90 is formed in the silicon substrate 10. The depth of the groove 90 is 100 to 300 nm.

As described in the step shown in FIG.
Selective etching removal of O film 16 and polysilicon film 1
4 to remove the control gate 84
Is used as a mask.
This etching also removes the silicon oxide film 76.
Therefore, the thickness of the silicon oxide film 76 on the control gate 84 depends on the thickness of the silicon oxide film 7 on the gate electrode 82.
6 smaller than the thickness.

As shown in FIG. 14, a resist 92 is formed on the main surface of the silicon substrate 10. Resist 92
Is the first region 11 where the source / drain 96 is formed.
And the end surface 92a of the control gate 84
Is patterned so as to cover the second region 13 where the source / drain 100 is to be formed and the end face 92 b thereof is located between the gate electrode 82 and the trench 90.

Using the resist 92 as a mask, the main surface of the silicon substrate 10 is covered with 40 to 120 K so as to cover the groove 90.
Phosphorus ions are implanted under the conditions of eV, 1E14 to 6E15 / cm ² . Next, 30-80 KeV, 1E15-6E
Ion implantation of phosphorus or arsenic is performed under the condition of 15 / cm ² . After the ion implantation, the implanted ions are heat-treated and N ⁺
A mold region 94 is formed. The depth of the N ⁺ type region 94 is 20
0 to 600 nm, the impurity concentration is 1E18 to 1E21 /
cm ³ . The conditions of the heat treatment for forming the N ⁺ type region 94 are as follows: atmosphere is N ₂ or N ₂ / O ₂ , and temperature is 900 to 950.
The degree and time are 30 to 180 minutes. By the above-described ion implantation and heat treatment, an N ⁺ type region 94 is formed on the main surface of the silicon substrate 10 so as to cover the groove 90.

As shown in FIG. 15, using the silicon oxide film 76 on the control gate 84 and the silicon oxide film 76 on the gate electrode 82 as a mask, the silicon substrate 1
0 to the main surface, 40 to 120 KeV, 5E12 to 5E1
Phosphorus ions are implanted under the condition of 4 / cm ² . Then 30
The ions of phosphorus or arsenic are implanted under the conditions of 80 KeV and 1E15〜6E15 / cm ² . The source / drain 96, N ⁺
A mold region 98 and a source / drain 100 are formed. N
The depth of the ⁺ type region 98 is 100 to 400 nm, and the impurity concentration is 1E17 to 1E21 / cm ³ .

As shown in FIG. 1, a silicon oxide film 44 serving as an interlayer insulating film is formed on the entire main surface of the silicon substrate 10 by, for example, a CVD method. PSG film, SOG film or BPS instead of silicon oxide film as interlayer insulating film
A G film may be used. PSG film, SOG film or BPS
It may have a single-layer structure using a G film alone, or may have a multilayer structure in which a silicon oxide film, a PSG film, an SOG film, or a BPSG film is combined. Next, using the patterned resist, the silicon oxide film 44 is selectively etched away to form a contact hole 46a exposing the source / drain 96 and a contact hole 46b exposing the source / drain 100. Then, an aluminum film is formed on the silicon oxide film 44 by using, for example, a sputtering method. This aluminum film is patterned to form aluminum wirings 48a and 48b. Instead of the aluminum wiring, an aluminum alloy wiring containing copper or the like in aluminum may be used.

In the first embodiment, as shown in FIG.
Since the control gate 84 and the gate electrode 82 are formed at the same time, it is not necessary to consider a margin for mask alignment between the mask for forming the control gate 84 and the mask for forming the gate electrode 82. For this reason, the distance between the control gate 84 and the gate electrode 82 can be reduced, and miniaturization of the nonvolatile semiconductor memory device can be achieved.

Further, the N ⁺ type regions 94 and 98 of the groove 90 are formed.
Is formed by two ion implantations of the ion implantation described in FIG. 14 and the ion implantation described in FIG. On the other hand, source / drain 9
6, 99 and 100 are formed by the ion implantation described with reference to FIG.
This is performed under the conditions of impurity concentration and depth required for 99 and 100. Therefore, the source / drain 96, 99, and 10 can be formed while lowering the diffusion resistance of the impurity region of the trench 90.
0 can be formed with their required impurity concentration and depth. The control gate 84 and the groove 9
Since the end face 92a of the resist 92 is not located between the control gate and the groove, there is no need to consider a margin for mask alignment between the control gate and the groove, and the distance between the control gate and the groove can be shortened. Therefore, high density and high integration of the nonvolatile semiconductor memory device can be achieved.

(Second Embodiment) A second embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention will be described. As shown in FIG. 16, the polysilicon film 24 is formed in the same manner as in the first embodiment.
Steps up to the formation of Then, a thickness of 200 to 30 is formed on the polysilicon film 24 by using, for example, a CVD method.
A 0 nm silicon oxide film 77 is formed. This silicon oxide film 77 is an example of a mask film. A resist 81 is formed on the silicon oxide film 77, and the resist 81 is patterned. This resist 81 is a third resist. As shown in FIG. 17, first, silicon oxide film 77 is selectively etched away using resist 81 as a mask. As shown in FIG. 18, the resist 81 is removed, and the polysilicon film 24 is
Is selectively removed by etching, and the control gate 10 is removed.
4 and the gate electrode 102 are formed simultaneously.

As shown in FIG. 19, a resist 106 is formed on the main surface of the silicon substrate 10. Then, the resist 106 is patterned into a pattern covering the gate electrode 102. This resist is the first resist. As shown in FIG. 20, using the silicon oxide film 77 on the control gate 104 and the resist 106 as a mask, the ONO
The film 16 and the polysilicon film 14 are selectively etched and removed in this order to form a floating gate 110. First
For the same reason as described in the embodiment, the floating gate 11
A groove 108 is inevitably formed in the main surface of the silicon substrate 10 between 0 and the gate electrode 102.

As described in the step shown in FIG.
Selective etching removal of O film 16 and polysilicon film 1
Control gate 10 for selective etching removal of 4
4 is used as a mask. This etching also removes the silicon oxide film 77. Therefore, the thickness of silicon oxide film 77 on control gate 104 is smaller than the thickness of silicon oxide film 77 on gate electrode 102.

As shown in FIG. 21, a resist 92 is formed on the main surface of silicon substrate 10. The resist 92 covers the first region 11 where the source / drain 96 is formed, and the second surface 13 where the end face 92 a is located above the control gate 104 and where the source / drain 100 is formed. It is patterned so that it covers and its end face 92b is located between the gate electrode 102 and the groove 108. Using the resist 92 as a mask, first ion implantation is performed on the silicon substrate 10 and heat treatment is performed to form an N ⁺ type region 94 that covers the groove 108. The conditions of ion implantation and heat treatment are the same as in the first embodiment.

As shown in FIG. 22, the silicon oxide film 77 on the control gate 104 and the gate electrode 102
Using the silicon oxide film 77 above the mask as a mask, a second ion implantation is performed on the main surface of the silicon substrate 10 and heat treatment is performed to form an N ⁺ type region 98 covering the source / drain 96 and 100 and the groove 108. I do. The conditions for ion implantation are the same as in the first embodiment. N ⁺ -type regions 94 and 98 on the first region 11 side constitute a source / drain 97. The N ⁺ type region 9 on the second region 13 side
8, the source / drain 99 is formed. The following steps are the same as in the first embodiment.

The second embodiment of the present invention has the same effects as the first embodiment, and further has the following effects. As shown in FIG. 18, in the second embodiment, a control gate 104 and a gate electrode 102 are formed using a silicon oxide film 77 as a mask.
Is formed. Therefore, compared with the case where the control gate and the gate electrode are formed using the resist as a mask,
The shapes of the control gate and the gate electrode can be made precise.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a nonvolatile semiconductor memory device manufactured by a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a partial plan view of a nonvolatile semiconductor memory device manufactured according to a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention;

FIG. 3 is a schematic diagram of a memory cell of a flash memory to which a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is applied;

FIG. 4 is a schematic sectional view of a memory cell of a flash memory to which a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is applied;

FIG. 5 is a schematic sectional view of a memory cell array of a flash memory to which a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is applied;

FIG. 6 is a partial cross-sectional view for illustrating a first step of a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 7 is a partial cross-sectional view for illustrating a second step of the first embodiment of the method of manufacturing the nonvolatile semiconductor memory device according to the present invention.

FIG. 8 is a partial cross-sectional view for illustrating a third step of the first embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 9 is a partial cross-sectional view for illustrating a fourth step of the first embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 10 is a partial cross-sectional view for illustrating a fifth step of the first embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 11 is a partial cross sectional view for illustrating a sixth step of the first embodiment of the method for manufacturing the nonvolatile semiconductor memory device according to the present invention.

FIG. 12 is a partial cross-sectional view for illustrating a seventh step of the first embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 13 is a partial cross-sectional view for illustrating an eighth step of the first embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 14 is a partial cross-sectional view for illustrating a ninth step of the first embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 15 is a partial cross-sectional view for illustrating a tenth step of the first embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 16 is a partial cross-sectional view for illustrating a first step of a second embodiment of the method for manufacturing the nonvolatile semiconductor memory device according to the present invention.

FIG. 17 is a partial cross sectional view for illustrating a second step of the second embodiment of the method for manufacturing the nonvolatile semiconductor memory device according to the present invention.

FIG. 18 is a partial cross-sectional view for illustrating a third step of the second embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 19 is a partial cross-sectional view for illustrating a fourth step of the second embodiment of the method for manufacturing the nonvolatile semiconductor memory device according to the present invention.

FIG. 20 is a partial cross-sectional view for illustrating a fifth step of the second embodiment of the method of manufacturing the nonvolatile semiconductor memory device according to the present invention.

FIG. 21 is a partial cross sectional view for illustrating a sixth step of the second embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 22 is a partial cross-sectional view for illustrating a seventh step of the second embodiment of the method of manufacturing the nonvolatile semiconductor memory device according to the present invention.

FIG. 23 is a partial cross-sectional view for describing a first step of an example of a conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 24 is a partial cross-sectional view for describing a second step of the example of the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 25 is a partial cross-sectional view for describing a third step of the example of the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 26 is a partial cross-sectional view for explaining a fourth step of an example of the conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 27 is a partial cross-sectional view for describing a fifth step of an example of the conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 28 is a partial cross-sectional view for describing a sixth step of an example of the conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 29 is a partial cross-sectional view for describing a seventh step of an example of the conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 30 is a partial cross-sectional view for explaining an eighth step of an example of the conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 31 is a partial cross-sectional view for explaining a ninth step of an example of the conventional method for manufacturing a nonvolatile semiconductor memory device.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 11 first region 12 tunnel oxide film 13 second region 14, 24 polysilicon film 15 memory cell 16 ONO film 17 select gate transistor 20 gate oxide film 37, 84, 104 control gate 80, 81, 86, 106 resist 88,110 floating gate 96,97,99,100 source / drain

Claims (15)

[Claims] A semiconductor substrate having a main surface including a first region and a second region; a floating gate formed on the first region; and a control gate formed on the floating gate. And a selection gate transistor including a gate electrode formed on the second region and selectively operating the storage element. Forming a tunnel insulating film on the first region, forming a first conductive film serving as the floating gate on the tunnel insulating film, and forming a first conductive film on the first conductive film. Forming a dielectric film; forming a gate insulating film on the second region; forming a second conductive film on the dielectric film and the gate insulating film. The etching rate is different from that of the first conductive film on the second conductive film. When selectively removing the first conductive film by etching, a mask film serving as a mask is formed. Forming, and selectively removing the mask film and the second conductor film by etching to form the control gate and the gate electrode at the same time. Forming a first resist so as to cover the gate electrode; and forming the first conductive film using the mask film and the first resist on the control gate as a mask. Forming a floating gate by selectively removing a body film by etching. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 2. The method according to claim 1, wherein, from the step of forming the mask film, the step of simultaneously forming the control gate and the gate electrode includes the steps of: forming a second resist on the mask film; Selectively etching and removing the mask film and the second conductor film using a second resist as a mask to simultaneously form the control gate and the gate electrode. . 3. The method according to claim 1, wherein, from the step of forming the mask film, the step of simultaneously forming the control gate and the gate electrode includes the steps of: forming a third resist on the mask film; Selectively etching and removing the mask film using a third resist as a mask; and selectively etching and removing the second conductor film using the mask film as a mask to simultaneously remove the control gate and the gate electrode. Forming a non-volatile semiconductor storage device. 4. The method according to claim 1, wherein the mask film includes an insulating film. 5. The method according to claim 4, wherein the mask film includes a silicon oxide film. 6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein said mask film has a thickness of 200 to 300 nm. 7. The nonvolatile semiconductor memory according to claim 1, wherein there are a plurality of said memory elements and said plurality of select gate transistors, and one select gate transistor selectively operates only one said memory element. Device manufacturing method. 8. A nonvolatile semiconductor memory device which stores information by accumulating electric charges, comprising: a semiconductor substrate having a main surface including a first region and a second region; A storage element including a formed floating gate and a control gate formed on the floating gate; and a select gate transistor including a gate electrode formed on the second region and selectively operating the storage element. A first film having the same width as the control gate, having a different etching rate from the floating gate, and being located on the control gate, and having the same width as the gate electrode; And a second film including the same material as above and located on the gate electrode. 9. The method according to claim 8, wherein the thickness of the first film is smaller than the thickness of the second film.
Non-volatile semiconductor storage device. 10. The storage element according to claim 8, wherein the storage element includes a first source / drain formed in the first region and the first source / drain sandwiching the floating gate and the control gate. / The second region formed in the first region at an interval from the drain
Wherein the select gate transistor has a third source / drain formed in the second region and an interval between the third source / drain so as to sandwich the gate electrode. A fourth source / drain formed in the second region,
A groove is inevitably formed on the main surface between the floating gate and the gate electrode; and the nonvolatile semiconductor memory device is further formed on the main surface so as to cover the groove. A non-volatile semiconductor memory device, further comprising an impurity region electrically connecting the second source / drain and the third source / drain. 11. The nonvolatile semiconductor memory device according to claim 10, wherein said impurity region has a higher impurity concentration than said first and fourth source / drain. 12. The nonvolatile semiconductor memory device according to claim 8, wherein said first and second films include an insulating film. 13. The nonvolatile semiconductor memory device according to claim 12, wherein said first and second films include a silicon oxide film. 14. The nonvolatile semiconductor memory device according to claim 8, wherein said first film has a thickness of 80 to 200 nm, and said second film has a thickness of 200 to 300 nm. 15. The nonvolatile semiconductor memory according to claim 8, wherein there are a plurality of said storage elements and said plurality of select gate transistors, and one of said select gate transistors selectively operates only one of said storage elements. apparatus.