JPH11330001A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent Cu from diffusing from a Cu embedding wiring layer or a Cu plug by providing plural barrier layers between a first layer which is constituted of a first material and a second layer constituted of a second material and by making elements excepting the elements, which constitute the first and the second material, to mix with the barrier layers. SOLUTION: One of first layers 2, 3 and 4 which are constituted of a first material or second layers 5, 6 and 7 constituted of a second material, is formed by Cu or metal including Cu and barrier layers 8, 9 and 10 are formed between the first layers 2, 3 and 4 and the second layers 5, 6 and 7 respectively. Elements excepting the elements which constitute the first and the second material are made to mix with these barrier layers 8, 9 and 10. That is, a compound is generated by reacting the elements, which constitute the first and the second material diffused into each barrier layer 8, 9 and 10 from a semiconductor active region and so on and the elements which are mixed with each of the barrier layers 8, 9 and 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same.
MP (Chemical Mechanical Po)
The present invention relates to a semiconductor device characterized by a barrier layer configuration for improving electromigration resistance of a plug and a buried wiring layer buried in a concave portion by a lithography method, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as an interconnect layer of a semiconductor device, an interconnect layer mainly made of an Al alloy has been used. Therefore, the use of Cu, which has lower resistance than Al and excellent electromigration resistance, has been studied.

In the case of forming such a fine wiring layer using Cu, in a dry etching method required for fine processing, there is an appropriate gas for etching Cu with a high selectivity to an insulating film serving as a base. For this reason, forming a buried plug and a buried wiring layer structure by a damascene method has become mainstream.

In the damascene method, a trench for a wiring layer or a contact hole, that is, a concave portion such as a via hole is provided in an insulating film, and an electrolytic plating method or a Cu (hfa
c) After depositing a thick Cu layer by a CVD method using TMVS or the like, the Cu layer deposited in a region other than the concave portion is removed by a CMP method, and the Cu buried wiring layer or Cu embedded in the concave portion is removed. This is a technique for forming a plug, and is attracting attention as a technique capable of forming a uniform wiring with a size of submicron or less.

[0005] Here, referring to FIGS.
Explains a manufacturing process of a semiconductor device using an embedded wiring process.
You. First, by selectively oxidizing the n-type silicon substrate 41, as shown in FIG.
To form an element isolation oxide film 42,
Some element formation regions surrounded by the film 42 may have p-type impurities such as B
The p-type well region 43 is formed by selectively introducing
The gate oxide film 44 and the gate made of polycrystalline Si
After the electrode 45 is formed, the side of the gate electrode 45 is
O_TwoForming a sidewall 46 made of a film,
Using the element isolation oxide film 42 and the gate electrode 45 as a mask
N-type impurities such as P (phosphorus) are selectively introduced to
After forming the source region 47 and the n-type drain region 48,
Interlayer insulation by PCVD (plasma chemical vapor deposition)
Thick SiO to be the edge film 49 _TwoDeposit the film.

Next, after the surface of the interlayer insulating film 49 is planarized by polishing using a CMP method, reactive ion etching (not shown) is performed using a predetermined resist mask (not shown) as a mask. RIE), the n-type source region 4
7. Via holes 50, 51, 52 for the n-type drain region 48 and the gate electrode 45 are formed. For simplicity of illustration, the via holes 50, 51, 52 are shown as being arranged in a straight line, but are actually formed at different positions from each other.

[0007] Next, after a TiN film 53 serving as a barrier metal is deposited on the entire surface by sputtering, a thick Cu plating layer 54 is deposited by electrolytic plating.

Then, polishing is performed by CMP until the surface of the interlayer insulating film 49 is exposed, and the Cu plating layer 54 and the TiN film 53 deposited in regions other than the via holes 50, 51, and 52 are polished.
Is removed to form Cu plugs 55, 56, 57.

[0009] Referring to FIG. 8 (e), an SiO ₂ film serving as an interlayer insulating film 58 is deposited again by the PCVD method, and reactive ion etching is performed using a predetermined resist mask (not shown) as a mask. By forming, a wiring layer groove 59 for forming a wiring layer electrically contacting the Cu plugs 55, 56, 57 is formed, and then a TiN film 60 to be a barrier metal is deposited on the entire surface by a sputtering method. . Since the via holes 50, 51, and 52 are actually formed at different positions from each other, in the drawing, the wiring layer groove for the wiring layer connected to the Cu plug 56 with respect to the n-type drain region 48 is shown. 59, the Cu plug 5
The wiring layer grooves for 5, 57 are also formed at other positions at the same time.

[0010] Next, after a thick Cu plating layer is deposited by electrolytic plating, polishing is performed by CMP until the surface of the interlayer insulating film 58 is exposed. After removing the Cu plating layer and the TiN film 60 deposited in the region other than
A Cu embedded wiring layer 61 connected to the u plug 56 is formed. Although not shown, the Cu plug 55,
A Cu buried wiring layer for 57 is also formed.

[0011] If necessary, such a process is performed on the upper wiring layer and the Cu plug for making a connection with the upper wiring layer, thereby forming a multilayer wiring structure using the Cu embedded wiring layer. doing.

[0012]

However, such Cu
The history of the buried wiring layer is short and there are many problems that have not been revealed yet. For example, since Cu has a large diffusion coefficient in Si and SiO ₂ , TiN which has been used as a barrier metal for the conventional Al wiring layer has been used. In the film, Si or S
There is a problem that diffusion of Cu into the iO ₂ film cannot be prevented.

For example, when Cu diffuses from a Cu plug into Si, ie, a source region or a drain region,
This causes deterioration of device characteristics such as an increase in leakage current and the like.
When u diffuses into Si or the SiO ₂ film constituting the interlayer insulating film, voids are formed in the Cu plug and the Cu embedded wiring layer, and the Cu plug and the Cu embedded wiring layer are deteriorated. There is a problem that the life of the embedded wiring layer is shortened.

Therefore, an object of the present invention is to improve the device characteristics and the reliability of the wiring layer structure by preventing the diffusion of Cu from the Cu buried wiring layer or the Cu plug.

[0015]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. Refer to FIG. 1. (1) The present invention provides a barrier layer 8, 9, 9 between a first layer made of a first material and second layers 5, 6, 7 made of a second material. In the semiconductor device having a multilayer structure provided with the first and second barrier layers 8, 9, and 10, the first material and the second
Characterized in that elements other than the elements constituting the material are mixed.

As described above, by mixing elements other than the elements constituting the first material and the second material into the barrier layers 8, 9, and 10, the first layers 2, 3, 4 or the second Layers 5, 6, 7, that is, the first material and the second material diffused from the semiconductor active region, the semiconductor diffusion wiring layer, the semiconductor wiring layer, the metal wiring layer, the metal plug, etc. to the barrier layers 8, 9, 10 Reacts with the elements mixed in the barrier layers 8, 9, and 10 to generate a compound, so that the elements forming the first material and the second material are prevented from further diffusing. Therefore, it is possible to prevent the deterioration of the element characteristics or the shortening of the wiring life.

(2) Further, according to the present invention, in the above (1), the elements to be mixed into the barrier layers 8, 9, 10 are environmental impurities in the barrier layers 8, 9, 10 and the first material and the second material.
Standard product energy delta _f H ° at the time of forming the element as a compound constituting the material _1, at 298 ℃, Δ _f H °
It is an element of ₁ ≦ −600 kJ / mol.

As described above, the diffusion due to the formation of a stable compound
In order to reduce the environmental impact, environmental barriers in the barrier layers 8, 9, 10
Pure, eg, oxygen, nitrogen, or carbon, and first
To form a compound with the elements constituting the second material and the second material
The standard energy of formation Δ _fH °₁At 298 ° C
And Δ_fH °₁≤-600 kJ / mol element
Is desirable.

[0019] (3) Regarding the above (2), the standard energy of formation Δ _f H ° _1, the barrier layer 8,
9, 10 and the first layers 2, 3, 4 or the second layers 5, 6,
Standard product energy delta _f H in generating compound and 7
° _2, characterized in that it has a relationship _{Δ f H ° 1 «Δ f H} ° 2.

As described above, in order to suppress diffusion by forming a compound, the barrier layers 8, 9, 10 and the first layer 2,
Since 3,4 or necessary to be more stable than the compounds produced by the second layer 5, 6 and 7, if a standard formation energy in generating the compound was delta _f H ° _2, it is desirable to have a relation of _{Δ f H ° 1 «Δ f H} ° 2.

(4) Further, according to the present invention, in any one of the above (1) to (3), the first material constituting the first layers 2, 3, 4 and the second layers 5, 6, 7, wherein at least one of the second materials constituting Cu 7 is Cu or a metal containing Cu.

The diffusion phenomenon of the elements constituting the first layers 2, 3, 4 or the second layers 5, 6, 7 is caused by the first layer 2, 3, 4, or the second layer 5, 6, 7 is Cu or Cu
This is remarkable when it is composed of a metal containing.

(5) In the present invention, in any one of the above (1) to (4), at least one of the barrier layers 8, 9, 10 may be made of a metal made of Ti, Ta or W, , Ta, or W nitride or Ti,
It is characterized by being either Ta or W obtained by adding Si to a nitride of W.

As described above, the barrier layers 8, 9, and 10 are made of a metal made of Ti, Ta, or W, Ti, T
a or a nitride of W, for example, TiN or T
i, Ta, or nitride of W added with Si,
For example, a Si-containing TiN film, that is, a TiSiN film is preferable, and by including Si, the crystal grain size of the TiN film is reduced to a nano-size, thereby improving the barrier resistance.
In addition, for the embedded wiring layer provided on the interlayer insulating film, T
A metal made of i, Ta, or W may be used.

(6) Further, according to the present invention, in any one of the above (1) to (5), the element to be mixed into the barrier layers 8, 9, 10 is As, Mo, Fe or S It is characterized by containing at least one element.

The diffusion of Cu is grain boundary diffusion along the crystal grain boundaries of the barrier layers 8, 9, and 10, for example, the TiN film (if necessary, LC Park and KBK).
im, Journal of Electrochem
Ial Society, vol. 142, p. 31
09, 1995), an element which easily forms a compound with Cu is contained in the barrier layers 8, 9, and 10 particularly at the grain boundaries, thereby forming a stable compound at the grain boundaries and suppressing diffusion. The diffusion of Cu can be suppressed by mixing an element that easily forms a compound with Cu into the barrier layers 8, 9, and 10.

[0027] Since the standard energy of formation Δ _f H ° ₁ there is the lower the reaction likely to occur at the time of forming a compound with Cu (see supra), as an element to be incorporated into the barrier layer 8, 9, 10, As , Mo, Fe, or by using any of S, the standard formation energy Δ _f H ° ₁ in forming the compound of the Cu, at 298 ° C., the _{Δ f H ° 1 ≦ -600kJ /} mol can do.

Here, oxygen, which is an environmental impurity, and A
The standard generation energy Δ _f H ° ₁ at 298 ° C. when generating a Cu compound of each element of s, Mo, Fe, and S,
Binding, compound phase, and, indicating standard formation energy Δ _f H ° ₁ at 298 ° C. The (kJ / mol) in this order, binding compound phase standard formation energy _{Δ f H ° 1 CuO Cu 2} O - 168.6 CuO _{- 157.3 Cu-As Cu 3 As} - 11.715 Cu 3 AsO 4 - 624.041 Cu 3 (AsO 4) 2 -1522.558 Cu-Mo CuMoO 4 - 911.694 CuFe CuFe 2 O 4 - 96.7.968 Cu-S Cu ₂ OSO ₄ -927.593 (if necessary, DR Li
ed etc., CRC Handbook of Chem
istry and Physics, 74the
d. , Chap. 5, "Data of heat o
f formation for Cu compou
nds ", CRC Press, BocaRaton,
FL, 1993; A. Brandes, Smit
cellsMetals Reference Boo
k, 6th ed. , Chap. 8, Butterwo
rth, London, 1983, and Ihsan
Barin, Thermochemical Dat
a of Pure Substances, VCH
Publisher, New York, 1989).

Therefore, only oxygen and copper, which are environmental impurities, have a high standard formation energy and therefore do not cause much compounding reaction. However, when As, Mo, Fe or S is added, the standard formation energy is low. , Cu ₃ AsO
₄ , Cu ₃ (AsO ₄ ) ₂ , CuMoO ₄ , CuFe ₂
Compounds such as O ₄ and Cu ₂ OSO ₄ are generated and the grain boundaries are filled with the compounds, so that the diffusion of Cu is suppressed.

(7) According to the present invention, in the method for manufacturing a semiconductor device according to any one of the above (1) to (6), an element to be mixed into the barrier layers 8, 9, and 10 is mixed by an ion implantation method. It is characterized by making it.

[0031] Thus, when of mixing element to form a standard formation energy Δ _f H ° ₁ low compound to the barrier layer 8, 9, 10, it is desirable to use an ion implantation method.

(8) Further, according to the present invention, in the method for manufacturing a semiconductor device according to any one of the above (1) to (6), the element to be mixed with the barrier layers 8, 9 and 10 may be a target serving as a sputtering source. Alternatively, it is characterized in that it is previously mixed into the evaporation source.

[0033] Thus, when of mixing low element having a standard formation energy Δ _f H ° ₁ to the barrier layer 8, 9, 10, forming a barrier layer 8, 9, 10 by sputtering or vapor deposition In this step, it is desirable that the element is previously mixed into a target serving as a sputtering source or a vapor deposition source.

(9) Further, according to the present invention, in the method for manufacturing a semiconductor device according to any one of the above (1) to (6), in the step of depositing the barrier layers 8, 9, and 10,
An element to be mixed in the barrier layers 8, 9, 10 is deposited on the surfaces of the barrier layers 8, 9, 10 or in the barrier layers 8, 9, 10 by a sputtering method or an evaporation method.

[0035] Thus, when of mixing low element having a standard formation energy Δ _f H ° ₁ to the barrier layer 8, 9, 10, forming a barrier layer 8, 9, 10 by sputtering or vapor deposition In this step, the elements may be deposited on the surfaces of the barrier layers 8, 9, and 10 by a sputtering method or a vapor deposition method, or may be deposited in the barrier layers 8, 9, and 10 in a sandwich manner.

(10) Further, according to the present invention, in the method for manufacturing a semiconductor device according to any one of the above (1) to (6), an element to be mixed with the barrier layers 8, 9, 10 is added to the barrier layers 8, 9, 10. , 10 are mixed in a step of forming a film by a chemical vapor deposition method.

[0037] Thus, when of mixing elements to form a compound having a low standard generation energy Δ _f H ° ₁ to the barrier layer 8, 9, 10, chemical vapor deposition of the barrier layer 8, 9, 10 In the step of forming a film by the CVD method, the element may be mixed into the barrier layers 8, 9, and 10 by mixing the element into a deposition atmosphere.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIGS.
Next, the first embodiment of the present invention will be described.
FIG. 3 is an explanatory diagram of a manufacturing process according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a first embodiment of the present invention.
FIG. Referring to FIG. 2A, first, similarly to a conventional manufacturing process, an n-type silicon substrate 11 is formed.
Is selectively oxidized to form an isolation oxide film 12.
After the formation, a part of the device surrounded by the device isolation oxide film 12 is formed.
A p-type impurity such as B is selectively introduced into the formation region to form a p-type impurity.
An L region 13 is formed, and then a gate oxide film 14 and
After forming the gate electrode 15 made of polycrystalline Si,
SiO 2 on the side of the gate electrode 15_TwoSide war consisting of membrane
Then, a device isolation oxide film 12 and a gate
P is selectively introduced using the gate electrode 15 as a mask to form an n-type
Source region 17 and n-type drain region 18 were formed.
That is, the thickness which becomes the interlayer insulating film 19 by the PCVD method is as follows.
For example, 0.8 μm SiO _TwoDeposit the film.

Next, after the surface of the interlayer insulating film 19 is flattened by polishing using a CMP method, C ₄ F _{8 is} formed using a predetermined resist mask (not shown) as a mask.
By performing reactive ion etching using a mixed gas of + CO + Ar, n-type source regions 17 and n
Via holes 20, 21, 22 for the mold drain region 18 and the gate electrode 15 are formed. For simplicity of illustration, also in this case, the via holes 20, 2
Although 1 and 22 are shown as being arranged in a straight line, they are actually formed at different positions.

Next, a barrier metal is formed by sputtering.
A TiN film 23 is deposited on the entire surface to a thickness of, for example, 50 nm.
After that, the As ions 24 are accelerated by 30 keV energy.
1.0 × 10¹³~ 1.0 × 10^Fifteencm^-2, Example
For example, 3 × 10 ¹⁴cm^-2Ion implantation under the conditions of
For example, by performing a heat treatment at 400 ° C. for 30 minutes.
Then, As ions 24 are mixed into the TiN film 23.

Next, referring to FIG. 2C, a Cu layer 25 having a thickness of, for example, 1.5 μm on the interlayer insulating film 19 is deposited by sputtering.

Then, polishing is performed by CMP until the surface of the interlayer insulating film 19 is exposed, and the Cu layer 25 and the TiN film 23 deposited in regions other than the via holes 20, 21, 22 are removed. Thus, Cu plugs 26, 27 and 28 are formed.

Referring again to FIG. 3E, a SiO ₂ film having a thickness of, for example, 0.8 μm to become the interlayer insulating film 29 is deposited again by the PCVD method, and then a predetermined resist mask (not shown) is used. Cu) by performing reactive ion etching using
After forming a wiring layer groove 30 for forming a wiring layer that is in electrical contact with the plugs 26, 27, and 28, a TiN film 31 serving as a barrier metal is deposited on the entire surface by a sputtering method. As ions 32, 30
With an acceleration energy of keV, 1.0 × 10 ^{13 to} 1.0 ×
As ions are implanted under conditions of 10 ¹⁵ cm ^-2 , for example, 3 × 10 ¹⁴ cm ^-2 , and a heat treatment is performed, for example, at 400 ° C. for 30 minutes to mix As ions 32 into the TiN film 31. In this case as well, actually, the via hole 2
Since 0, 21 and 22 are formed at different positions from each other, in the figure, the wiring layer groove 3 for the wiring layer connected to the Cu plug 27 with respect to the n-type drain region 18 is shown.
Although 0 is shown, the groove for the wiring layer for the Cu plugs 26 and 28 is also formed at other positions at the same time. Also,
Actually, a SiN film of about 50 nm is deposited as an etching stopper layer under the thick SiO ₂ film which becomes the interlayer insulating film 28.

Next, as shown in FIG.
After depositing a 1.5 μm Cu layer, polishing is performed by a CMP method until the surface of the interlayer insulating film 29 is exposed,
Cu layer and TiN deposited in areas other than wiring layer groove 30
The film 23 is removed, and a Cu embedded wiring layer 33 connected to the Cu plug 27 is formed. Although not shown, a Cu embedded wiring layer for the Cu plugs 26 and 28 is also formed at the same time.

By performing such a process on the upper wiring layer and the Cu plug for making a connection with the upper wiring layer as required, a multilayer wiring structure with a Cu embedded wiring layer is formed. doing.

FIG. 4 is a graph showing the effect of the embodiment of the present invention.
n for p-type region⁺N forming a mold region⁺On / p diode
, A 50 nm TiN film is deposited, and after As ion implantation
Next, a 200 nm Cu film and a 50 nm TiN film are sequentially deposited.
To form an electrode having a TiN / Cu / TiN structure,
After an annealing treatment at 700 ° C. for 30 minutes,
When a reverse bias of 2.5 V is applied to the diode,
Leakage current is measured and the leakage current is
This is shown as a distribution. As is clear from the figure,
When As ions are implanted, compared to when not implanted
Leakage current is reduced, especially when the injection amount is 1 × 10¹⁴cm^-2
Or 1 × 10^Fifteencm ^-2Leak current is 1 × 10
^-9A, and the cumulative probability without ion implantation is 9
About 1 × 10 at 9%^-6Large leak current compared to A
To be reduced.

Therefore, in the first embodiment of the present invention, As is mixed in the TiN film 23,
Even if Cu diffuses from the Cu plugs 26 and 27 during the operation of the device, Cu ₃ AsO ₄ , Cu
A compound such as ₃ (AsO ₄ ) ₂ is generated, and this compound fills the crystal grain boundaries of the TiN film 23, thereby suppressing Cu diffusion.

Since the periphery of the Cu buried wiring layer 33 which is in contact with the SiO ₂ film is covered with the TiN film 31 mixed with As, Cu of the Cu buried wiring layer 33 diffuses into the SiO ₂ film. Therefore, the Cu buried wiring layer 33
Since no void is generated in the wiring layer, the life of the wiring layer is not reduced.

Next, a manufacturing process according to the second embodiment of the present invention will be described with reference to FIGS. Referring to FIG. 5A, first, similarly to the first embodiment, the element isolation oxide film 12 is formed by selectively oxidizing the n-type silicon substrate 11, and then surrounded by the element isolation oxide film 12. A p-type impurity such as B is selectively introduced into a part of the element formation region to form a p-type well region 13, and then a gate oxide film 14 and a gate electrode 15 made of polycrystalline Si are formed. A side wall 16 made of a SiO ₂ film is formed on the side of the gate electrode 15, and then an element isolation oxide film 12 is formed.
After the P type is selectively introduced using the gate electrode 15 as a mask to form the n-type source region 17 and the n-type drain region 18, the thickness to become the interlayer insulating film 19 by the PCVD method is, for example, 0.8 μm. A SiO ₂ film is deposited.

Next, the surface of the interlayer insulating film 19 is planarized by polishing using a CMP method, and then C ₄ F _{8 is} formed using a predetermined resist mask (not shown) as a mask.
By performing reactive ion etching using a mixed gas of + CO + Ar, n-type source regions 17 and n
Via holes 20, 21, 22 for the mold drain region 18 and the gate electrode 15 are formed. For simplicity of illustration, also in this case, the via holes 20, 2
Although 1 and 22 are shown as being arranged in a straight line, they are actually formed at different positions.

Next, as shown in FIG. 5 (b), Mo is added to 0.05 to 2.0%, for example, 1.0%.
Mo-containing TiN film 34 serving as a barrier metal by sputtering using a Ti target containing
Is deposited on the entire surface to a thickness of, for example, 50 nm.

Next, a Cu layer 25 having a thickness of, for example, 1.5 μm on the interlayer insulating film 19 is deposited by the same sputtering method.

Next, polishing is performed by CMP until the surface of the interlayer insulating film 19 is exposed, and the Cu layer 25 and the Mo-containing TiN film 3 deposited in regions other than the via holes 20, 21 and 22 are polished.
4 to form Cu plugs 26, 27 and 28.

Next, an SiO ₂ film having a thickness of, for example, 0.8 μm to become the interlayer insulating film 29 is deposited again by the PCVD method, and then a predetermined resist mask (shown in FIG. Cu) by performing reactive ion etching using
A wiring layer groove 30 for forming a wiring layer that is in electrical contact with the plugs 26, 27, 28 is formed, and then again
T containing 0.05 to 2.0% of Mo, for example, 1.0%
By sputtering using an i target, a Mo-containing TiN film 35 serving as a barrier metal is deposited on the entire surface. Also in this case, the via holes 20, 21 and 22 are actually formed at different positions from each other. Therefore, in the drawing, the via holes 20, 21 and 22 are provided for the wiring layer connected to the Cu plug 27 for the n-type drain region 18. The wiring layer groove 30 is shown, but the wiring layer groove for the Cu plugs 26 and 28 is also formed at another position at the same time. Actually, an SiN film of about 50 nm is deposited as an etching stopper layer under a thick SiO ₂ film serving as the interlayer insulating film 28.

Next, a Cu layer having a thickness of, for example, 1.5 μm is deposited again by the sputtering method, and then polished by the CMP method until the surface of the interlayer insulating film 29 is exposed. And the Cu layer and M deposited in the region other than the wiring layer groove 30
By removing the o-containing TiN film 35, a Cu buried wiring layer 33 connected to the Cu plug 27 is formed. In this case,
Although not shown, a Cu embedded wiring layer for the Cu plugs 26 and 28 is also formed at the same time.

By performing such a process on the upper wiring layer and the Cu plug for making a connection with the upper wiring layer as required, a multilayer wiring structure with a Cu embedded wiring layer is formed. doing.

As described above, in the second embodiment of the present invention, the Mo-containing TiN film 33 is used as the barrier film, so that the Cu plugs 26 and 27 move from the Cu plugs 26 and 27 during operation of the device.
Is diffused, the Cu-containing TiN film 34
oO ₄ is generated, and this compound is used as the Mo-containing TiN film 34.
By filling the crystal grain boundaries, the diffusion of Cu can be suppressed.

Since the periphery of the Cu buried wiring layer 33 which is in contact with the SiO ₂ film is covered with the Mo-containing TiN film 35, the Cu of the Cu buried wiring layer 33 does not diffuse into the SiO ₂ film. Therefore, no void is generated in the Cu embedded wiring layer 33, so that the life of the wiring layer is not reduced.

The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible. For example, as the barrier metal, a TaN film or a WN film may be used instead of the TiN film, or a TiN film or a TaN film may be used.
The film or the WN film may contain Si. By including Si, the crystal grain size of the barrier film is reduced to nano size, and Cu diffusion along grain boundaries is effectively suppressed. can do.

The barrier film may be a Ti film, a Ta film, or a W film. When the barrier film is provided on Si, the formation of silicide with Ti, Ta, and W becomes a problem. Since there is no problem in the portion in contact with the SiO ₂ film, it can be used as a barrier film for the upper wiring layer.

In the description of each of the above embodiments, the element contained in the TiN film is As or Mo.
Is used, but Fe or S which forms a compound having a small standard generation energy like As or Mo may be used.

In the description of each of the above embodiments, when As or Mo is contained, the ion implantation method or the sputtering method is used.
An OCVD method (metal organic chemical vapor deposition method) may be used. In the case of using an evaporation method, an element which forms a compound having a small standard generation energy may be contained in an evaporation source. When the method is used, an element which forms a compound having a small standard generation energy may be contained in the growth atmosphere.

In the description of each of the above embodiments, the element for forming a compound having a small standard generation energy is contained in the sputtering source and mixed in the entire TiN film. It may be mixed in a TiN film in a sandwich manner.
When a film is formed by a sputtering method or an evaporation method, an element which forms a compound having a small standard generation energy may be sputtered or evaporated alone.

In the description of each of the above embodiments, the Cu layer is deposited by the sputtering method. However, the Cu layer is not limited to the sputtering method, but may be formed by the electrolytic plating method, the electroless plating method, or the Cu ( hfac) TMV
It may be deposited by MOCVD using S. When the Cu layer is deposited by the electrolytic plating method, a Cu seed film serving as a seed in the electrolytic plating step is deposited to a thickness of, for example, 200 nm by a sputtering method before depositing the Cu layer. It is desirable to use a conductive film.

In the description of each of the above embodiments, the SiO ₂ film formed by the PCVD method at a low temperature is used as the interlayer insulating film in consideration of the influence on the Cu plug and the Cu embedded wiring layer. That is, although the LTO film is used,
It is not limited to the TO film, but may be FSG (fluorine-containing S
iO ₂ film), a SOG inorganic containing hydrogen HSQ,
Alternatively, a low dielectric constant film such as an organic insulating film may be used. By using such a low dielectric constant film,
The parasitic capacitance between the wiring layers can be reduced, so that a delay in operation speed can be prevented.

In the description of each of the above embodiments, pure Cu is used for the Cu plug and the Cu embedded wiring layer as the interlayer insulating film. However, the present invention is not limited to pure Cu. , Cu doped with other elements of Cu
A metal containing Cu as a main component, such as an alloy, may be used.

In the description of each of the above embodiments, the Cu plug and the Cu layer of the first layer connected to the Cu plug are described.
Although the embedded wiring layer is formed in a separate step, a wiring layer groove is also formed in the via hole forming step, and a Cu plug and a first Cu embedded wiring layer connected to the Cu plug are formed simultaneously. May be.

In the description of each of the above embodiments, an IGFET (insulated gate type FE) is used as a semiconductor element.
T) is described as an example, but as is clear from the example of the diode in FIG. 4, the present invention is also applied to other semiconductor elements such as a bipolar transistor.

[0069]

According to the present invention, the Cu buried wiring layer and the C
When forming the u plug, the barrier film contains an element such as As which forms a compound having a small standard generation energy, so that diffusion of Cu can be suppressed by generating a compound with Cu. As a result, it is possible to reduce the deterioration of the operating characteristics of the element or the life of the wiring layer, and to improve the reliability of a high-speed and high-integration semiconductor integrated circuit device using low-resistance Cu as the wiring layer. Can be.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the first embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of an effect in the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a manufacturing process partway through a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process of the second embodiment of the present invention after FIG. 5;

FIG. 7 is an explanatory diagram of a manufacturing process of a conventional semiconductor device halfway.

FIG. 8 is an explanatory diagram of a manufacturing process of the conventional semiconductor device after FIG. 7;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 first layer 3 first layer 4 first layer 5 second layer 6 second layer 7 second layer 8 barrier layer 9 barrier layer 10 barrier layer 11 n-type silicon substrate 12 element isolation Oxide film 13 p-type well region 14 gate oxide film 15 gate electrode 16 sidewall 17 n-type source region 18 n-type drain region 19 interlayer insulating film 20 via hole 21 via hole 22 via hole 23 TiN film 24 As ions 25 Cu layer 26 Cu plug 27 Cu plug 28 Cu plug 29 Second interlayer insulating film 30 Wiring layer groove 31 TiN film 32 As ion 33 Cu embedded wiring layer 34 Mo-containing TiN film 35 Mo-containing TiN film 41 n-type silicon substrate 42 element isolation oxide film 43 p Well region 44 gate oxide film 45 gate electrode 46 sidewall 47 n-type Region 48 n-type drain region 49 interlayer insulating film 50 via hole 51 via hole 52 via hole 53 TiN film 54 Cu plating layer 55 Cu plug 56 Cu plug 57 Cu plug 58 second interlayer insulating film 59 groove for wiring layer 60 TiN film 61 Cu filling Embedded wiring layer

Claims (10)

[Claims] A first layer made of a first material and a second layer made of a first material;
In a semiconductor device having a multi-layer structure in which a barrier layer is provided between a second layer and a second layer made of a material, elements other than the elements constituting the first material and the second material are mixed in the barrier layer. A semiconductor device comprising: Wherein element to be mixed into the barrier layer, the standard energy of formation delta _f H ° at the time of forming the element as a compound constituting the environmental impurity and the first and second materials of the barrier layer ₁ at 298 ° C., Δ _f H ° ₁
2. The semiconductor device according to claim 1, wherein the element is ≦ −600 kJ / mol. 3. The standard energy of formation Δ_fH °₁When,
A compound formed between the barrier layer and the first layer or the second layer;
The standard energy of formation Δ_fH ° _TwoIs Δ_fH °₁≪Δ_fH °_Two 3. The semiconductor according to claim 2, wherein:
apparatus. 4. At least one of the first material forming the first layer and the second material forming the second layer is made of Cu
Or a metal containing Cu.
The semiconductor device according to any one of claims 3 to 3. 5. The method according to claim 1, wherein at least one of the barrier layers comprises T
a metal comprising i, Ta, or W; a nitride of Ti, Ta, or W; or a nitride of Ti, Ta, or W to which Si is added; Item 5. The semiconductor device according to any one of Items 1 to 4. 6. The element mixed with the barrier layer is A
6. The semiconductor device according to claim 1, comprising at least one element of s, Mo, Fe, or S.
13. The semiconductor device according to item 9. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the element to be mixed into the barrier layer is mixed by an ion implantation method. . 8. The method for manufacturing a semiconductor device according to claim 1, wherein the element to be mixed in the barrier layer is mixed in a target serving as a sputtering source or a vapor deposition source in advance. A method for manufacturing a semiconductor device, comprising: 9. The method for manufacturing a semiconductor device according to claim 1, wherein, in the step of depositing the barrier layer, an element mixed in the barrier layer is
A method for manufacturing a semiconductor device, comprising: depositing on the surface of the barrier layer or in the barrier layer by a sputtering method or an evaporation method. 10. The method for manufacturing a semiconductor device according to claim 1, wherein the element to be mixed in the barrier layer is mixed in the step of forming the barrier layer by a chemical vapor deposition method. A method of manufacturing a semiconductor device.