JPH11327491A - Display device, and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device in which power consumption is reduced and occurrence of animation pseudo contour is reduced or prevented, and its driving method. SOLUTION: Each field is divided into temporally a light emitting period and a pulse blanking period, and each light emitting period is divided into temporally plural sub-fields. In a pulse blanking period, a pulse is not applied to a scan electrode 12 and a sustain-electrode 13, and voltage of the scan electrode 12 and the sustain-electrode 13 is held at the prescribed level. In non-light emitting periods set in each field, as at least voltage of a second electrode is held at the prescribed level or potential difference between the first electrode and the second electrode is held constant, a charge/discharge current is reduced. Therefore, power consumption of the display device is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a display device for displaying an image by controlling discharge and a driving method thereof.

[0002]

2. Description of the Related Art PDP (Plasma Display Panel)
Is advantageous in that it can be made thinner and have a larger screen. In this plasma display device, an image is displayed by utilizing light emission at the time of gas discharge.

FIG. 14 is a view for explaining a method of driving a discharge cell in an AC type PDP. As shown in FIG. 14, in an AC-type PDP discharge cell, the surfaces of opposing electrodes 301 and 302 have dielectric layers 303 and 30 respectively.
4 is covered.

[0004] As shown in FIG.
When a voltage lower than the discharge starting voltage is applied during 302, no discharge occurs. As shown in FIG.
When a pulse-like voltage (writing pulse) higher than the discharge start voltage is applied between the electrodes 301 and 302, a discharge occurs. When the discharge occurs, the negative charge proceeds toward the electrode 301 and is accumulated on the wall surface of the dielectric layer 303, and the positive charge proceeds toward the electrode 302 and is accumulated on the wall surface of the dielectric layer 304. The charges accumulated on the wall surfaces of the dielectric layers 303 and 304 are called wall charges. The voltage induced by the wall charges is called a wall voltage.

[0005] As shown in FIG.
Negative wall charges are accumulated on the wall of the first layer, and positive wall charges are accumulated on the wall of the dielectric layer 302. In this case, since the polarity of the wall voltage is opposite to the polarity of the externally applied voltage, the effective voltage in the discharge space decreases as the discharge proceeds,
The discharge stops automatically.

As shown in FIG. 14D, when the polarity of the externally applied voltage is reversed, the polarity of the wall voltage becomes the same direction as the polarity of the externally applied voltage, so that the effective voltage in the discharge space increases. If the effective voltage at this time exceeds the discharge starting voltage, a discharge of the opposite polarity occurs. As a result, the positive charge advances toward the electrode 301, neutralizes the negative wall charge already accumulated in the dielectric layer 303, and the negative charge
To neutralize the positive wall charges already accumulated in the dielectric layer 304.

Then, as shown in FIG. 14E, positive and negative wall charges are accumulated on the wall surfaces of the dielectric layers 303 and 304, respectively. In this case, since the polarity of the wall voltage is opposite to the polarity of the externally applied voltage, the effective voltage in the discharge space decreases as the discharge proceeds, and the discharge stops.

Further, as shown in FIG. 14 (f), when the polarity of the externally applied voltage is reversed, a discharge of the opposite polarity is generated, the negative charge proceeds in the direction of the electrode 301, and the positive charge becomes the electrode 3
It proceeds in the direction of 02 and returns to the state of FIG.

As described above, once the discharge is started by applying a write pulse higher than the discharge start voltage, the polarity of the externally applied voltage (sustain pulse) lower than the discharge start voltage is changed by the action of the wall charge. By inverting the discharge, the discharge can be maintained. Starting discharge by applying a write pulse is referred to as address discharge, and sustaining discharge by applying alternately inverted sustain pulses is referred to as sustain discharge.

[0010] As shown in FIG.
By applying an erasing pulse having a polarity opposite to the wall voltage between 302, the wall charges accumulated on the wall surfaces of the dielectric layers 303 and 304 are extinguished, and the discharge can be terminated. The pulse width of the erasing pulse is set narrow so that residual wall charges can be canceled and wall charges of the opposite polarity cannot be newly stored. Once the wall charge disappears, FIG.
As shown in FIG. 4H, no discharge occurs even when the next sustain pulse is applied.

FIG. 15 is a schematic diagram mainly showing the structure of a PDP (plasma display panel) of a conventional plasma display device.

As shown in FIG. 15, a PDP 1 has a plurality of address electrodes 11 and a plurality of scan electrodes (scan electrodes) 1.
2 and a plurality of sustain electrodes (sustain electrodes) 13. The plurality of address electrodes 11 are arranged in the vertical direction of the screen, and the plurality of scan electrodes 12 and the plurality of sustain electrodes 13 are arranged in the horizontal direction of the screen. The plurality of sustain electrodes 13 are commonly connected.

A discharge cell is formed at each intersection of the address electrode 11, the scan electrode 12, and the sustain electrode 13. Each discharge cell forms a pixel on the screen.

The address driver 2 drives a plurality of address electrodes 11 according to image data. The scan driver 3 drives the plurality of scan electrodes 12 in order. The sustain driver 4 drives the plurality of sustain electrodes 13 in common.

FIG. 16 is a schematic sectional view of a three-electrode surface discharge cell in an AC type PDP. Discharge cell 1 shown in FIG.
In 00, a pair of scan electrode 12 and sustain electrode 13 are formed in a horizontal direction on surface glass substrate 101, and these scan electrode 12 and sustain electrode 13 are covered with transparent dielectric layer 102 and protective layer 103. I have. On the other hand, an address electrode 11 is formed in a vertical direction on a back glass substrate 104 facing the front glass substrate 101, and a transparent dielectric layer 10 is formed on the address electrode 11.
5 are formed. A phosphor 106 is applied on the transparent dielectric layer 105.

In the discharge cell 100, the address electrode 1
A period in which an address discharge is generated between the address electrode 11 and the scan electrode 12 by applying a write pulse between the scan electrode 12 and the scan electrode 12 and then alternately inverted between the scan electrode 12 and the sustain electrode 13 By applying an appropriate sustain pulse, a sustain discharge is generated between scan electrode 12 and sustain electrode 13.

As a gradation display driving method in the AC type PDP, an ADS (Address and Display Period Separate) is used.
d; address / display period separation) method.
FIG. 17 is a diagram for explaining the ADS method. FIG.
The vertical axis indicates the scanning direction (vertical scanning direction) of the scan electrodes from the first line to the m-th line, and the horizontal axis indicates time.

In the ADS system, one field (1/60)
(Seconds = 16.67 ms) is temporally divided into a plurality of subfields. For example, when performing 256 gradation display with 8 bits, one field is divided into eight subfields. Each subfield is divided into an address period in which an address discharge for selecting a lighting cell is performed and a sustain period in which a sustain discharge for display is performed.

In the example of FIG. 17, one field is temporally divided into four subfields SF1, SF2, SF3 and SF4. The subfield SF1 is divided into an address period AD1 and a sustain period SUS1, the subfield SF2 is divided into an address period AD2 and a sustain period SUS2, and the subfield SF3 is divided into an address period AD
3 and a sustain period SUS3.
F4 is divided into an address period AD4 and a sustain period SUS4.

In the ADS system, the first in each subfield
Scanning by address discharge is performed on the entire surface of the PDP from the line to the m-th line, and a sustain discharge is performed when the address discharge on the entire surface is completed. That is, the sustain period is set to a period excluding the address period. Therefore, the ratio of the sustaining period in one field is as small as about 30%, and there is a limit to increasing the luminance.

In order to increase the brightness of the PDP,
Address and sustain simultaneous drive method (IEICE: TECHNI
CAL REPORT OF IEICE.EID96-71, ED96-149, SDM96-175 (19
97-01) and PP.19-24) have been proposed. FIG. 18 is a diagram for explaining the address / sustain simultaneous driving method. The vertical axis in FIG. 18 indicates the scanning direction (vertical scanning direction) of the scan electrodes from the first line to the m-th line, and the horizontal axis indicates time.

In the address / sustain simultaneous driving method,
The sustain discharge is started after the address discharge for each line. In the example of FIG. 18, one field is temporally divided into four subfields SF1, SF2, SF3, and SF4, and each of the subfields SF1 to SF4 has an address period AD1 to AD4 and a sustain period SUS1 to SUS4, respectively.
And

In each of the subfields SF1 to SF4, sustain periods SUS1 to SUS4 are set for each line, following the address periods AD1 to AD4. Therefore, almost all of one field is a sustain period, and high luminance can be achieved.

FIG. 19 is a timing chart showing the drive voltage of each electrode in the conventional simultaneous address and sustain drive method. FIG. 19 shows drive voltages for the sustain electrode 13, the scan electrode 12 and the address electrode 11 on the nth to (n + 3) th lines. Where n
Is any integer.

In FIG. 19, a sustain pulse Psu is applied to the sustain electrode 13 at a constant cycle.
During the address period, a write pulse Pw is applied to the scan electrode 12. A write pulse Pwa is applied to the address electrode 11 in synchronization with the write pulse Pw. Write pulse Pw applied to address electrode 11
ON / OFF of a is controlled according to each pixel of the image to be displayed. When the write pulse Pw and the write pulse Pwa are applied simultaneously, an address discharge occurs at a discharge cell at the intersection of the scan electrode 12 and the address electrode 11, and the discharge cell is turned on.

In the sustain period after the address period, a sustain pulse Psc is applied to the scan electrode 12 at a constant cycle.
The phase of the sustain pulse Psc applied to the scan electrode 12 is the same as that of the sustain pulse Psc applied to the sustain electrode 13.
The phase is shifted by 180 degrees with respect to the phase of su. In this case, the sustain discharge occurs only in the discharge cells lit by the address discharge.

At the end of each subfield, an erase pulse Pe is applied to the scan electrode 12. Thereby,
The wall charge of each discharge cell disappears, and the sustain discharge ends. After application of the erasing pulse Pe, before the start of the next subfield, the pause pulse Pr is applied to the scan electrode 12 at a constant period.
Is applied. A period from the application of the erasing pulse Pe to the start of the next subfield is called a pause period.

[0028]

In the above-described conventional address / sustain simultaneous driving method, almost all of one field is a sustain period, so that high luminance can be achieved. However, as shown in FIG. 18, since the luminance of the display image is represented by time-dividing one field into a plurality of subfields and superimposing those subfields, it takes a while until the luminance of each pixel is determined. The light emission time becomes longer. As a result, a phenomenon called a moving image pseudo contour in which a ring of the moving image appears to be double occurs.

As shown in FIG. 19, the sustain pulse Psu is always applied to the sustain electrode 13 at a constant cycle, and the sustain pulse Psc or the pause pulse Pr is applied to the scan electrode 12 at a constant cycle. The power consumption increases due to the charging / discharging current at the electrode 13 and the scan electrode 12.

An object of the present invention is to provide a display device with reduced power consumption and reduced or prevented occurrence of a pseudo-moving interval of a moving image, and a driving method thereof.

[0031]

(1) First invention A display device according to a first invention has a plurality of discharge cells having at least first and second electrodes and a plurality of discharge cells set in each discharge cell. Dividing means for temporally dividing a field into a light emitting period and a non-light emitting period; and periodically applying a first pulse voltage to a first electrode of the discharge cell during a light emitting period set for each discharge cell by the dividing means. A first voltage application means for applying the voltage, and a second pulse voltage is periodically applied to a second electrode of the discharge cell during a light emission period set for each discharge cell by the division means. During the non-emission period set in the cell, the second
And a second voltage applying means for maintaining the voltage of the electrodes at a predetermined level.

In the display device according to the present invention, each field set in each discharge cell is temporally divided into a light emitting period and a non-light emitting period. During the light emission period, a first pulse voltage is periodically applied to the first electrode of the discharge cell, and a second pulse voltage is periodically applied to the second electrode of the discharge cell. Thereby, sustain discharge is performed between the first electrode and the second electrode. During the non-emission period, the voltage of the second electrode of the discharge cell is maintained at a predetermined level. Thereby, the charge / discharge current at the second electrode is reduced.

As described above, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, the generation of the moving pseudo ring interval is reduced or prevented. Further, the charge / discharge current of the second electrode is reduced in the non-light emission period set in each field, so that the power consumption of the display device is reduced.

(2) Second Invention In the display device according to the second invention, in the configuration of the display device according to the first invention, the first voltage applying means is set to each discharge cell by the dividing means. In the non-light emitting period, the voltage of the first electrode of the discharge cell is maintained at a predetermined level.

In this case, since the voltage of the first electrode of the discharge cell is maintained at a predetermined level during the non-emission period set in each field, the charge / discharge current at the first electrode is reduced, The power consumption of the display device is further reduced.

(3) Third Invention A display device according to a third invention is characterized in that a plurality of discharge cells having at least first and second electrodes and each field set in each discharge cell is determined by a light emitting period and a non-light emitting period. Dividing means for temporally dividing the light emitting period into a light emitting period;
A first voltage applying means for periodically applying the pulse voltage, and a second electrode having a phase different from the first pulse voltage to the second electrode of the discharge cell during a light emission period set for each discharge cell by the dividing means. And a pulse voltage having the same phase as the first pulse voltage is periodically applied to the second electrode of the discharge cell during the non-emission period set for each discharge cell by the dividing means. Second to apply
And voltage applying means.

In the display device according to the present invention, each field set in each discharge cell is temporally divided into a light emitting period and a non-light emitting period. A first pulse voltage is periodically applied to a first electrode of the discharge cell. During the light emission period,
A second pulse voltage having a phase different from the first pulse voltage is periodically applied to a second electrode of the discharge cell. Thereby, sustain discharge is performed between the first electrode and the second electrode. During the non-emission period, the first electrode is applied to the second electrode of the discharge cell.
Are periodically applied. Thereby, the potential difference between the first electrode and the second electrode is kept constant, and the charge and discharge currents at the first and second electrodes are reduced.

As described above, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, the generation of the moving pseudo ring interval is reduced or prevented. In addition, the charge and discharge currents of the first and second electrodes are reduced during the non-emission period set in each field, so that the power consumption of the display device is reduced.

(4) Fourth Invention In the display device according to the fourth invention, in the configuration of the display device according to the first, second or third invention, the dividing means sets the light emission period of each field to a plurality of times. It is time-divided into subfields.

In this case, since the light emission period of each field is temporally divided into a plurality of subfields, gradation display is possible. Further, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, it is possible to obtain an image of a gradation display in which the pseudo ring interval of the moving image is reduced or prevented.

(5) Fifth Invention In the display device according to the fifth invention, in the configuration of the display device according to the fourth invention, the dividing means may include a non-light-emission period between sub-fields in a light-emission period of each field. Further settings are made. In this case, power consumption is further reduced.

(6) Sixth invention A display device according to a sixth invention is the display device according to the fourth or fifth invention, wherein the dividing means comprises:
The non-light emitting period is variably set based on at least one of the number of times of light emission for each gradation, the number of subfields, and the time of one field.

In this case, the non-light emitting period is automatically set for each field based on at least one of the number of gradations, the number of times of light emission per gradation, the number of subfields, and the time of one field. Therefore, even when the number of gradations, the number of times of light emission per gradation, the number of subfields, or the time of one field is changed, power consumption can be reduced.

(7) Seventh Invention In the display device according to the seventh invention, in the configuration of the display device according to any one of the first to sixth inventions, the non-light emitting period is forcibly set at an arbitrary time. And setting means for setting.

In this case, since the non-light emitting period can be set at an arbitrary time, the displayed image can be erased at an arbitrary timing.

(8) Eighth Invention In the display device according to the eighth invention, the plurality of first electrodes arranged in the first direction and the plurality of first electrodes are paired with each other. A plurality of second electrodes arranged in one direction; a plurality of third electrodes arranged in a second direction intersecting the first direction; a plurality of first electrodes; a plurality of second electrodes. A plurality of discharge cells provided at the intersections of the electrodes and the plurality of third electrodes, and each field set for each pair of the first and second electrodes is temporally divided into a light emitting period and a non-light emitting period. Dividing means, first voltage applying means for periodically applying a first pulse voltage to the first electrode during the light emission period set to each first electrode by the dividing means, and each first electrode by the dividing means. The second pulse voltage is periodically applied to the second electrode during the light emission period set for the second electrode. And a second voltage applying means for maintaining the voltage of the second electrode at a predetermined level during the non-emission period set for each second electrode by the dividing means.

In the display device according to the present invention, each discharge cell has a three-electrode structure. Each field set for each pair of the first and second electrodes is temporally divided into a light emitting period and a non-light emitting period. During the light emission period, a first pulse voltage is periodically applied to the first electrode and a second pulse voltage is applied to the second electrode.
The second pulse voltage is periodically applied to the electrodes. Thereby, sustain discharge is performed between the first electrode and the second electrode. During the non-emission period, the voltage of the second electrode is kept at a predetermined level. Thereby, the charge / discharge current at the second electrode is reduced.

As described above, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, the generation of the moving pseudo ring interval is reduced or prevented. Further, the charge / discharge current of the second electrode is reduced in the non-emission period set in each field, so that the power consumption of the display device is reduced.

(9) Ninth Invention A display device according to a ninth invention is the display device according to the eighth invention, wherein the first voltage applying means is set to each first electrode by the dividing means. The voltage of the first electrode is kept at a predetermined level during the non-emission period.

In this case, since the voltage of the first electrode is maintained at a predetermined level during the non-emission period set in each field, the charge / discharge current at the first electrode is reduced, and Power consumption is further reduced.

(10) Tenth Invention A display device according to a tenth invention is a display device, wherein a plurality of first electrodes arranged in a first direction and a plurality of first electrodes are paired with each other. A plurality of second electrodes arranged in one direction; a plurality of third electrodes arranged in a second direction intersecting the first direction; a plurality of first electrodes; a plurality of second electrodes. A plurality of discharge cells provided at the intersections of the electrodes and the plurality of third electrodes, and each field set for each pair of the first and second electrodes is temporally divided into a light emitting period and a non-light emitting period. Dividing means, a first voltage applying means for periodically applying a first pulse voltage to the plurality of first electrodes, and a second voltage applying means for applying the second pulse to each of the second electrodes by the dividing means. A second electrode having a phase different from the first pulse voltage on the electrode;
Pulse voltage is applied periodically, and the second
And a second voltage applying means for periodically applying a pulse voltage having the same phase as the first pulse voltage to the second electrode during a non-emission period set for the electrode.

In the display device according to the present invention, each discharge cell has a three-electrode structure. Each field set for each pair of the first and second electrodes is temporally divided into a light emitting period and a non-light emitting period. A first pulse voltage is periodically applied to the first electrode. In the light emitting period, a second pulse voltage having a phase different from that of the first pulse voltage is periodically applied to the second electrode. Thereby, sustain discharge is performed between the first electrode and the second electrode. In the non-emission period, a pulse voltage having the same phase as the first pulse voltage is periodically applied to the second electrode. Thereby, the first
The potential difference between the first electrode and the second electrode is kept constant, and the charge and discharge currents at the first and second electrodes are reduced.

As described above, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, the generation of the moving pseudo ring interval is reduced or prevented. In addition, the charge and discharge currents of the first and second electrodes are reduced during the non-light emitting period set in each field, so that the power consumption of the display device is reduced.

(11) Eleventh Invention The display device according to the eleventh invention is an eighth, ninth, or first display device.
In the configuration of the display device according to the aspect of the present invention, the dividing means includes:
The light emission period of each field is temporally divided into a plurality of subfields.

In this case, since the light emission period of each field is temporally divided into a plurality of subfields, gradation display is possible. Further, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, it is possible to obtain an image of a gradation display in which the pseudo ring interval of the moving image is reduced or prevented.

(12) Twelfth Invention In the display device according to the twelfth invention, in the configuration of the display device according to any one of the eighth to eleventh inventions, a light emission period set for each second electrode is provided. A third voltage applying means for applying a third pulse voltage for selecting a discharge cell to emit light in accordance with image data in a previous address period to the corresponding third electrode; The means applies a fourth pulse voltage to the second electrode during the address period.

In this case, during the address period before the light emission period,
A third pulse voltage is applied to a third electrode corresponding to a discharge cell to emit light, and a fourth pulse voltage is applied to a corresponding second electrode. Thereby, the third electrode to which the third pulse voltage is applied during the address period and the fourth electrode
Discharge occurs at the discharge cell at the intersection with the second electrode to which the pulse voltage has been applied, and the sustain discharge is performed in the light emitting period after the address period.

(13) Thirteenth Invention A method for driving a display device according to a thirteenth invention is a method for driving a display device provided with a plurality of discharge cells having at least first and second electrodes. Each field set in a discharge cell is temporally divided into a light emitting period and a non-light emitting period, and a first pulse voltage is periodically applied to a first electrode of the discharge cell in a light emitting period set in each discharge cell. And periodically applying a second pulse voltage to the second electrode to maintain the voltage of the second electrode of the discharge cell at a predetermined level during the non-emission period set for each discharge cell. is there.

In the driving method of the display device according to the present invention, each field set in each discharge cell is temporally divided into a light emitting period and a non-light emitting period. During the light emission period, a first pulse voltage is periodically applied to the first electrode of the discharge cell, and a second pulse voltage is periodically applied to the second electrode of the discharge cell. Thereby, sustain discharge is performed between the first electrode and the second electrode. During the non-emission period, the voltage of the second electrode of the discharge cell is maintained at a predetermined level. Thereby, the charge / discharge current at the second electrode is reduced.

As described above, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, the generation of the moving pseudo ring interval is reduced or prevented. Further, the charge / discharge current of the second electrode is reduced in the non-emission period set in each field, so that the power consumption of the display device is reduced.

(14) Fourteenth Invention A method for driving a display device according to a fourteenth invention is directed to the method for driving a display device according to the thirteenth invention, wherein the discharge cell is used in a non-light emitting period set for each discharge cell. Is maintained at a predetermined level.

In this case, since the voltage of the first electrode of the discharge cell is maintained at a predetermined level during the non-emission period set in each field, the charge / discharge current at the first electrode is reduced, The power consumption of the display device is further reduced.

(15) Fifteenth Invention A method for driving a display device according to a fifteenth invention is a method for driving a display device provided with a plurality of discharge cells having at least first and second electrodes. Each field set in a discharge cell is temporally divided into a light emitting period and a non-light emitting period, and a first pulse voltage is periodically applied to a first electrode of each discharge cell, and set in each discharge cell. Periodically applying a second pulse voltage having a phase different from the first pulse voltage to the second electrode of the discharge cell during the light emission period,
In the non-emission period set for each discharge cell, a pulse voltage having the same phase as the first pulse voltage is periodically applied to the second electrode of the discharge cell.

In the driving method of the display device according to the present invention, each field set in each discharge cell is temporally divided into a light emitting period and a non-light emitting period. A first pulse voltage is periodically applied to a first electrode of the discharge cell. In the light emitting period, a second pulse voltage having a phase different from the first pulse voltage is periodically applied to the second electrode of the discharge cell. Thereby, sustain discharge is performed between the first electrode and the second electrode. In the non-emission period, a pulse voltage having the same phase as the first pulse voltage is periodically applied to the second electrode of the discharge cell. Thereby, the first electrode and the second electrode
The potential difference between the first and second electrodes is kept constant.
The charge / discharge current at the electrode is reduced.

As described above, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, the generation of the moving pseudo ring interval is reduced or prevented. In addition, the charge and discharge currents of the first and second electrodes are reduced during the non-light emitting period set in each field, so that the power consumption of the display device is reduced.

(16) Sixteenth Invention A display device driving method according to a sixteenth invention is directed to the display device driving method according to the thirteenth, fourteenth, or fifteenth invention, wherein the light emitting period of each field is set to a plurality of times. It is time-divided into subfields.

In this case, since the light emission period of each field is temporally divided into a plurality of subfields, gradation display is possible. Further, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, it is possible to obtain an image of a gradation display in which the pseudo ring interval of the moving image is reduced or prevented.

(17) Seventeenth Invention In the method for driving a display device according to the seventeenth invention, a plurality of first electrodes arranged in a first direction are paired with a plurality of first electrodes, respectively. A plurality of second electrodes arranged in a first direction, a plurality of third electrodes arranged in a second direction intersecting the first direction, a plurality of first electrodes, a plurality of A method of driving a display device comprising a second electrode and a plurality of discharge cells provided at intersections of a plurality of third electrodes, wherein each of the first and second electrodes is set for each pair. The field is temporally divided into a light emitting period and a non-light emitting period,
A first pulse voltage is periodically applied to the first electrode during a light emission period set for each first electrode, and a second pulse is applied to the second electrode during a light emission period set for each second electrode. Is periodically applied, and the voltage of the second electrode is maintained at a predetermined level during the non-emission period set for each second electrode.

In the display device driving method according to the present invention, each field set for each pair of the first and second electrodes is temporally divided into a light emitting period and a non-light emitting period. In the light emitting period, a first pulse voltage is periodically applied to the first electrode, and a second pulse voltage is periodically applied to the second electrode. Thereby, sustain discharge is performed between the first electrode and the second electrode. During the non-emission period, the voltage of the second electrode is kept at a predetermined level. Thereby, the charge / discharge current at the second electrode is reduced.

As described above, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, the generation of the moving pseudo ring interval is reduced or prevented. In addition, the charge / discharge current of the second electrode is reduced in the non-emission period set in each field, so that the power consumption of the entire display device is reduced.

(18) Eighteenth Invention The display device driving method according to the eighteenth invention is the same as the driving method of the display device according to the seventeenth invention, wherein the display device is driven during the non-light emitting period set for each first electrode. The voltage of the first electrode is maintained at a predetermined level.

In this case, the voltage of the first electrode is maintained at a predetermined level during the non-light emitting period set in each field, so that the charge / discharge current at the first electrode is reduced, and Power consumption is further reduced.

(19) Nineteenth Invention In the display device driving method according to the nineteenth invention, a plurality of first electrodes arranged in a first direction and a plurality of first electrodes are paired. A plurality of second electrodes arranged in a first direction, a plurality of third electrodes arranged in a second direction intersecting the first direction, a plurality of first electrodes, a plurality of A method of driving a display device comprising a second electrode and a plurality of discharge cells provided at intersections of a plurality of third electrodes, wherein each of the first and second electrodes is set for each pair. The field is temporally divided into a light emitting period and a non-light emitting period,
A first pulse voltage is periodically applied to a plurality of first electrodes, and a second pulse having a phase different from the first pulse voltage is applied to the second electrodes during a light emission period set for each second electrode.
Is periodically applied, and a pulse voltage having the same phase as the first pulse voltage is periodically applied to the second electrode during the non-emission period set for each second electrode. .

In the display device driving method according to the present invention, each field set for each pair of the first and second electrodes is temporally divided into a light emitting period and a non-light emitting period. A first pulse voltage is periodically applied to the first electrode. In the light emitting period, a second pulse voltage having a phase different from that of the first pulse voltage is periodically applied to the second electrode. Thereby, sustain discharge is performed between the first electrode and the second electrode. During the non-light emitting period, the first electrode is applied to the second electrode.
Are periodically applied. Thereby, the potential difference between the first electrode and the second electrode is kept constant, and the charge and discharge currents at the first and second electrodes are reduced.

As described above, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, the generation of the moving pseudo ring interval is reduced or prevented. In addition, since the charge and discharge currents of the first and second electrodes are reduced during the non-emission period set in each field, the power consumption of the entire display device is reduced.

(20) Twentieth invention The driving method of the display device according to the twentieth invention is the same as the driving method of the display device according to the seventeenth, eighteenth, or nineteenth invention, wherein each light emission period is set to a plurality of subfields. In time.

In this case, since the light emission period of each field is temporally divided into a plurality of subfields, gradation display is possible. Further, since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, it is possible to obtain an image of a gradation display in which the pseudo ring interval of the moving image is reduced or prevented.

(21) Twenty-First Invention A display device driving method according to a twenty-first invention is the display device driving method according to any one of the seventeenth to twentieth inventions, wherein the display device is set for each second electrode. A third pulse voltage for selecting a discharge cell to emit light in accordance with image data in an address period before a light emission period is applied to a corresponding third electrode, and a fourth pulse voltage is applied to the second electrode. Are applied to the electrodes.

In this case, during the address period before the light emission period,
A third pulse voltage is applied to a third electrode corresponding to a discharge cell to emit light, and a fourth pulse voltage is applied to a corresponding second electrode. Thereby, the third electrode to which the third pulse voltage is applied during the address period and the fourth electrode
Discharge occurs at the discharge cell at the intersection with the second electrode to which the pulse voltage has been applied, and the sustain discharge is performed in the light emitting period after the address period.

[0080]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a plasma display device will be described as an example of a display device according to the present invention.

FIG. 1 is a block diagram showing the configuration of a plasma display device according to one embodiment of the present invention. In the plasma display device of the present embodiment, a compression driving method described later is used.

The plasma display device shown in FIG.
P (plasma display panel) 1a, address driver 2, scan driver 3, sustain driver 4,
It includes a discharge control timing generation circuit 5, an A / D converter (analog-to-digital converter) 6, a scan number converter 7, and a subfield converter 8.

The video signal VD is input to the A / D converter 6. Further, the discharge control timing generation circuit 5, A /
A horizontal synchronizing signal H and a vertical synchronizing signal V are supplied to the D converter 6, the scan number converter 7, and the subfield converter 8.

The A / D converter 6 converts the video signal VD into digital image data, and gives the image data to the scan number converter 7. The scanning number converter 7 converts the image data into P
The image data is converted into image data of the number of lines corresponding to the number of pixels of DP1a, and the image data of each line is provided to the subfield conversion unit 8. The image data for each line is composed of a plurality of pixel data respectively corresponding to a plurality of pixels of each line. The subfield conversion unit 8 divides each pixel data of the image data for each line into a plurality of bits corresponding to a plurality of subfields, and serially converts each bit of each pixel data to the address driver 2 for each subfield. Output.

The discharge control timing generating circuit 5 generates discharge control timing signals SC and SU based on the horizontal synchronizing signal H and the vertical synchronizing signal V, and supplies them to the scan driver 3 and the sustain driver 4, respectively.

FIG. 2 is a block diagram mainly showing the configuration of PDP 1a of the plasma display device of FIG.

As shown in FIG. 2, PDP 1a includes a plurality of address electrodes (data electrodes) 11, a plurality of scan electrodes (scan electrodes) 12, and a plurality of sustain electrodes (sustain electrodes) 13. The plurality of address electrodes 11 are arranged in the vertical direction of the screen, and the plurality of scan electrodes 12 and the plurality of sustain electrodes 13 are arranged in the horizontal direction of the screen. The plurality of sustain electrodes 13 are separated from each other for each line.

A discharge cell is formed at each intersection of the address electrode 11, the scan electrode 12, and the sustain electrode 13,
Each discharge cell forms a pixel on the screen.

The address driver 2 is connected to the power supply circuit 21. The address driver 2 converts data serially provided for each subfield from the subfield converter 8 of FIG. 1 into parallel data, and drives a plurality of address electrodes 11 based on the parallel data.

The scan driver 3 includes an output circuit 3a and a shift register 3b. The sustain driver 4 includes an output circuit 4a and a shift register 4b. These scan driver 3 and sustain driver 4
Are connected to a common power supply circuit 22.

Shift register 3b of scan driver 3
Supplies the discharge control timing signal SC supplied from the discharge control timing generation circuit 5 of FIG. 1 to the output circuit 3a while shifting in the vertical scanning direction. The output circuit 3a outputs a discharge control timing signal SC supplied from the shift register 3b.
, The plurality of scan electrodes 12 are sequentially driven.

Shift register 4 of sustain driver 4
b shifts the discharge control timing signal SU given from the discharge control timing generation circuit 5 of FIG. 1 in the vertical scanning direction to the output circuit 4a. The output circuit 4a outputs a discharge control timing signal S supplied from the shift register 4b.
The plurality of sustain electrodes 13 are sequentially driven in response to U.

In this embodiment, the sustain driver 4 and the discharge control timing generation circuit 5 correspond to first voltage applying means, and the scan driver 3 and the discharge control timing generation circuit 5 correspond to second voltage applying means. Also,
The address driver 2 corresponds to a third voltage applying unit, the discharge control timing generating circuit 5 and the subfield conversion unit 8 correspond to a dividing unit, and the discharge control timing generating circuit 5 corresponds to a setting unit. Furthermore, the sustain electrode 13
Corresponds to the first electrode, the scan electrode 12 corresponds to the second electrode, and the address electrode 11 corresponds to the third electrode.

FIG. 3 is a diagram for explaining a compression drive system used in the plasma display device of FIG. The vertical axis in FIG. 3 indicates the scanning direction (vertical scanning direction) of the scan electrodes from the first line to the m-th line, and the horizontal axis indicates time.

In the compression driving method, one field is temporally divided into a light emitting period and a pulse blanking period (non-light emitting period), and the light emitting period is temporally divided into a plurality of subfields. In this compression drive system, as in the address / sustain simultaneous drive system, sustain discharge is started for each line following address discharge.

In this embodiment, the light emission period is temporally divided into four subfields SF1, SF2, SF3, SF4, and each subfield SF1 to SF4 has an address period AD1 to AD4 and a sustain period SUS1 to SUS4, respectively.
And

In each of the subfields SF1 to SF4, sustain periods SUS1 to SUS4 are set after the address periods AD1 to AD4 for each line. Further, a pulse blanking period is set for each line following the light emission period.

FIG. 4 is a timing chart showing a driving voltage applied to each electrode of the PDP 1a during the light emitting period. In FIG. 4, the address electrode 11, the sustain electrode 13
Also, the driving voltages of the scan electrodes 12 on the nth to (n + 2) th lines are shown. Here, n is an arbitrary integer.

As shown in FIG. 4, during the light emitting period, a sustain pulse Psu is applied to the sustain electrode 13 at a constant period. During the address period, a write pulse Pw is applied to the scan electrode 12. This write pulse Pw
, A write pulse Pwa is applied to the address electrode 11. ON / OFF of the write pulse Pwa applied to the address electrode 11 is controlled according to each pixel of the image to be displayed. Write pulse Pw and write pulse P
When wa is applied at the same time, an address discharge is generated in the discharge cell at the intersection of the scan electrode 12 and the address electrode 11, and the discharge cell is turned on.

In the sustain period after the address period, sustain pulse Psc is applied to scan electrode 12 at a constant period.
The phase of the sustain pulse Psc applied to the scan electrode 12 is the same as that of the sustain pulse Psc applied to the sustain electrode 13.
It is shifted by 180 degrees from the phase of sc. In this case, the sustain discharge occurs only in the discharge cells lit by the address discharge.

At the end of each subfield, an erase pulse Pe is applied to the scan electrode 12. Thereby,
The wall charge of each discharge cell is reduced to the extent that disappearance or sustain discharge does not occur, and the sustain discharge ends. In the pause period after the application of the erase pulse Pe, the pause pulse Pr is applied to the scan electrode 12 at a constant period. This pause pulse Pr has the same phase as the sustain pulse Psu.

The write pulse Pwa applied to the address electrode 11 changes between 0V and 175V. Also,
Sustain pulse Ps applied to sustain electrode 13
u varies between 185V and 0V. Write pulse Pw applied to each scan electrode 12, sustain pulse Ps
c and the pause pulse Pr change between 185V and 0V, and the erase pulse Pe changes between 0V and 185V.

FIG. 5 is a timing chart showing the driving voltage applied to the sustain electrode and the scan electrode in the last subfield of the light emission period and the pulse blanking period.

As shown in FIG. 5, the pulse blanking period is set after the pause period of the last subfield SF4 of the light emission period. During the pulse blanking period, the sustain pulse Psu is not applied to the sustain electrode 13, and the voltage of the sustain electrode 13 is maintained at a predetermined level (0 V in this embodiment). Further, in the pulse blanking period, the pause pulse Pr is not applied to the scan electrode 12, and the voltage of the scan electrode 12 is maintained at a predetermined level (0 V in this embodiment).

As described above, in the plasma display device of the present embodiment, since each field is temporally divided into the light emission period and the pulse blanking period, the light emission period in each field is compressed. The light emission time until the luminance of each pixel is determined is reduced. Therefore, the generation of the moving pseudo ring interval is reduced or prevented.

In the pulse blanking period set in each field, no pulse is applied to scan electrode 12 and sustain electrode 13, and the voltage of scan electrode 12 and sustain electrode 13 is maintained at a constant level. Therefore, the charge / discharge current at scan electrode 12 and sustain electrode 13 is reduced, and the power consumption of the entire plasma display device is reduced.

FIGS. 6 and 7 are block diagrams showing the structure of the main part of discharge control timing generating circuit 5 of FIG.
8 is a waveform diagram showing a basic pulse, a drive voltage of a sustain electrode and a drive voltage of a scan electrode, and FIG. 9 is a waveform diagram showing a light emission period start signal, a light emission period end signal, and a pulse blanking signal.

In FIG. 8, the basic pulse PLS has a half cycle (double frequency) of the sustain pulse Psu applied to the sustain electrode 13 and the sustain pulse Psc applied to the scan electrode 12. Here, the period of the basic pulse PLS is CK.

In FIG. 6, the signal processing unit 31 comprises a display image having the number of gradations, the number of light emission modes, the number of subfields, the time of a pause period of each subfield, the time of a 1V period (one vertical scanning period), and the image mute. Output a signal.

The number of light emission modes is defined as one half of the number of light emission at gradation level 1. If the weighting of a certain subfield is 64 gradations and the number of light emission modes is 3, the number (the number of times of light emission) of the basic pulses PLS included in the sustain period of the subfield is 64 × 3 × 2 = 384.

The number of light emission modes is 2 by the multiplier 33 in FIG.
Is multiplied by the multiplier 32 and the result of the multiplication by the multiplier 33 is multiplied by the multiplier 32. Thus, the number of times of light emission required for the 1 V period (the number of basic pulses PLS in the sustain period) is obtained. For example, when the number of gradations is 256 and the number of light emission modes is 3, the number of times of light emission required in the 1 V period (the number of basic pulses PLS in the sustain period) is 255 × 3 × 2 = 1530.

Next, the time of the idle period is multiplied by 1 / CK by the multiplier 36. Thereby, the number of basic pulses PLS in the idle period is obtained. The number of basic pulses PLS and the number of subfields in the idle period are determined by the multiplier 3
Multiplied by five. Thereby, the number of basic pulses PLS in the idle period within the 1 V period is obtained.

For example, when the number of subfields is 8, the pause period is 120 μs, and the period CK of the basic pulse PLS is 4 μs, the basic pulse P in the pause period within the 1 V period is set.
The number of LSs is 8 × 120/4 = 240.

The number of times of light emission required in the 1V period (the number of basic pulses PLS in the sustain period) and the number of basic pulses PLS in the idle period in the 1V period are added by the adder. As a result, the basic pulse P necessary for the light emission period within the 1V period
The number of LS is determined.

In the above example, the number of basic pulses PLS required for the light emission period within the 1 V period is 240 + 1530 = 17
70.

The number of basic pulses PLS required for the light emitting period within the 1 V period is given to one input terminal of the comparator 37.

From the total number of the basic pulses PLS in the 1V period, the basic pulse P necessary for the light emission period in the above 1V period is calculated.
By subtracting the number of LS, the number of basic pulses PLS in the pulse blanking period is obtained.

In the above example, the time of the 1 V period is set to 16.7.
ms, the number of basic pulses PLS in the pulse blanking period is 16700 / 4-1770 = 240
It becomes 5.

The multiplier 38 calculates 1 / C in the time of the 1V period.
K is multiplied. Thereby, the total number of basic pulses PLS in the 1 V period is obtained. The total number of basic pulses PLS in the 1 V period is provided to one input terminal of the comparator 40.

The counter 39 counts the number of the basic pulses PLS, and supplies the counted value to the other input terminal of the comparator 40 and the other input terminal of the comparator 37.

The comparator 40 compares the count value of the counter 39 with the total number of basic pulses PLS in the 1V period, and compares the basic pulse PLS in the 1V period with the count value.
Is output via the inverter 21 when the total number is equal to the total number, and a reset signal RST is given to the counter 39. Thereby, the counter 39 is reset.

In this way, the inverter 21 outputs 1
Each time the V period starts, a light emission period start signal A shown in FIG. 9 is output. The light emission period start signal A is supplied to the flip-flop 42
As a reset signal RST.

The comparator 37 changes the count value of the counter 39 into the basic pulse PL necessary for the light emission period within the 1 V period.
The light emission period end signal B is output when the count value matches the number of basic pulses PLS necessary for the light emission period within the 1 V period as compared with the number of S.

In this manner, the light emission period end signal B shown in FIG. 9 is output from the comparator 37 every time the light emission period in each 1V period ends. The light emission period end signal B is supplied to the flip-flop 42 as a set signal.

The flip-flop 42 is connected to the inverter 21
Is reset by a light emission period start signal A output from the comparator 37, and is set by a light emission period end signal B output from the comparator 37. Thereby, pulse blanking signal PB shown in FIG. 9 is output from flip-flop 42.

This pulse blanking signal PB is
As shown in the figure, the signal rises to a high level in synchronization with the falling edge of the light emission period start signal A, and falls to a low level in synchronization with the rising edge of the light emission period end signal B. That is, the pulse blanking signal PB is at a high level during the light emission period and is at a low level during the pulse blanking period.

The pulse blanking signal PB output from the flip-flop 42 is supplied to one input terminal of the AND gate 43 in FIG. 6, and the image mute signal D is supplied to the other input terminal. The AND gate 43 outputs a pulse blanking signal PB1.

The pulse blanking signal PB1 is supplied to one input terminal of the AND gate 46 and the OR gate 4 shown in FIG.
7 is provided to one input terminal. The other input terminal of the AND gate 46 is supplied with the write pulse Pw, the sustain pulse Psc, the erase pulse Pe, and the pause pulse Pr output from the scan pulse generation circuit 44. The other input terminal of the OR gate 47 is supplied with a panel selection signal PS.

The output signal of OR gate 47 is applied to one input terminal of AND gate 48. AND gate 48
Is connected to a sustain pulse generating circuit 45.
Are supplied.

The output signal of AND gate 46 is applied to scan driver 3 as discharge control timing signal SC. The output signal of AND gate 48 is provided to sustain driver 4 as discharge control timing signal SU.

When the image mute signal D is at the high level, the pulse blanking signal PB is output from the AND gate 43 as the pulse blanking signal PB1. During the light emission period, the pulse blanking signals PB and PB1 are at a high level. As a result, the write pulse Pw and the sustain pulse P output from the scan pulse generation circuit 44 are output.
The sc, the erase pulse Pe, and the pause pulse Pr are given to the scan driver 3 as a discharge control timing signal SC, and the sustain pulse Psu output from the sustain pulse generation circuit 45 is given to the sustain driver 4 as a discharge control timing signal SU.

In the pulse blanking period, the pulse blanking signals PB and PB1 are at a low level. In this case, the scan driver 3 is supplied with a low-level discharge control timing signal SC, and the sustain driver 4 is supplied with a low-level discharge control timing signal SU.

On the other hand, when the image mute signal D goes low, the pulse blanking signal PB1 also goes low. In this case, the scan driver 3 is supplied with a low-level discharge control timing signal SC, and the sustain driver 4 is supplied with a low-level discharge control timing signal SU.
Is given.

As described above, the write pulse Pw, output from the scan pulse generation circuit 44 during the light emission period,
Sustain pulse Psc, erase pulse Pe and pause pulse P
r is supplied to the scan driver 3 as the discharge control timing signal SC, and the sustain pulse Psu output from the sustain pulse generation circuit 45 is supplied to the sustain driver 4 as the discharge control timing signal SU. During the pulse blanking period, low-level discharge control timing signals SC and SU are supplied to the scan driver 3 and the sustain driver 4, respectively.

Further, by setting the image mute signal D to the low level at an arbitrary timing, the display image can be turned off by the circuit immediately before the PDP 1a. As a result, when a channel is selected or an abnormality occurs in signal processing, the PDP is transmitted using the time lag of the transmission time of the video signal.
It is possible to instantly turn off the display image 1a. In addition, when the PDP 1a is not used, the display image is turned off by the circuit immediately before the PDP 1a, thereby saving power.

When panel select signal PS is at a high level, sustain pulse Psu output from sustain pulse generating circuit 45 is applied to sustain driver 4 as discharge control timing signal SU regardless of the state of pulse blanking signal PB1. .

In this case, the pause pulse Pr is not applied to the scan electrode 12 during the pulse blanking period, and the sustain pulse Psu is applied to the sustain electrode 13.
Therefore, the PDP 1 to which the sustain electrodes 13 shown in FIG. 15 are commonly connected can be used instead of the PDP 1a of FIG.

FIG. 10 is a timing chart showing another example of the driving voltage applied to each electrode of the PDP 1a during the light emitting period.

In the example of FIG. 10, a pulse blanking period is set in a part or all of the rest period following the sustain period of each subfield in the light emitting period. That is,
During part or all of the rest period, no pulse is applied to the scan electrode 12 and the sustain electrode 13, and the voltage of the scan electrode 12 and the sustain electrode 13 is maintained at a predetermined level (0 V in this example).

As a result, the charge / discharge current at scan electrode 12 and sustain electrode 13 is further reduced, and the power consumption of the plasma display device is further reduced.

FIG. 11 is a block diagram showing another example of the configuration of the main part of the discharge control timing generation circuit 5. In FIG. Also,
FIG. 12 is a signal waveform diagram of each part of the discharge control timing generation circuit 5 of FIG. FIG. 11 shows a portion of the discharge control timing generation circuit 5 corresponding to FIG.

The pulse blanking signal PB1 output from the AND gate 43 shown in FIG. 6 is supplied to one input terminal of the AND gate 51 shown in FIG. AND gate 5
2 is connected to the pulse blanking signal PB
1 inverted signal is input. To the other input terminal of the AND gate 51, a write pulse Pw, a sustain pulse Psc, an erase pulse Pe, and a pause pulse Pr output from the scan pulse generation circuit 44 are given as output signals PSC. The other input terminal of the AND gate 52 is supplied with a sustain pulse Psu output from the sustain pulse generating circuit 45.

The output signal SCO of the AND gate 51 is OR
The signal is supplied to one input terminal of the gate 53. Output signal SC1 of AND gate 52 is applied to the other input terminal of OR gate 53.

The output signal of OR gate 53 is applied to scan driver 3 as discharge control timing signal SC. The output signal of the sustain pulse generation circuit 45 is provided to the sustain driver 4 as a discharge control timing signal SU.

In the light emitting period, the pulse blanking signal P
B1 goes high. Thereby, the AND gate 5
The output signal SC0 of 1 becomes equal to the output signal PSC of the scan pulse generation circuit 44. At this time, the AND gate 5
2 output signal SC1 becomes low level. Thereby,
The output signal of the OR gate 53 is the scan pulse generation circuit 4
4 output signal PSC. Therefore, the write pulse Pw, the sustain pulse Psc, the erase pulse Pe, and the pause pulse Pr are given to the scan driver 3 as the discharge control timing signal SC.

During the pulse blanking period, the pulse blanking signal PB1 goes to a low level. Thereby,
The output signal SC0 of the AND gate 51 goes low. The output signal SC1 of the AND gate 52 is equal to the output signal of the sustain pulse generating circuit 45. Accordingly, the output signal of OR gate 53 becomes equal to the output signal of sustain pulse generating circuit 45. Therefore,
A blanking pulse Pb having the same phase as the sustain pulse Psu is supplied to the scan driver 3 as a discharge control timing signal SC.

The sustain driver 4 includes a sustain pulse Ps output from the sustain pulse generating circuit 45.
u is always given.

As described above, in the light emitting period, the write pulse Pw output from the scan pulse generation circuit 44,
Sustain pulse Psc, erase pulse Pe and pause pulse P
r is supplied to the scan driver 3 as the discharge control timing signal SC, and the sustain pulse Psu output from the sustain pulse generation circuit 45 is supplied to the sustain driver 4 as the discharge control timing signal SU. In the pulse blanking period, the sustain pulse Psu output from the sustain pulse generating circuit 45 is used as the discharge control timing signal SU.
And a blanking pulse Pb having the same phase as the sustain pulse Psu is supplied to the scan driver 3 as a discharge control timing signal SC.

FIG. 13 is a timing chart showing drive voltages applied to the sustain electrode and the scan electrode when the discharge control timing generation circuit 5 of FIG. 11 is used.

As shown in FIG. 13, the pulse blanking period is set after the pause period of the last subfield SF4 of the light emission period. During the pulse blanking period,
The sustain pulse Psu is periodically applied to the sustain electrode 13, and the sustain pulse Ps is applied to the scan electrode 12.
A blanking pulse Pb having the same phase as u is periodically applied.

As described above, in the example of FIG. 13, in the pulse blanking period set in each field, the drive voltages of scan electrode 12 and sustain electrode 13 have the same phase, and scan electrode 12 and sustain electrode 13 have the same phase.
Is kept constant. Therefore, the charge / discharge current at scan electrode 12 and sustain electrode 13 is reduced, and the power consumption of the entire plasma display device is reduced.

When the discharge control timing generation circuit 5 shown in FIG. 11 is used, the sustain pulse Psu is constantly applied to the sustain electrode 13 at a constant cycle.
Instead of P1a, PDP1 to which sustain electrode 13 shown in FIG. 15 is commonly connected can be used.

[0153]

According to the display device and the method of driving the same according to the present invention, the voltage of at least the second electrode is maintained at a predetermined level during the non-emission period set in each field, or the first electrode is driven. Since the potential difference between the first electrode and the second electrode is kept constant, the charge / discharge current at least in the second electrode is reduced. Therefore, the power consumption of the display device is reduced.

Since the light emission period in each field is compressed, the light emission time until the luminance of each pixel is determined is reduced. Therefore, the generation of the moving pseudo ring interval is reduced or prevented.

In particular, the voltage of the first electrode is kept at a predetermined level or the potential difference between the first electrode and the second electrode is kept constant during the non-light emitting period set in each field. In this case, the charge / discharge current at the first electrode is also reduced, and the power consumption of the display device is further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a plasma display device according to an embodiment of the present invention.

FIG. 2 is a view mainly showing P of the plasma display device of FIG. 1;
Block diagram showing the configuration of the DP

FIG. 3 is a diagram for explaining a compression driving method used in the plasma display device of FIG. 1;

FIG. 4 is a timing chart showing a driving voltage applied to each electrode of the PDP during a light emitting period.

FIG. 5 is a timing chart showing a driving voltage applied to a sustain electrode and a scan electrode in a last subfield of a light emitting period and a pulse blanking period.

FIG. 6 is a block diagram showing a configuration of a main part of the discharge control timing generation circuit of FIG. 1;

FIG. 7 is a block diagram showing a configuration of a main part of the discharge control timing generation circuit of FIG. 1;

FIG. 8 is a waveform chart showing a basic pulse, a drive voltage applied to a sustain electrode, and a drive voltage applied to a scan electrode.

FIG. 9 is a waveform chart showing a light emission period start signal, a light emission period end signal, and a pulse blanking signal.

FIG. 10 is a timing chart showing another example of a driving voltage applied to each electrode of the PDP during a light emitting period.

FIG. 11 is a block diagram showing another example of the configuration of the main part of the discharge control timing generation circuit.

12 is a signal waveform diagram of each part of the discharge control timing generation circuit of FIG.

13 is a waveform chart showing drive voltages applied to a sustain electrode and a scan electrode when the discharge control timing generation circuit of FIG. 11 is used.

FIG. 14 is a diagram illustrating a method for driving a discharge cell in an AC PDP.

FIG. 15 is a schematic diagram mainly showing a configuration of a PDP of a conventional plasma display device.

FIG. 16 is a schematic sectional view of a three-electrode surface discharge cell in an AC type PDP.

FIG. 17 is a diagram for explaining the ADS method.

FIG. 18 is a diagram for explaining an address 5 sustain simultaneous driving method;

FIG. 19 is a timing chart showing a drive voltage of each electrode according to a conventional simultaneous address and sustain drive method.

[Explanation of symbols]

 1, 1a PDP 2 address driver 3 scan driver 4 sustain driver 5 discharge control timing generation circuit 11 address electrode 12 scan electrode 13 sustain electrode Pw write pulse Pe erase pulse Pr pause pulse Psc sustain pulse Psu sustain pulse SC, SU discharge control timing signal

Continuing from the front page (72) Inventor Kazuo Ohira 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd.

Claims (21)

[Claims] A plurality of discharge cells having at least a first electrode and a second electrode; dividing means for temporally dividing each field set in each discharge cell into a light emitting period and a non-light emitting period; Means for periodically applying a first pulse voltage to the first electrode of the discharge cell during a light emission period set for each discharge cell by the means; and setting for each discharge cell by the dividing means. A second pulse voltage is periodically applied to the second electrode of the discharge cell during the light emission period, and the second pulse voltage of the discharge cell during the non-light emission period set for each discharge cell by the dividing means. A second voltage applying means for maintaining the voltage of the electrodes at a predetermined level. 2. The method according to claim 1, wherein the first voltage application unit maintains the voltage of the first electrode of the discharge cell at a predetermined level during a non-emission period set for each discharge cell by the division unit. The display device according to claim 1. 3. A plurality of discharge cells having at least first and second electrodes; dividing means for temporally dividing each field set in each discharge cell into a light emitting period and a non-light emitting period; A first voltage application unit for periodically applying a first pulse voltage to the first electrode of the cell; and a light emitting period set for each discharge cell by the division unit. A second pulse voltage having a phase different from that of the first pulse voltage is periodically applied to the electrode, and the second electrode of the discharge cell is applied to the second electrode of the discharge cell during a non-emission period set for each discharge cell by the dividing unit. A display device comprising: a second voltage application unit that periodically applies a pulse voltage having the same phase as the first pulse voltage. 4. The display device according to claim 1, wherein the dividing unit temporally divides a light emitting period of each field into a plurality of subfields. 5. The display device according to claim 4, wherein said dividing means further sets a non-light emitting period between subfields in a light emitting period of each field. 6. The method according to claim 1, wherein the dividing unit variably sets the non-light emitting period based on at least one of the number of gradations, the number of light emission per gradation, the number of subfields, and the time of one field. The display device according to claim 4, wherein the display device is a display device. 7. The display device according to claim 1, further comprising a setting unit for forcibly setting the non-light emitting period at an arbitrary time. 8. A plurality of first electrodes arranged in a first direction, and a plurality of second electrodes arranged in the first direction so as to be paired with the plurality of first electrodes, respectively. And a plurality of third electrodes arranged in a second direction intersecting the first direction; and a plurality of third electrodes arranged in a second direction intersecting the first direction. A plurality of discharge cells provided at the intersection; a dividing unit for temporally dividing each field set for each pair of the first and second electrodes into a light emitting period and a non-light emitting period; A first voltage application unit for periodically applying a first pulse voltage to the first electrode during a light emission period set for each first electrode; and a first voltage application unit for setting each second electrode by the division unit. When a second pulse voltage is periodically applied to the second electrode during the light emitting period, A display device comprising: a second voltage applying unit that maintains a voltage of the second electrode at a predetermined level during a non-light emitting period set for each second electrode by the dividing unit. 9. The method according to claim 1, wherein the first voltage applying unit keeps the voltage of the first electrode at a predetermined level during a non-light emitting period set for each first electrode by the dividing unit. Item 10. The display device according to Item 8. 10. A plurality of first electrodes arranged in a first direction, and a plurality of second electrodes arranged in the first direction so as to be paired with the plurality of first electrodes, respectively. And a plurality of third electrodes arranged in a second direction intersecting the first direction; and a plurality of third electrodes arranged in a second direction intersecting the first direction. A plurality of discharge cells provided at the intersections; dividing means for temporally dividing each field set for each pair of the first and second electrodes into a light emitting period and a non-light emitting period; First voltage application means for periodically applying a first pulse voltage to one electrode; and the first pulse to the second electrode during a light emission period set to each second electrode by the division means. Periodically applying a second pulse voltage having the same phase as the voltage, And a second voltage applying means for periodically applying a pulse voltage having the same phase as the first pulse voltage to the second electrode during a non-emission period set for each second electrode. A display device characterized by the above-mentioned. 11. The display device according to claim 8, wherein the division unit temporally divides a light emission period of each field into a plurality of subfields. 12. A third pulse voltage for selecting a discharge cell to emit light in accordance with image data in an address period before an emission period set for each second electrode is applied to a corresponding third electrode. 12. The apparatus according to claim 8, further comprising: a third voltage applying unit configured to apply, wherein the second voltage applying unit applies a fourth pulse voltage to the second electrode during the address period. 13. The display device according to any one of the above. 13. A method of driving a display device having a plurality of discharge cells having at least first and second electrodes, wherein each field set in each discharge cell is divided into a light emitting period and a non-light emitting period. And periodically applying a first pulse voltage to the first electrode of the discharge cell during a light emission period set for each discharge cell, and applying a second pulse voltage to the second electrode of the discharge cell. Apply pulse voltage periodically,
A method of driving a display device, comprising: maintaining a voltage of the second electrode of a discharge cell at a predetermined level during a non-emission period set for each discharge cell. 14. The method according to claim 13, wherein a voltage of the first electrode of the discharge cell is maintained at a predetermined level during a non-light emitting period set for each discharge cell. 15. A method for driving a display device comprising a plurality of discharge cells having at least first and second electrodes, wherein each field set in each discharge cell is divided into a light emitting period and a non-light emitting period. And periodically applying a first pulse voltage to the first electrode of each discharge cell, and applying the first pulse voltage to the second electrode of the discharge cell during a light emission period set for each discharge cell. A second pulse voltage having a phase different from that of the first pulse voltage is periodically applied, and the same as the first pulse voltage is applied to the second electrode of the discharge cell during a non-emission period set for each discharge cell. A method for driving a display device, wherein a pulse voltage having a phase is periodically applied. 16. The method according to claim 13, wherein the light emitting period of each field is temporally divided into a plurality of subfields. 17. A plurality of first electrodes arranged in a first direction, and a plurality of second electrodes arranged in the first direction so as to be paired with the plurality of first electrodes, respectively. A plurality of third electrodes arranged in a second direction intersecting the first direction; the plurality of first electrodes; and the plurality of second electrodes.
And a plurality of discharge cells provided at intersections of the plurality of third electrodes, wherein each field set for each of the first and second electrodes of each pair is provided. Is temporally divided into a light emitting period and a non-light emitting period, a first pulse voltage is periodically applied to the first electrode during the light emitting period set for each first electrode, and each second
A second pulse voltage is periodically applied to the second electrode during a light emission period set for the second electrode, and the voltage of the second electrode is set to a predetermined value during a non-light emission period set for each second electrode. A method for driving a display device, wherein the display device is maintained at a level. 18. The method according to claim 17, wherein a voltage of the first electrode is maintained at a predetermined level during a non-light emitting period set for each first electrode. 19. A plurality of first electrodes arranged in a first direction, and a plurality of second electrodes arranged in the first direction so as to be paired with the plurality of first electrodes, respectively. A plurality of third electrodes arranged in a second direction intersecting the first direction; the plurality of first electrodes; and the plurality of second electrodes.
And a plurality of discharge cells provided at intersections of the plurality of third electrodes, wherein each field set for each of the first and second electrodes of each pair is provided. Is temporally divided into a light emitting period and a non-light emitting period, a first pulse voltage is periodically applied to the plurality of first electrodes, and the first pulse voltage is applied to the light emitting period set in each second electrode. A second pulse voltage having a phase different from that of the first pulse voltage is periodically applied to the second electrode, and the first electrode is applied to the second electrode during a non-emission period set for each second electrode. A method for driving a display device, wherein a pulse voltage having the same phase as a pulse voltage is periodically applied. 20. The method according to claim 17, wherein the light emitting period of each field is temporally divided into a plurality of subfields. 21. A third pulse voltage for selecting a discharge cell to emit light in accordance with image data in an address period before a light emission period set for each second electrode is applied to a corresponding third electrode. 18. The method according to claim 17, further comprising applying a fourth pulse voltage to the second electrode while applying the voltage.
20. The driving method of the display device according to any one of 20.