JPH11326460A - Boundary scan circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a boundary scan circuit by which a test time can be shortened in the case that a part of a substrate, on which plural IC's are loaded, is tested. SOLUTION: In this boundary scan circuit, plural IC's (IC1 to IC4) are combined on the same scan path, and each IC is connected through the same selector 5, and also by changing a connection target over by an internal path of the selector 5, a test data sent in the scan path are enabled to be selectively outputted, optionally to a specific IC on the substrate. Therefore, both the length of the test data and the time required for the test can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a plurality of integrated circuits having a boundary scan circuit section (hereinafter, abbreviated as "IC"), and manufacturing defects of a substrate on which each IC is connected by a scan path. The present invention relates to a boundary scan circuit to be tested.

[0002]

2. Description of the Related Art A boundary scan circuit is known which tests a substrate on which a plurality of ICs are mounted for defective manufacturing by a boundary scan method. As shown in FIG. 6, this type of boundary scan circuit has a circuit board 61 on which a plurality of ICs (IC1 to IC4) and an edge connector 62 for connecting a predetermined tester are arranged. The TDI (TDI is an abbreviation for Test Data Input, hereinafter the same) terminal of the first stage IC1 is connected to the ATDI terminal of the edge connector 62.
C TDO (TDO stands for Test Data Output, same hereafter) terminal is connected to its own TDI terminal, and the final stage IC
The TDO terminal No. 4 is connected to the ATDO terminal of the edge connector 62 to form one scan path.

Each of the IC1 to IC4 has a TDI terminal, a TDO terminal for realizing a boundary scan,
A test access port (hereinafter, TAP) and a plurality of boundary scan cells (hereinafter, BSC) which are 1-bit registers in which test data can be set are provided. The user logic for performing the operation is automatically switched by a control signal (not shown). The two logics are separated from each other in circuit, and the test logic does not affect the user logic. The reverse is also true.

[0006] In the boundary scan circuit 60 shown in FIG. 6, for example, the operation of testing one cell (referred to as a test data set point P) in the IC 3 is as follows. First, test data is input to the scan path from a tester (not shown) connected to the edge connector 62 through the ATDI terminal. This test data is
Via the TDI terminal and TDO terminal of C2, it reaches the TDI terminal of IC3 and is set to BSC. The test data after the test is output from the TDO terminal of IC3 to the ATDO terminal of the edge connector 62 via the TDI terminal and TDO terminal of IC4. The test data in this case is 1 bit for IC1, 1 bit for IC2, and 3 bits for the test data set point P in IC3, for a total of 5 bits.

[0005]

As described above, in the conventional boundary scan circuit, the I
C, for example, when testing IC3, all ICs
Required the same length of test data as when testing In addition, since it is necessary to send test data to the entire scan path that passes through or is equivalent to all of the ICs on the substrate 61, the test time cannot be reduced despite the small test target range. there were.

SUMMARY OF THE INVENTION An object of the present invention is to provide a boundary scan circuit that can reduce the length of test data and the time required for testing.

[0007]

According to the present invention, a plurality of integrated circuits having a boundary scan circuit section are mounted on one substrate, and the integrated circuits are connected in series by a scan path. In the boundary scan circuit, the input and output terminals of all the integrated circuits except the input terminal of the first integrated circuit and the output terminal of the last integrated circuit are intensively connected through the scan path, and the output side of one integrated circuit is connected. A common selector for selectively connecting a scan path and an input-side scan path of another integrated circuit is provided on the substrate.

[0008] Another boundary scan circuit of the present invention comprises:
The common selector and test data input / output means for inputting predetermined test data to the first-stage integrated circuit and obtaining the test data from the last-stage integrated circuit are arranged on the substrate. I do.

The common selector connects the input / output terminals of the integrated circuits represented by the selection signal by switching an internal path, for example, upon input of a predetermined selection signal.

The present invention also provides the input / output terminals of all the integrated circuits except the input terminal of the first stage integrated circuit and the output terminal of the last stage integrated circuit provided on the substrate of the boundary scan circuit. A plurality of terminals for centrally connecting through the scan path, and a common terminal for selectively connecting an output side scan path of one integrated circuit and an input side scan path of another integrated circuit based on a predetermined selection signal; A selector having a selector disposed on the substrate is provided.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a boundary scan circuit according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a configuration diagram of a boundary scan circuit of the present embodiment. The boundary scan circuit 10 includes a substrate 11
A plurality of upper ICs, for example, IC1 to IC4, are connected by a single scan path, and a selector 5 for switching the path of test data on the scan path and an edge connector 12 for connecting a tester are provided. Be composed.

The scan path is formed by connecting as follows.・ ATDI terminal of edge connector 12 and TDI of IC1
1 terminal, TDO1 terminal of IC1 and IN1 of selector 5 (input)
Terminals: TDO2 terminal of IC2 and IN2 (input) of selector 5
Terminal ・ TDO3 terminal of IC3 and IN3 (input) of selector 5
Terminals: OUT1 (output) terminal of selector 5 and TDI of IC2
2 terminals, OUT2 (output) terminal of selector 5 and TDI of IC3
3 terminals, OUT3 (output) terminal of selector 5 and TDI of IC4
4 terminals ・ TDO4 terminal of IC4 and ATDO of edge connector 6
Terminal.

A selector control signal input terminal (hereinafter, CONT1 terminal) of the selector 5 is supplied with a selector control signal from a tester via a selector control signal terminal (hereinafter, CONT terminal) of the edge connector 12. ing. This selector control signal is a control signal for selectively switching the internal path of the selector 5 as described later.

FIG. 2 is a detailed block diagram of IC1 to IC4. Here, assuming that each of the ICs 1 to 4 has a common structure, only one IC is shown. I
Each of C1 to IC4 has a TDI terminal, a TDO terminal, a TAP, and six BSCs for realizing a boundary scan function, and further includes an internal logic circuit to be tested (a circuit for realizing logic in the IC) and It has a data input terminal (IN) terminal and a data output (OUT) terminal.

Each BSC is connected between the internal logic circuit and the IN terminal, and between the internal logic circuit and the OUT terminal. The broken line is the scan path inside the IC. The test data input from the TDI terminal is TAP
(In the case of not the IC under test) or via each BSC (in the case of the IC under test) to the TDO terminal.

Next, the operation of the boundary scan circuit 10 of the present embodiment will be described. Here, as shown in FIG. 3, an operation in a case where the test data set point P in the IC 3 is tested will be described. First, the selector 5
, And sets the internal path of the selector 5 to “IN1 terminal → OUT2 terminal”. Next, test data is input from the tester to the ATDI terminal of the edge connector 12. The input test data is input to the IN1 terminal of the selector 5 via the TAP of IC1,
Further, it is led to the OUT2 terminal via the internal path of the selector 5. Therefore, the bit length of the test data needs only 1 bit for TAP1 of IC1 and 3 bits for BSC of IC3, so 4 bits is sufficient.

Next, a specific configuration example of the selector 5 according to the present embodiment will be described. Before testing a specific IC on the board 11, the selector 5 controls the CO of the edge connector.
The selector control signal is input to the NT terminal, and the internal path is switched so that the test data can be output to the target IC in the shortest time. FIG. 4 shows a configuration example of the internal path for realizing such a function. The black circles in FIG. 4 indicate patterns that can be selected by the selector control signal. That is, I
N1 terminal is one of OUT1 terminal to OUT3 terminal;
The N2 terminal can be connected to the OUT2 terminal or OUT3 terminal, and the IN3 terminal can be connected to the OUT3 terminal.

FIG. 5 shows a switching pattern of an internal path when each IC is tested using such a selector 5. In the illustrated case, there are the following three internal path switching methods. First switching pattern: While connecting the IN1 terminal and the OUT1 terminal (thin solid line), the IN2 terminal is connected to the OUT2 terminal.
Terminal (thick long broken line) or OUT3 terminal (short broken line). When connected to the OUT2 terminal, the IN3 terminal and the OUT3 terminal are connected (a thin long broken line). In such a switching pattern, the test data input to IC1 is input to IC4 through IC2 and IC3, so that the test data length is the same (maximum) regardless of the test data set point.

Second switching pattern: IN1 terminal and OUT
The two terminals are connected (thick solid line), and the IN3 terminal and the OUT3 terminal are simultaneously connected (thin long broken line). In such a switching pattern, the test data input to IC1 is input to IC4 through IC3. Therefore, IC
The test data length is shortened by the amount by which 2 can be bypassed. In this switching pattern, the test data set point is IC3
The shortest scan path is obtained when the BSC is within. The above-described test operation using FIG. 3 selects such a switching pattern.

Third switching pattern: IN1 terminal and OUT
Connect only three terminals (thin solid line). This switching pattern is the shortest scan path when the test data set point is the BSC in the IC 4.

As described above, in the boundary scan circuit of the present embodiment, by switching the internal path of the selector 5, the test data can be output to the target IC to the target IC by bypassing the specific IC on the substrate 11. As a result, the test data length can be shortened,
Further, when the test target range is small, the test time can be reduced.

[0022]

As is apparent from the above description, according to the present invention, there is a specific effect that the test data length and the time required for the test can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a boundary scan circuit of the present invention.

FIG. 2 is a detailed block diagram of an integrated circuit having a boundary scan circuit unit.

FIG. 3 is an explanatory diagram of an operation of the boundary scan circuit of the present embodiment, particularly, a diagram for explaining an operation of a selector that switches a connection destination of an integrated circuit that passes test data input to a scan path.

FIG. 4 is an explanatory diagram illustrating a configuration example of an internal path of a selector according to the embodiment;

FIG. 5 is a diagram showing a specific example of the switching operation of the internal path of the selector according to the embodiment.

FIG. 6 is a configuration diagram of a conventional boundary scan circuit.

[Explanation of symbols]

 10, 60 Boundary scan circuit 5 Selector 6 Edge connector 11 Board 12 Edge connector

Claims (4)

[Claims] 1. A boundary scan circuit in which a plurality of integrated circuits each having a boundary scan circuit section are mounted on a single substrate, and each integrated circuit is connected in series by a scan path. The input / output terminals of all the integrated circuits except the output terminals of the integrated circuits of the stages are collectively connected through the scan path, and select the output side scan path of one integrated circuit and the input side scan path of the other integrated circuit. A boundary selector circuit, wherein a common selector to be connected to the substrate is disposed on the substrate. 2. A boundary scan circuit in which a plurality of integrated circuits each having a boundary scan circuit section are mounted on one substrate, and each integrated circuit is connected in series by a scan path. The input / output terminals of all the integrated circuits except the output terminals of the integrated circuits of the stages are collectively connected through the scan path, and select the output side scan path of one integrated circuit and the input side scan path of the other integrated circuit. A common selector that is connected to the first stage integrated circuit, and test data input / output means for inputting predetermined test data to the first stage integrated circuit and obtaining the test data from the last stage integrated circuit are arranged on the substrate. A boundary scan circuit. 3. The common selector according to claim 1, wherein, upon input of a predetermined selection signal, input / output terminals of the integrated circuits represented by the selection signal are connected by switching an internal path. 3. The boundary scan circuit according to 1 or 2. 4. A plurality of integrated circuits each having a boundary scan circuit unit are mounted on one substrate, and each integrated circuit is provided on the substrate of the boundary scan circuit connected in series by a scan path. A plurality of terminals for intensively connecting the input terminal of the circuit and the input / output terminals of all the integrated circuits except the output terminal of the final stage integrated circuit through the scan path; based on a predetermined selection signal, A selector, wherein a common selector for selectively connecting an output-side scan path of an integrated circuit and an input-side scan path of another integrated circuit is provided on the substrate.