JPH11312007A - Programmable controller - Google Patents

Abstract

(57) [Summary] To provide a programmable controller in which control processing and information processing are integrated. A control processing bus for transferring control processing data at a fixed period and an information processing bus for transferring information processing data at a non-fixed period are provided separately, and control processing and information processing are executed independently. The cyclic data transfer circuit for transferring the control processing data and the control processing dedicated processor (SPU) for executing the control operation have a timer count end report of CP.
U and is activated by the CPU. The cyclic data transmission circuit has a PI / O between the PI / O and the PI / O memory.
Send and receive O data. The SPU reads the program from the sequence memory storing the control program, and
Input / output necessary for O is performed via a PI / O memory. Data necessary for the control processing is transferred at a fixed period by the control processing bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device such as a programmable controller, and more particularly to a bus of a programmable controller in which a function as a control device requiring real-time control and a function of an information / communication device are integrated. It is.

[0002]

2. Description of the Related Art A programmable controller (PL)
C) is a controller generally used widely as a control device for controlling machines and equipment, and a user can program the control contents, conditions, procedures, and the like of the machine and equipment by combining command words. PLC is basically a control arithmetic unit (a general-purpose processor for information processing (CPU: Central Pr
processor, control processor (SPU: Se)
queue processor unit), a process input / output device (PI / O) for transmitting and receiving input / output signals to and from a control target, a PI / O memory (PI / O image memory) storing PI / O information, and a programming tool device And a communication line controller, which are connected by a common bus as described in JP-A-61-29906 to realize a function as a PLC.

The basic function of a PLC is to control a process (machine, equipment) by a program.
This is realized by performing a series of processing of “O input → control calculation → PI / O output” at high speed and at a constant period. In recent control systems at production sites, information processing such as communication processing is indispensable. In the past, control was performed by a controller, and information processing was performed by a personal computer or workstation.However, the demand for devices that integrate process control and information processing has increased. The controller is required to have a function that operates in conjunction with the controller. In particular, a PLC that plays a central role in a production site has a high demand for a function of processing information such as a communication function, and various production-related information (production management, quality control, etc.) besides control, which is a basic function of the PLC. ,progress,
In order to handle the yield, etc., it is important to enhance information processing functions such as information transmission, arithmetic processing, and information management.

[0004]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 61-2990
FIG. 5 shows a configuration of a conventional PLC using one common bus as disclosed in Japanese Patent Application Laid-Open No. 6-206. In a conventional PLC, PL
Since the functions constituting C are connected by one common bus 28, when both the control processing and the information processing are performed, the control processing and the information processing cannot be executed independently and in parallel.
This example is shown using the operation timing chart of the control system processing and the information system processing in the conventional PLC of FIG.

In a conventional PLC, a control system process C-1 is executed by a control system process activation A. After the control system processing start A, the control system processing C-2 is executed again after a certain period by the control system processing start B, and the control system processing is repeatedly executed at the fixed period T. On the other hand, information processing is started at irregular intervals via a communication line due to an event (such as a request from an operator). The information processing request D executes the information processing I-1. The information processing is not started in a fixed cycle like the control processing, and the processing time varies depending on the contents of the request at that time, and the control processing and the information processing may overlap. Information processing I by information processing request E
-2 is executed, but if the control system process C-3 which is started at regular intervals during the process is started, the process is transferred (bus usage right) to the control system process, and the control system process is given priority. After the control processing, the information processing is continued.

Therefore, if the time required for the information processing required for the PLC becomes large in the control cycle T, the processing of the information processing system is stagnated, the function of the entire PLC becomes unstable, and the control processing and the information processing are not performed. Cannot be realized. Therefore, it is required that the control system and the information system have independent configurations and perform stable processing. However, the conventional system is simply reduced in size, and the internal configuration of the PLC is divided into control and information processing. Just by doing so, it is not possible to build a control system that integrates control and information.

An object of the present invention is to provide a PLC bus configuration for realizing a PLC that integrates control processing and information processing, and a control system that can be easily and compactly constructed by a PLC to which the PLC is applied. It is in.

[0008]

According to the present invention, as described in the above-mentioned prior art, there is provided a PLC in which control system processing and information system processing are integrated. Independently equipped with a control bus (cyclic bus) and an information bus (random bus) for transferring data for process progress, failure status, production management, and information processing.
By providing a competing circuit for arbitrating access to the PI / O memory from the CPU, SPU, and cyclic data transfer means connected to each bus, the control processing and the information processing share the PI / O memory and The P which integrates control processing and information processing by being executed in parallel
LC can be realized.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a PLC to which an independent control system processing bus and an information processing bus are applied in an embodiment of the present invention. In FIG. 1, a communication interface device (hereinafter, referred to as a communication I / F) 3 for connecting a CPU 1, a main memory 2, a program device 4 and the like for executing information processing requiring random processing is provided for information processing. Connect with a bus (random bus) 5. The information processing bus 5 transfers data for information processing such as progress of process, defect status, production management, and communication processing controlled by the system. On the other hand, each function for control system processing requiring cyclic processing, PI / O6, 7 and PI
A PI / O memory 9 for storing data to be exchanged with I / O (hereinafter referred to as PI / O data). The PI / O data is transferred between the PI / O memory 9 and the PI / Os 6 and 7 at a constant cycle. A control processing bus (cyclic bus) 15 connects a cyclic data transfer circuit 8 to be transferred and a control processing dedicated processor (SPU) 10 for a control operation for executing a control program at regular intervals. The SPU 10 is connected to a SEQ memory 11 for storing a control program. The CPU 1 is connected with a timer 1 and a timer 2 for activating the SPU 10 and the cyclic data transfer circuit 8 at a fixed cycle, and manages a cycle of a cyclic process from the CPU 1 side.

The CPU 1 sends a timer 1 (13) and a timer 2 (14) for activating the SPU 10 and the cyclic data transfer circuit 8 at a fixed period, respectively, to an activation signal T.
Start by M1_START16 and TM2_START17 (10
0). Here, the timer 1 (13) is used for the cyclic data transfer circuit 8 and the timer 2 (14) is used for the SPU 10, and the timer 1 manages the cycle T of the cyclic processing.
The timer 2 manages the upper limit of data transfer by the cyclic data transfer circuit.

When the set time is reached, the timer 1 (13) counts the timer 1 count end report signal TM1_END18.
Informs the CPU 1 that the timer 1 has counted up. CPU receiving this signal TM1_END18
1 is a cyclic data transfer circuit activation signal CYC_S
The cyclic data transfer circuit 8 is activated by the TART 26. The activated cyclic data transfer circuit 8 is
The input / output data of the I / Os 6 and 7 is transferred to and from the PI / O memory 9. At this time, the read / write request signal CYC-P of the PI / O memory from the cyclic data transfer circuit is output.
The I / O_R / W 23 is input to the contention circuit 12, and the contention circuit 12 determines the right to use the PI / O memory according to the set priority order, and issues a PI / O memory read / write signal PI / O to the PI / O memory. OMEM_R / W25 is output and P
Controls I / O memory read / write. When the cyclic data transfer circuit 8 completes the data transfer of the set PI / O, the cyclic data transfer completion report signal CYC_END27 causes the PI / Os 6, 7 and P
The completion of the data transfer with the I / O memory 9 is indicated by C
Report to PU1.

On the other hand, when the timer 2 (14) reaches the set time, the timer 2 count end report signal TM2_EN
CP that the timer 2 has counted up by D19
Report to U1. By this signal TM2_END19, C
PU1 outputs the SPU activation signal SPU_START20 to activate SPU10. The activated SPU 10 is SE
The control program stored in the Q memory 11 is read, and a predetermined control operation is executed. At this time, in order to transmit / receive PI / O data necessary for the control operation from the PI / O memory 9 via the control system bus 15, first, the PI / O memory read / write signal SPU-PI / OMEM_R /
W22 is input to the competition circuit 12. And the competition circuit 12
Determines the access from the SPU 10 to the PI / O memory 9, the SPU 10 reads the PI / O data from the PI / O memory 9. When the control operation processing is completed, the SPU 10 outputs an SPU operation end report signal SPU_END21 by using
Report to CPU1.

After that, the CPU 1 receiving the count-up report of the timer 1 by the TM1_END 18 makes the timer 1 count up at the same time when the cyclic data transfer circuit 8 is activated.
(13) The timer 2 (14) is restarted.

As described above, the SPU 10 and the cyclic data transfer circuit 8 are activated at regular intervals, and control is realized.

FIG. 2 shows the operation timing chart. Timer 1 (13) signals the end of counting by signal TM1_E.
Report by ND18. The CPU 1 outputs the signal TM1_E
Upon receiving the ND 18, the timer 1 executes a termination process 100,
At the time of the timer 1 end processing 100, the timer 1 (13),
Timer 2 (14) is set to signal TM1_START,
Activated by TM2_START. At the same time, the signal CYC
-The cyclic data transfer circuit 8 is started by START20. The cyclic data transfer circuit 8 notifies the end of the data transfer processing 105 by the signal CYC_END27 to the CPU.
Report to 1. The timer 2 (14) reports the end of counting to the CPU 1 by a signal TM2_END19. CPU
1 indicates a signal SPU_ST in the timer 2 end processing 101.
The SPU 10 is started by the ART 20. The SPU 10 reports the end of the control operation processing 106 to the CPU 1 by a signal SPU_END21. SPU10,
The cyclic data transfer circuit 8 is repeatedly activated at a constant period T, and cyclic processing is performed. Here, the PI / O data transfer processing (CYC data transfer processing) 105 and the control arithmetic processing 106 use the control system bus, and the CPU 1 uses the information system bus for the random information system processing. The processing and the control system processing can be performed independently and in parallel.

When PI / O data is required in the information processing, a PI / O memory read / write signal CPU-PI / O_R / W24 from the CPU 1 is input to the competing circuit 12, and the competing circuit 12 gives priority. Attached to PI / O
Memory can be read / written. Competitive circuit 1
In the processing in 2, the processing of the control system and the processing of the information system are performed in parallel. Therefore, when trying to access the PI / O memory from the information system, the P
It may be that the I / O memory is being accessed. In this case, the competing circuit 12 includes a PI / O memory read / write signal SPU-PI / OMEM_R / W22 from the control SPU 10 or the cyclic data transfer circuit 8,
A signal CYC-PI / O_R / W23 and a PI / O memory read / write signal CPU-PI / O_
R / W 24 is input, and one of the signal transmission sources is selected according to the priority of these signals. At the time of selection, the time constraint of the control system is emphasized, and the signal CYC-PI / O
_R / W23 with the highest priority, and the signal CPU-PI / O_R /
The W24 and the signal SPU-PI / OMEM_R / W can be processed to permit access to the PI / O memory 9 on average so that the processing is not biased, and the signal CYC
-PI / O_R / W23 and signal SPU-PI / OMEM
_R / W priority signal CPU-PI / O_R / W24
It is also possible to set higher.

The end report signal CYC_END 27 of the cyclic data transfer processing 105 to the CPU 1 and the end report signal SPU_END 21 of the control operation processing 106
Can be checked by the CPU 1 to confirm whether the cyclic data transfer circuit 8 and the SPU 10 are operating normally.

As described above, a PLC in which control processing and information processing are integrated can be realized. In the embodiment shown in FIG. 1, the count-up of the timer 1 and the timer 2 is once reported to the CPU 1, and the CPU 1 activates the SPU 10 and the cyclic data transfer circuit 8.
A method is also conceivable in which the timer 1 and the timer 2 are connected to the SPU 10 and the cyclic data transfer circuit 8, respectively, and are directly activated without the intervention of the CPU 1. In this case, CPU1 and S
The PU 10 and the cyclic data transfer circuit 8 operate independently of each other, so that it is easy to perform information processing and control processing in parallel. It is not possible to easily monitor whether the SPU 10 is operating normally or not. In addition, the information processing and the control processing cooperate with each other and perform processing in synchronization with each other. Up C
This is more difficult than reporting to PU1.

As shown in FIG. 3, according to the present invention, after the control system process C-1 is executed by the control system process start A, the control system process C-2 is again executed after a predetermined period by the control system process start B.
Is executed, and the control system processing is repeatedly executed at a constant cycle T. On the other hand, the information processing is started via a communication line due to an aperiodic event, and the processing time differs depending on the content of the processing request, so that the control processing and the information processing may overlap. When the information processing request I executes the information processing I-1 and the information processing request E executes the information processing I-2, the information processing I-2 by the information processing request E is changed to the next processing. Even if the processing is not completed by the start of the control system execution processing, the control system bus and the information system bus are made independent as shown in FIG.
U is an interrupt process for managing the processing cycle of the control system;
Except for a slight interruption due to contention processing performed when accessing the I / O memory, information processing continues, so that information processing is not stagnated. As described above, since the processing time of each is stably secured and the processing stagnation does not occur, the control processing and the information processing are performed in parallel and cooperatively. Integrated PLC
Can be realized.

FIG. 4 shows an example in which the functions constituting the PLC according to the present invention are modularized to constitute the PLC according to the present invention.

The backplane 30, the CPU module 31, the PI / O module 32, the communication module 33,
Each module such as the extended memory module 34 is connected to either the control bus or the information bus by a control bus module connector 35 or an information bus module connector 36. A connector for both a control bus (for PI / O) and an information bus (for option) are attached to each mounting slot of the backplane 30,
I / O and other options can be implemented in any slot of backplane 30. The connection to which bus is determined by the position of the connector of the module. Also, even when a single connector is used for both the PI / O and the option, the PI / O can be connected to any slot without restricting the mounting position.
Both O and optional implementations are possible. This allows the user to freely configure the control system by freely combining the modules according to the machine or equipment to be controlled.

[0022]

As described above, since the control processing bus for transferring the control information at a fixed period and the information processing bus are independently provided, both processing times can be secured independently.
The respective processes are executed stably, and the system does not perform uneasy operation due to the stagnation of the processes, so that it is possible to realize a PLC in which the control process and the information process are integrated.
And the control system can be compactly and easily constructed by the PLC to which the present invention is applied.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a PLC according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of a control system process and an information system process of the PLC according to the embodiment of the present invention.

FIG. 3 is an operation timing chart of a control system process and an information system process of the PLC according to the embodiment of the present invention.

FIG. 4 is a diagram showing a configuration in which the PLC of the present invention is modularized for each function.

FIG. 5 is a configuration diagram of a conventional PLC.

FIG. 6 is an operation timing chart of a conventional control system process and information system process of a PLC.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Central processing unit (CPU), 2 ... Main memory, 3 ... Communication I
/ F, 4 program device, 5 information processing bus (random bus), 6, 7 process input / output device (PI /
O), 8: cyclic data transfer circuit, 9: PI / O
Memory, processor for control processing (SPU), 1
1 ... control program storage memory (SEQ memory), 1
2: Competitive circuit, 13: Timer 1, 14: Timer 2, 15
... Control processing bus (cyclic bus).

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Tadashi Okamoto 5-2-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant of Hitachi, Ltd. (72) Kazuhisa Watanabe 5-chome, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Inside the Hitachi, Ltd. Omika Plant (72) Inventor Kimiharu Yaguchi 5-2-1, Omika-cho, Hitachi City, Ibaraki Pref.

Claims (6)

[Claims] 1. A programmable controller comprising a CPU for performing communication processing and an operation means for performing control operation, wherein a first bus (cyclic bus) for performing data transfer at a fixed period and a data access at irregular intervals are provided. When two units (random buses) are provided and a unit connected to both the first bus and the second bus is accessed, an output is made from an access request source connected to one of the two buses. A programmable controller comprising a circuit for selecting one access request from access requests. 2. The programmable controller according to claim 1, wherein the units connected to both the first bus and the second bus are PI / O memories for storing data exchanged with a control process. The request source is the CPU, the arithmetic means, and the PI /
A programmable controller, which is a cyclic data transfer circuit that controls data transfer between the O-memory and the control process at a constant cycle. 3. A programmable controller comprising a CPU for performing communication processing and an operation means for performing control operation, wherein a first bus (cyclic bus) for performing data transfer at a fixed period and a data access at irregular intervals are provided. 2 buses (random buses), and the first bus is connected to the arithmetic means and a cyclic data transfer circuit that controls data transfer at a fixed period in the first bus. Is connected to the CPU, and the arithmetic unit and the cyclic data transfer unit are
A programmable controller, which is started at a fixed period by a signal from the CPU, and outputs a signal for notifying the CPU of the end of processing to the arithmetic means and the cyclic data transfer means. 4. The programmable controller according to claim 3, further comprising: a first timer for controlling said cyclic data transfer cycle; and a second timer for controlling a start timing of said arithmetic means. A timer and a second timer are connected to the CPU, and based on a signal from the first timer, the CPU activates the first and second timers and the cyclic data transfer unit, and a second timer A programmable controller characterized in that the CPU activates the calculating means based on a signal from the CPU. 5. The programmable controller according to claim 4, further comprising: a first timer for controlling said cyclic data transfer cycle; and a second timer for controlling a start timing of said arithmetic means. A programmable controller, wherein a timer is connected to the cyclic data transfer means, and the second timer is connected to the arithmetic means. 6. A programmable controller comprising a CPU for performing communication processing and an operation means for performing control operation, wherein a first bus (cyclic bus) for performing data transfer at a fixed period and a data access at irregular intervals are provided. 2 buses (random buses), and the first bus is connected to the arithmetic means and a cyclic data transfer circuit that controls data transfer at a fixed period in the first bus. Is connected to the CPU, and the arithmetic unit and the cyclic data transfer unit are
The computing means and the cyclic data transfer means are started at regular intervals by the CPU, and the end of the processing is determined by the CP.
U, and any of the arithmetic means or the cyclic data transfer circuit or the CPU becomes an access request source and accesses a unit connected to both the first bus and the second bus. A programmable controller comprising a contention circuit for selecting one access request from access requests output from an access request source.