JPH1130789A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of afterimage or uneven display through a high contrast ratio by providing a TFT element for writing signals and a resetting TFT element which consists of a thin film transistor of a channel different from that of the signal writing TFT element and which is connected between a pixel electrode and an auxiliary capacity line. SOLUTION: A signal line 12 is connected to a pixel electrode 15 through an n channel TFT element 14. The pixel electrode 15 is also connected to an auxiliary capacity line 13 in the same line through a p channel TFT element 17. The gate electrode of the n channel TFT element 14 and that of the p channel TFT element 17 that are connected to the same pixel electrode 15 are connected to the scanning line 11 of a different line. Thus, with the two switching (TFT) elements 14, 17 equipped for resetting and for signal writing, the two operations are simultaneously performed, thereby preventing lowering of an effective impressed voltage, eliminating an afterimage due to 'step response', and enabling a high contrast to be obtained at a lower voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device using a ferroelectric liquid crystal and an antiferroelectric liquid crystal.

[0002]

2. Description of the Related Art In order to improve the response speed and viewing angle of a TFT-LCD using a TN liquid crystal, several studies have been made on using a ferroelectric liquid crystal or an antiferroelectric liquid crystal as a liquid crystal material. When a liquid crystal material having these spontaneous polarizations, that is, a liquid crystal material of a chiral smectic C phase or its subphase is applied to an active matrix type liquid crystal display element, when the response time of the liquid crystal is longer than the writing time, It is known that a phenomenon in which the holding voltage is lowered due to this occurs (Hartmann: J. Appl. Phys. 66, 1132 (1989)). This decrease in the holding ratio is a so-called insufficient writing, which results in a decrease in the effective applied voltage, and lowers the contrast ratio, which is a serious problem in practical use.

In addition, in the case of driving in a positive / negative symmetric mode by inverting the polarity of the applied voltage for each frame, that is, in the case of AC driving, when the absolute value of the signal voltage changes at a certain frame, the brightness is repeated over several frames. However, there is also known a problem that a phenomenon in which the transmitted light amount settles down, that is, a so-called step response occurs (Verhulst et al .: IDRC'94digest, 377 (1994)). In the step response, a ghost is recognized as an afterimage having a trailing shape, which poses a practical problem.

In the case of an asymmetric mode instead of a symmetric mode, that is, a DC drive, no step response occurs and the contrast ratio is improved (Tanaka et al .: SID'94digest, 430 (1)
994)). However, since the response is cumulative, the response speed of the image is lower than that of the AC drive. This decrease in the response speed of the image is also due to insufficient writing in one writing, that is, a decrease in the holding voltage. The shorter the writing time, the lower the response speed. In DC driving, there is a trade-off between the contrast ratio and the response speed of an image, and both require an optimal design to obtain a sufficient value, but the margin is narrow. Further, the problems of image sticking due to impurities and residual images due to residual hysteresis are difficult to be solved even by driving contrivance.

As described above, in any of the symmetric mode (AC drive) and the asymmetric mode (DC drive), insufficient writing due to a decrease in the holding ratio causes a serious problem in practical use.

There are two possible measures to reduce the retention of liquid crystal materials in terms of their characteristics: increasing the response speed and reducing the spontaneous polarization. The above problem can be solved by using a liquid crystal material which is sufficiently fast even at a low voltage drive or a temperature range slightly lower than normal temperature and has a response time shorter than the writing time. However, at present, there is no liquid crystal material satisfying the condition. . Further, it is questioned how to realize a higher response speed especially in a low temperature range.

[0007] Liquid crystal display elements will be further enlarged in the future.
Higher definition is required, but this necessarily involves a reduction in the writing time per line. Therefore, it is difficult to solve the above-mentioned problem due to the limitation of increasing the speed of the liquid crystal material.

In addition, the reduction of spontaneous polarization causes a reduction in response speed in principle, and the above problem cannot be solved after all. As described above, the improvement of the characteristics by the liquid crystal material is insufficient as a countermeasure against the problem of the decrease in the holding voltage.

Next, a measure by improving the driving method and the circuit structure will be considered. First, a method of increasing the auxiliary capacitance can be considered. The auxiliary capacitance value of an active matrix type liquid crystal display device using a normal TN liquid crystal is approximately the same as the capacitance between a pixel electrode and a counter electrode filled with liquid crystal, but is increased by 10 times or more. By doing so, a decrease in the holding voltage can be solved. However, the step response cannot be solved as long as the response speed of the liquid crystal material is as low as the current level. In addition, the amount of current increases correspondingly with the increase in the auxiliary capacitance, so that the power consumption increases and the load on the drive circuit increases. Therefore, it cannot be said that it is suitable for practical use, and its use is limited.

As another solution, 0 V immediately before writing is applied.
There is known a method of writing a nearby voltage and performing a reset operation for erasing or canceling a previously held charge.
An active matrix driving method using a TFT or a TFD is proposed in Japanese Patent Application Laid-Open No. 7-64056. However, these methods allocate a part of a writing time to a reset operation. For this reason, the step response is solved, but the substantial writing time is shortened unless the number of lines is reduced, so that the contrast is not sufficiently improved. Further, when the writing time is shortened due to the high definition, the writing time is further shortened due to the reset operation, and the insufficient writing becomes serious. Further, in these methods, the reset time cannot be sufficiently secured, and only an incomplete reset can be performed. Therefore, it is impossible to completely eliminate the step response. In particular, when the state changes from the dark state to the bright state, the problem that the luminance of the first frame becomes too high remains.

Further, a circuit structure having two TFDs and two signal lines for each pixel has been reported in order to take a longer reset time and perform a complete reset operation (Verhulst e).
tal .: IDRC'94digest, 377 (1994)). In this report,
It is also possible to perform a reset operation during writing of another line. However, the number of elements and wires per pixel is large,
Further, the driving waveform is complicated, and there is a problem in terms of manufacturing yield and cost. In addition, the TFD has a problem in that it is difficult to suppress variations in element characteristics of the entire display element, and is not suitable for practical use.

[0012]

As described above, in an active matrix type liquid crystal display device using a ferroelectric liquid crystal or an anti-ferroelectric liquid crystal, the conventional liquid crystal material and the driving method cause a reduction in holding voltage. There is a problem that afterimages and display unevenness occur due to a decrease in contrast ratio or a decrease in image response speed.

An object of the present invention is to provide a liquid crystal display element having a high contrast ratio and free from afterimages and display unevenness, while using a ferroelectric liquid crystal or an antiferroelectric liquid crystal as a liquid crystal material. is there.

[0014]

[Means for Solving the Problems]

[Configuration] The present invention is configured as described below to achieve the above object. (1) The present invention (Claim 1) is an active matrix type liquid crystal display element using a thin film transistor and a liquid crystal material of a chiral smectic C phase or a sub-phase thereof, comprising a p-channel or n-channel thin film transistor. Signal writing T connected between the line and the pixel electrode
It is characterized by comprising an FT element and a reset TFT element which is composed of a thin film transistor having a channel different from that of the signal writing TFT element and is connected between the pixel electrode and an auxiliary capacitance line.

Preferred embodiments of the present invention are shown below. (1-1) The signal writing TFT element is an n-channel thin film transistor, and the reset TFT element is a p-channel thin film transistor.

A preferred method of driving the liquid crystal display device of the present invention will be described below. (1-2) At the same time as performing signal writing by applying a voltage to a scanning line so as to turn on only the signal writing TFT element of a certain pixel row, the plurality of pixel rows different from the pixel row A reset operation of a plurality of pixel rows is performed by applying a voltage to the scanning line so that only the switching TFT element is turned on. (2) The present invention (claim 2) relates to an active matrix type liquid crystal display device using a liquid crystal material of a chiral smectic C phase or a sub phase thereof, wherein the first scanning line, the signal line, and the pixel electrode , A signal writing switching element controlled by the selected first scanning line, a second scanning line, and the pixel writing electrode connected to the storage capacitor. And a reset switching element controlled by the second scanning line.

Preferred embodiments of the present invention are shown below. (2-1) The second scanning line of one or more pixel rows is connected to the first scanning line of one or more different pixel rows.

A pixel row is a group of pixels to which an image signal is simultaneously written from a signal line when the first scanning line is selected. (2-1.1) The second scanning line is connected to the first scanning line via a diode. (2-1.2) The second scanning line is connected to the first scanning line on the substrate. That is, only the terminal of the first scanning line connected to the driving IC is provided on the substrate, and the terminal of the second scanning line is not formed. (2-2) The first and second scanning lines and signal line driving circuits are formed on an array substrate. (2-3) The first scanning line and the second scanning line are connected to different driving ICs from terminals provided on the same side or different sides of the array substrate end or the array substrate peripheral circuit substrate end. .

A preferred method for driving the liquid crystal display device of the present invention is described below. (2-4) At the same time as applying a voltage to the first scanning line to perform signal writing so as to turn on only the signal writing switching element of a certain pixel row, a signal different from that of the pixel row is applied. A voltage is applied to the second scanning line so that only the reset switching elements of one or more pixel rows are turned on, and the plurality of pixel rows are reset.

[Operation] The present invention has the following operation and effects by the above configuration. One end of a signal writing switching (TFT) element and one end of a reset operation switching (TFT) element are connected to one pixel electrode, and the other ends are connected to a signal line and an auxiliary capacitance line, respectively. Since the two switching (TFT) elements can be independently controlled, the signal writing operation and the reset operation can be performed independently.

Therefore, signal writing is performed by signal writing switching (TFT) connecting the signal line and the pixel electrode, and reset operation is performed by reset switching (TFT) connecting the auxiliary capacitance line and the pixel electrode. In each pixel, a reset operation is performed before writing a signal, so that it is possible to eliminate the above-described problems of contrast reduction and step response that need to be solved.

Further, by performing a reset operation on several other rows at the same time as writing a signal on one row, the reset effect is further enhanced, the contrast is further improved, and the step response can be completely eliminated. Become.

When a pixel electrode is connected to an auxiliary capacitance line (auxiliary capacitance line) via a reset switching (TFT) element, an auxiliary electrode belonging to either the same row as the pixel to be reset or an adjacent row is used. Several methods are conceivable, such as connecting a capacitance line or connecting to an auxiliary capacitance line wired in a direction crossing the scanning line.

At the time of resetting, the storage capacitor potential is hardly moved and is set to the same potential as the counter electrode potential, and the pixel applied voltage is set to 0.
When resetting to a voltage near V, reset TF
In some cases, it is possible to increase the aperture ratio by connecting to a storage capacitor line belonging to a row adjacent to the pixel for which T is to be reset, or to a storage capacitor line wired in a direction crossing the scanning line. .

When resetting the voltage applied to the pixel to a voltage other than 0 V, for example, a saturation voltage or a voltage near 1/2 of the saturation voltage by resetting the storage capacitor potential at the time of reset, the reset TFT is reset. It is preferable to connect to an auxiliary capacitance line attached to the same row as the pixels.

The functions and effects unique to each invention will be described below. [Configuration (1)] According to this configuration, the decrease in the aperture ratio is caused by the TF
This is only an area for one T element, which is more advantageous than the conventional method of increasing the number of wirings.

Further, an n-channel TFT element having high mobility is used as a TFT element for signal writing, and
It is preferable to use a p-channel TFT element having lower mobility than the element as the reset operation TFT element, rather than the opposite case. That is, while the reset time can be sufficiently taken, the signal writing time is limited by the number of lines. Therefore, it is preferable to use a signal writing TFT element having better writing characteristics.

[Configuration (2)] According to this configuration, it is possible to use a conventional scanning line driving IC, so that there is no increase in cost.

Also, by connecting one or more rows of second scanning lines different from the first scanning lines, the number of terminals connected to the scanning line driving IC can be reduced by the conventional method without the second scanning lines. In this case, the reset operation can be automatically performed only by making the driving waveforms input to the respective scanning line terminals the same as in the conventional case.

Further, when the second scanning line is connected to the first scanning lines of a plurality of rows which are continuously selected, if the same driving waveform as in the related art is applied, the selection signal from the first scanning line is continuously output. This is applied to the second scanning line, and the simultaneous reset operation of a plurality of lines, that is, a sufficient reset time can be secured.

Further, by connecting the first scanning line and the plurality of second scanning lines via diodes, respectively,
The reset of a plurality of lines can be performed completely independently at the same time as each signal writing, and the quality of the displayed image can be maintained. Further, the first scanning line and one or more If the circuit is configured so as to be branched into two scanning lines, both the peripheral circuit board and the scanning line driving IC can be diverted to the conventional one, and the cost does not increase at all.

Further, by performing a reset operation on several other rows simultaneously with writing a signal on a certain row, the reset effect is further enhanced, the contrast is further improved, and the step response can be completely eliminated. Become.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. These embodiments are described for the purpose of facilitating the understanding of the present invention, and can be variously modified and used without changing the gist of the present invention.

First, an embodiment of a liquid crystal display element in which two TFT elements, an n-channel TFT element and a p-channel TFT element, are connected to a pixel electrode will be described. [First Embodiment] In a liquid crystal display element, a CF substrate on which a counter electrode is formed is disposed via a liquid crystal material on a TFT array substrate on which a TFT element, a pixel electrode, and the like are formed.

The TFT array substrate has 640 × 480.
(VGA) pixels are arranged in a matrix. Each pixel is composed of three sub-pixels corresponding to three primary colors.

FIG. 1 is a plan view showing a configuration of a sub-pixel on a TFT array substrate. FIG. 2A is a circuit diagram showing an equivalent circuit of a 4-row, 2-column portion in the sub-pixel group.
The scanning lines 11 are formed in the row direction, and the signal lines 12 are formed in the column direction. Further, the auxiliary capacitance line 13 is formed in the row direction.

The scanning line 11 has an n-channel TFT element 14
Are connected. Also, if the signal line 12 is n
It is connected to the pixel electrode 15 via the channel TFT element 14.

The pixel electrode 15 is connected to the auxiliary capacitance line 13 via the auxiliary capacitance 16. Further, the pixel electrode 15
It is connected to the auxiliary capacitance line 13 in the same row via the p-channel TFT element 17. An n-channel TFT element 14 connected to the same pixel electrode 15 and a p-channel TFT element 1
The gate electrodes 7 are connected to the scanning lines 11 in different rows.

The semiconductor layer of each TFT element has a-S
i was used. n-channel and p-channel TFT elements 1
4, 17 adjust the initial carrier concentration and the film thickness of a-Si or the film thickness of the gate insulating film as appropriate to obtain both T and T.
The FT elements 14 and 17 were formed so that the difference between the threshold voltages was larger than twice the signal amplitude during driving. As will be described later, in the drive system of the present embodiment, since the signal amplitude is ± 3 V, the difference between the threshold voltages of the two TFT elements is set to 6 V or more.
Further, the W / L of the p-channel TFT element 17 was made larger than that of the n-channel TFT element 14.

The liquid crystal cell was manufactured by the following method. The CF substrate had an overcoat layer, and a portion of the ITO electrode (opposite electrode) facing the signal line and the TFT element of the TFT array substrate opposed to each other was removed by etching. Further, a 30 nm-thick SiO 2 is formed on the ITO electrode.
_Two films were formed by a sputtering method. ITO electrode (pixel electrode) on TFT array substrate and SiO on CF substrate
_On each of the _two layers, a low pretilt polyimide film was formed as a liquid crystal alignment film. The alignment film of each substrate was rubbed in the cell longitudinal direction in the direction opposite to the injection direction. However, the rubbing axes of both substrates were shifted by about 10 °. The cell gap was 2.0 μm by spraying a resin-coated silica spacer between the TFT array substrate and the CF substrate.
And

As the liquid crystal material, spontaneous polarization 200 nC / c
A threshold antiferroelectric liquid crystal A (manufactured by Mitsui Petrochemical Co.) having m ² , a response time of 100 μs, and a saturation voltage of 4 V was used. The driving system has a maximum applied voltage of ± 3 V and a selection time of 64 μm per line.
s compatible with VGA (up and down two-part drive) was used. The scanning line driving waveform shown in FIG. 2B was input to each scanning line 11. In this waveform, a reset p-channel T
After a reset pulse 21 for turning on the FT element 17, a signal writing pulse 22 for turning on the n-channel TFT element 14 for signal writing is output. The reset pulse 21 was partially overlapped by a plurality of lines, and the pulse width was set to about 300 μs to secure a sufficient reset time.

When a reset pulse 21 is input to the scanning line 11, the n-channel TFT element 14 remains off and 1
The p-channel TFT element 17 connected to the pixel below the row is turned on. Then, when the p-channel TFT element 17 is turned on, the pixel electrode 15 is connected to the auxiliary capacitance line 13. Then, the reset operation is performed by keeping the storage capacitor line potential at the same potential as the counter electrode potential with almost no movement and setting the pixel applied voltage to a voltage near 0V.

Next, the signal write pulse 22 causes n
The channel TFT element 14 is turned on, the p-channel TFT element is turned off, and an image is displayed by inputting an image signal corresponding to the gradation of the image from the signal line 12 to the pixel electrode 15.

The image signal input from the signal line 12 was set to an alternating current centered on the potential of the counter electrode, and in each frame, the signal line was inverted for each column to invert the signal polarity, and driving was performed to display an image.

As a result of the image display, the contrast ratio was 70:
1. A response speed of 1 ms or less was obtained, and no afterimage due to a step response was observed. [Second Embodiment] The liquid crystal display device of the present embodiment is a display in which 640 × 480 (VGA) pixels are formed on an array substrate.

FIG. 3 is a plan view showing a configuration of a sub-pixel on the TFT array. FIG. 4A is a circuit diagram showing an equivalent circuit of a 4-row, 2-column portion in the sub-pixel group. 3 and 4, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The feature of this embodiment is that an n-channel TFT element 14 connected to the same pixel electrode 15 and a p-channel TFT
The gate electrode of the FT element 17 is connected to the scanning line 11 of the same pixel row, and the pixel electrode 15 is connected to the auxiliary capacitance line 13 of the same pixel row via the p-channel TFT element 17.

The auxiliary capacitance lines 13 in each row are not connected at the extreme end and taken out from the same terminal as usual, but are taken out independently from the terminals provided at the substrate end opposite to the scanning line terminals in each row. In this structure, the potential of each auxiliary capacitance line 13 can be driven independently. Note that the terminal of the auxiliary capacitance line 13 and the terminal of the scanning line 11 may be collectively taken out from the same side and the group of the auxiliary capacitance line 13 and the group of the scanning line 11 may be collectively taken out and driven by different driving circuit IC groups. It is.

The manufacturing method of each TFT element, liquid crystal material and liquid crystal cell is the same as that of the first embodiment, and the description is omitted. The drive system used was a VGA-compatible (vertical two-part drive) with a maximum applied voltage of 3 V and a selection time of 64 μs per line. The scanning line driving waveform illustrated in FIG. 4B was input to each scanning line 11. The reset pulse 21 partially overlaps a plurality of pixel rows, and its pulse width is set to about 300 μs to secure a sufficient reset time.

When a reset pulse 21 is input to the scanning line 11, the n-channel TFT element 14 turns off and the p-channel TFT element 17 turns on. p-channel TFT
When the element 17 is turned on, the pixel electrode 15 is connected to the auxiliary capacitance line 13. Then, the reset operation is performed by setting the pixel applied voltage to a voltage near 1/2 of the saturation voltage having the polarity opposite to the signal polarity of the previous frame. This behavior is
This is performed by shifting the potential of the auxiliary capacitance line to half the saturation voltage of the liquid crystal.

Next, the signal writing pulse 22 causes n
The channel TFT element 14 is turned on, an image signal corresponding to the gradation of the image is input from the signal line 12 to the pixel electrode 15, and an image is displayed.

The image signal was AC with the potential of the counter electrode as the center, and in each frame, row inversion (H inversion) for inverting the signal polarity was performed for each row and driving was performed to display an image. As a result of the image display, a contrast ratio of 70: 1, 1 m
A response speed of s or less was obtained, and no afterimage due to the step response was observed.

[Third Embodiment] The liquid crystal display element of the present embodiment is a display in which 640 × 480 (VGA) pixels are formed on an array substrate.

FIG. 5 is a plan view showing the configuration of the sub-pixel on the TFT array. FIG. 6A is a circuit diagram showing an equivalent circuit of a 4-row, 2-column portion in the sub-pixel group. 5 and 6, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment is characterized in that an n-channel TFT element 14 connected to the same pixel electrode 15 and a p-channel TFT
The gate electrode of the FT 17 is connected to the scanning line of the same pixel row, and the pixel electrode is connected to the auxiliary capacitance line 13 of a different pixel row via the p-channel TFT element 17.

Since the method of manufacturing each TFT element is the same as that of the first embodiment, the description is omitted. In the liquid crystal display device of the present embodiment, the spontaneous polarization is 100 nC / c.
A distorted helical ferroelectric liquid crystal (DHF liquid crystal) B having m ² , a response time of 90 μs, and a saturation voltage of 3 V was used. The liquid crystal cell is
An ordinary manufacturing method comprising a TFT array substrate and a CF substrate was used. A CF substrate having an ITO electrode (opposite electrode) formed on the entire surface was used, and an 80 nm thick SiO ₂ film was formed on the ITO electrode by a sputtering method. A low pretilt polyimide film was formed as a liquid crystal alignment film on each of the ITO electrode layer of the TFT array substrate and the SiO ₂ layer of the CF substrate. The rubbing process, the cell gap conditions, and the like were the same as in the first embodiment.

The drive system used was a VGA compatible (upper and lower two-part drive) with a maximum applied voltage of ± 3 V and a selection time of 64 μs for one line. The scanning line driving waveform illustrated in FIG. 6B was input to each scanning line 11. The reset pulse 21 was partially overlapped by a plurality of lines, and the pulse width was set to about 200 μs to secure a sufficient reset time.

When the reset pulse 21 is input to the scanning line 11, the n-channel TFT element 14 turns off and the p-channel TFT element 17 turns on. p-channel TFT
When the element 17 is turned on, the pixel electrode 15 is connected to the auxiliary capacitance line 13. Then, the reset operation is performed by setting the pixel applied voltage to a voltage near 0V. This behavior is
This is performed by fixing the potential to the same potential as the counter electrode potential.

Next, the signal write pulse 22 causes n
The channel TFT element 14 is turned on, an image signal corresponding to the gradation of the image is input from the signal line 12 to the pixel electrode 15, and an image is displayed.

The image signal was set to an alternating current centering on the potential of the counter electrode, and in each frame, a signal line inversion for inverting the signal polarity was performed for each signal line, and driving was performed to display an image.
A contrast ratio of 70: 1 and a response speed of 1 ms or less were obtained, and no afterimage due to the step response was observed.

Fourth Embodiment FIG. 7 is a plan view showing a configuration of a sub-pixel on a TFT array. FIG. 8A is a circuit diagram showing an equivalent circuit of a 4-row, 2-column portion in the sub-pixel group.

This embodiment is characterized in that an n-channel TFT element 14 connected to the same pixel electrode 15 and a p-channel TFT
The gate electrode of the FT element 17 is the scanning line 11 of a different pixel row.
And the pixel electrode 15 is connected to the auxiliary capacitance line 13 of a different pixel row via the p-channel TFT element 17.

For the semiconductor layer of each TFT element, poly-Si was used instead of a-Si used in the above embodiment. n-channel TFT element 14 and p-channel TF
By adjusting the initial carrier concentration and thickness of the poly-Si layer and the thickness of the gate insulating film, the T element 17 is adjusted so that the threshold voltage difference between the two TFTs becomes larger than twice the signal amplitude at the time of driving. Created. As will be described later, since the signal amplitude is ± 3 V in the drive system of the present embodiment, the difference between the threshold voltages is set to 6 V or more. The method for manufacturing the liquid crystal material and the cell was the same as in the first embodiment.

The drive system used was XGA-compatible (upper and lower two-part drive) with a maximum applied voltage of ± 3 V and a line selection time of 42 μs. The scanning line driving waveform illustrated in FIG. 8B was input to each scanning line 11. The reset pulse 21 was partially overlapped by a plurality of lines, and the pulse width was set to about 250 μs to secure a sufficient reset time.

When a reset pulse 21 is input to the scanning line 11, the n-channel TFT element 14 remains off and 1
The p-channel TFT element 17 connected to the pixel on the row is turned on. Then, when the p-channel TFT element 17 is turned on, the pixel electrode 15 is connected to the auxiliary capacitance line 13.

When the p-channel TFT element 17 is on, the potential of the auxiliary capacitance line 13 is kept almost the same as the potential of the counter electrode without moving, and the voltage applied to the pixel is set to a voltage near 0 V. Done.

Next, the signal writing pulse 22 causes n
This is performed by turning on the channel TFT element 14 and turning off the p-channel TFT element, and inputting an image signal according to the gradation of the image from the signal line 12 to the pixel electrode 15.

The image signal was set to an alternating current with the potential of the counter electrode as the center, and the pixels were driven by performing pixel inversion (dot inversion) for inverting the signal polarity for each pixel in each frame to display an image.

As a result of the image display, a contrast ratio of 70: 1 and a response speed of 1 ms or less were obtained, and no afterimage due to the step response was observed. [Comparative Example 1-1] One TFT element and one pixel per pixel
A cell was prepared under the same conditions as in the first embodiment, except that a conventional array structure having a scanning line and a signal line each was used. When normal driving was performed without performing a reset operation, the contrast ratio was reduced to 20: 1, and an afterimage due to a step response was observed. Next, driving was performed in which the first half of the selection time of one line was used for the reset operation. The afterimage due to the step response has been eliminated, but the contrast ratio is 25:
Only about 1 was obtained.

[Comparative Example 1-2] A reset TFT using a p-channel TFT element as a signal writing TFT element
A cell using the same array structure, cell configuration, and circuit configuration as in the first embodiment is used under the same conditions, except that an n-channel TFT element is used as the element and the W / L of the p-channel TFT element is larger than that of the n-channel TFT element. Created in. The same driving as in the first embodiment was performed, but the afterimage due to the step response was eliminated, but the contrast ratio was only about 50: 1.

Therefore, it is understood that it is preferable to use an n-channel TFT element as the signal writing TFT element and use a p-channel TFT element as the reset TFT element.

Next, an embodiment of a liquid crystal display element having two switching elements, a signal writing switching element and a reset switching element, and each switching element is connected to a different scanning line will be described.

[Fifth Embodiment] The liquid crystal display element of the present embodiment has 1024 × 768 pixels arranged in a matrix (XGA).

FIG. 9 is a plan view showing a structure of a TFT array substrate of a liquid crystal display device according to a fifth embodiment of the present invention. FIG. 10 shows an equivalent circuit of a portion of three columns in the sub-pixel group.

The first scanning lines 31 and the second scanning lines 32 are formed in the row direction, and the signal lines 12 are formed in the column direction. The auxiliary capacitance line 13 is formed in the row direction, and is connected to the common auxiliary capacitance line 13 at an end.

The first scanning line 31 is connected to the gate electrode of the signal writing TFT element 33. Also, the signal line 12
Are connected to the pixel electrode 15 via the signal writing TFT element 33.

The second scanning line 32 is connected to the gate electrode of the reset TFT element 34. The auxiliary capacitance line 13 is connected to the pixel electrode 1 via the reset TFT element 34.
5 is connected. The pixel electrode 15 is connected to the storage capacitor 1.
6 is connected to the auxiliary capacitance line 13.

The first scanning lines 31 are combined into three bundles from the end of the TFT array substrate and connected to the first scanning line driving IC 41, and the second scanning lines 32 are similarly combined into three bundles from the end of the array substrate. Connected to the second scanning line driving IC 42.

Signal writing and resetting TFT element 3
Reference numerals 3 and 34 are formed using an a-Si layer as a channel. The liquid crystal cell includes a TFT array substrate on which a TFT element and a pixel electrode are formed, and a C array on which a counter electrode is formed.
An F substrate is disposed to face and a liquid crystal material is injected between the two. The CF substrate has an overcoat layer, and a portion of the ITO facing the signal lines and the TFT elements of the array substrate
The electrode was removed by etching. Further, a 30 nm thick SiO ₂ film is formed on the ITO electrode layer by sputtering.

On the ITO electrode of the TFT substrate and on the SiO ₂ layer of the CF substrate, a low pretilt polyimide film was formed as a liquid crystal alignment film. The alignment film of each substrate was rubbed in the cell longitudinal direction in the direction opposite to the injection direction. However, the rubbing axes of both substrates were shifted by about 10 °. And
The cell gap was set to 2.0 μm by scattering resin-coated silica spacers.

As the liquid crystal material, spontaneous polarization 200 nC / c
A threshold antiferroelectric liquid crystal A (manufactured by Mitsui Petrochemical) having m ² , a response time of 100 μs, and a saturation voltage of 4 V was used. The driving system has a maximum applied voltage of ± 5 V and a selection time of one line of 42.
An XGA-compatible one (upper and lower two-part drive) of μs was used.
The driving waveform shown in FIG. 11 is input to each first scanning line 31 of the equivalent circuit shown in FIG.
The driving waveform illustrated in FIG. Note that the reference numerals added to the drive waveforms in FIG. 11 correspond to the first and second scanning lines 31 and 32 denoted in FIG.

This drive waveform is applied to the reset TFT element 3
4 and a signal write pulse 22 for turning on the signal writing TFT element 33. The reset pulse 21 is partially overlapped by a plurality of lines, and the pulse width is set to about 300 μs to sufficiently secure the reset time.

When the reset pulse 21 is input to the second scanning line 32, the signal writing TFT element 33 remains off and the reset TFT element 34 turns on. And
When the reset TFT element 34 is turned on, the pixel electrode 15 is connected to the auxiliary capacitance line 13. And the auxiliary capacitance line 13
The reset operation is performed by setting the potential of the pixel to the same potential as the counter electrode potential with almost no change, and setting the pixel applied voltage to a voltage near 0 V.

Next, the signal writing pulse 22 input to the first scanning line 31 generates a signal writing TFT element 33.
Is turned on, and an image signal corresponding to the gradation of the image is input from the signal line 12 to the pixel electrode 15 to perform image display.

The image signal was set to an alternating current centered on the potential of the counter electrode, and the image was displayed by driving by performing signal line inversion for inverting the signal polarity for each column in each frame. The potential of the auxiliary capacitance line was the same as the potential of the counter electrode, and was kept constant.

As a result of the image display, a contrast ratio of 70: 1 and a response speed of 1 ms or less were obtained, and no afterimage due to the step response was observed. According to the liquid crystal display device of the present embodiment, the first scanning line and the second scanning line have different ICs.
By driving the first scanning line and the second scanning line on the same side of the array substrate and providing two systems, the driving by the conventional scanning line driving IC becomes possible. It is possible to suppress an increase in cost. That is, since the first and second scanning lines are alternately arranged in the display area, if terminals for connecting the driving ICs are provided on the same side of the substrate end, the number of driving ICs increases due to an increase in the number of terminals. A scanning line drive IC with a different specification from the past is required,
This leads to higher costs.

The same effect can be obtained by installing the two terminals on different sides of the array substrate, or separating each terminal into two systems by a peripheral circuit. [Sixth Embodiment] The liquid crystal display device of the present embodiment is 640
× 480 pixels are arranged in a matrix (VGA).

FIG. 12 is a circuit diagram showing an equivalent circuit of a liquid crystal display according to the sixth embodiment of the present invention. 12, the same parts as those of FIG. 11 are denoted by the same reference numerals, and the description thereof will be omitted. Since the configuration of the sub-pixel is the same as that of the fifth embodiment, the illustration is omitted.

This embodiment is characterized in that the second scanning line 32
Is connected outside the pixel region to the first scanning line 31 separated by three pixel rows via the bypass line 51. The first and second scanning lines 3 are provided at the end of the TFT array substrate.
Terminals 1 and 32 are provided with a common terminal. That is, the same number of scanning line terminals as the number of pixel rows are provided, and there is no difference between a conventional scanning line and a single liquid crystal display element.

Further, the first and second dummy scanning lines 35 and 36 are provided in the region where there is no pixel at the uppermost portion and the lowermost portion in order to make the writing characteristics the same as those at the central portion. The lowermost first scanning line 31 and the uppermost second scanning line 32 are
They are connected by a bypass line 51a. FIG.
As shown in FIG. 3, the lowermost first scanning line 31 and the uppermost second scanning line 32 are not connected, and the uppermost second scanning line 32 is not connected.
And the first scanning line 31 of the lowermost layer are respectively connected to the first and second scanning lines.
May be connected to the dummy scanning lines 35 and 36.

The terminals at the ends of the array substrate are separately provided for the first scanning line 31 and the second scanning line 32, and the bypass line 5
1 may be provided on a peripheral circuit board and connected to a drive IC, and the same effect as in the above example can be obtained in terms of display characteristics.

Further, in the case of the upper and lower two-part drive in which the signal line 12 is separated at the center, the terminals of the scanning lines corresponding to the same upper and lower positions are connected to each other on the array substrate or on the peripheral circuit, so that the scanning is performed. It is possible to halve the number of line drive ICs.

The method of manufacturing each TFT element and liquid crystal cell was the same as in the fifth embodiment. An antiferroelectric liquid crystal C having a spontaneous polarization of 140 nC / cm ² , a response time of 120 μs, and a saturation voltage of 6 V was used as a liquid crystal material. After the cell formation, the scanning line group was connected to the scanning line driving IC from the end of the array substrate via the peripheral circuit substrate.

The scanning line driving IC has a maximum applied voltage of ± 5 V,
A VGA-compatible (upper and lower divided drive) with a selection time of 64 μs per line was used. The drive waveform shown in FIG. 14 was input to each scanning line terminal, and a reset operation and a write operation were performed. The pulse 38 in this waveform is a pulse for turning on the signal writing TFT element 33 connected to the first scanning line 31, and is also applied to the second scanning line 32 separated by three pixel rows. This is a pulse for turning on the connected reset TFT element 34.

The pulse 38 input to the second scanning line 32
Is the same as the writing pulse of the first scanning line 31 of the pixels separated by three pixel rows, and the reset time is about 64 μs. The reset operation was performed by setting the potential of the auxiliary capacitance line 13 to the same potential as the counter electrode potential without substantially moving the same, and setting the pixel applied voltage to a voltage near 0 V. The liquid crystal continues to respond for about 192 μs between the reset operation and the write operation, whereby the liquid crystal is almost reset.

The image signal input from the signal line was set to an alternating current centering on the potential of the counter electrode, and the image was displayed by driving the signal line by inverting the signal polarity for each column in each frame.

As a result of the image display, a contrast ratio of 80: 1 and a response speed of 1 ms or less were obtained, and no afterimage due to the step response was observed. Further, an array structure was prepared in which the auxiliary capacitance lines of each row were independent without connecting them all on the substrate, and were taken out from another terminal so that each auxiliary capacitance line 13 could be driven independently. Other preparation conditions were the same as above, and the same driving was performed. However, the reset operation was performed by setting the pixel applied voltage to 電 圧 of the saturation voltage of the liquid crystal having the polarity opposite to the signal polarity of the previous frame. This reset operation was performed by shifting the potential of the auxiliary capacitance line to half the saturation voltage of the liquid crystal.

The image signal was set to an alternating current with the counter electrode potential at the center, and the image was displayed by performing row inversion (H inversion) for inverting the signal polarity for each row in each frame.
As a result of the image display, a contrast ratio of 80: 1 and 1 ms
The following response speed was obtained, and no afterimage due to the step response was observed.

According to the present embodiment, by connecting the second scanning line to the first scanning line of a different pixel row, the reset operation can be performed using the conventional driving IC, and the cost is increased. Can be suppressed.

[Seventh Embodiment] The liquid crystal display element of the present embodiment has 640 × 480 pixels arranged in a matrix (VGA).

FIG. 15 is a circuit diagram showing an equivalent circuit of a liquid crystal display device according to the seventh embodiment of the present invention. 15, the same parts as those of FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted. Since the structure of the sub-pixel is the same as that of the fifth embodiment, the illustration thereof is omitted.

The feature of this embodiment is that four second scanning lines 32 are connected to bypass lines 52 outside the pixel area, and four bypass lines 52 each having a diode 39 interposed therebetween. That is, it is connected to the bypass line 53. The four bypass lines 53 connected to the same bypass line 52 are connected to the first scanning line 31 to which a signal write pulse is continuously applied.

At the end of the TFT array substrate, a common terminal for the first and second scanning lines 31 and 32 is provided. That is, a conventional scanning line is the same as a single-system liquid crystal display element in that the same number of scanning line terminals as pixel rows are provided.

The terminals at the end of the array substrate are separately provided for the first scanning line 31 and the second scanning line 32, and the diode 39 is provided.
May be provided on the peripheral circuit board and connected to the driving IC, and the display characteristics are the same as those in the above example.

The uppermost second scanning line 32 is connected to the lowermost first scanning line 31 via a bypass line 52a. In addition, as shown in FIG.
Is not connected to the uppermost second scanning line 32, and the uppermost second scanning line 32 and the lowermost first scanning line 31 are respectively connected to the first and second dummy scanning lines. 35,3
6 may be connected.

The method of manufacturing each TFT element was the same as in the first embodiment. Spontaneous polarization 100 nC / c as liquid crystal material
A distorted helical ferroelectric liquid crystal (DHF liquid crystal) B having m ² , a response time of 90 μs, and a saturation voltage of 3 V was used. The liquid crystal cell is
An ordinary manufacturing method comprising a TFT array substrate and a CF substrate was used. A CF substrate having a solid ITO electrode was used, and an SiO ₂ film was sputtered to a thickness of 80 nm on the ITO electrode layer. A low pretilt polyimide film was formed as a liquid crystal alignment film on each of the ITO electrode layer of the TFT substrate and the SiO ₂ layer of the CF substrate. The rubbing / cell gap conditions were the same as in the fifth embodiment.

The drive system used was a VGA-compatible (vertical two-part drive) with a maximum applied voltage of ± 5 V and a selection time of 64 μs per line. The drive waveform shown in FIG. 17 was input to each scanning line terminal, and a reset operation and a write operation were performed.

The four second scanning lines 32 connected to the same bypass line 52 are connected via the bypass line 53 to the four first scanning lines 31 to which the pulse 38 is continuously input. ing. Therefore, four pulses 38 are continuously input to the second scanning lines 32 connected to the same bypass line 52. That is, about 25 lines are provided for the four second scanning lines 32.
A reset pulse of 6 μs is input, and a reset operation is performed simultaneously on four pixel rows.

The reset operation was performed by setting the potential of the auxiliary capacitance line 13 to the same potential as the counter electrode potential without substantially moving the potential, and setting the pixel applied voltage to around 0V. The liquid crystal continues to respond between the reset operation and the write operation, whereby the liquid crystal is almost reset.

The image signal was set to an alternating current with the counter electrode potential at the center, and in each frame, the image signal was driven by performing signal line inversion for inverting the signal polarity for each column in each column. As a result of the display, a contrast ratio of 70: 1 and a response speed of 1 ms or less were obtained, and no afterimage due to the step response was observed.

According to the present embodiment, the second scanning lines are continuously selected, the reset time can be sufficiently long, and the plurality of second scanning lines are different from the plurality of first scanning lines of different pixel rows. By connecting to a scanning line, a conventional driving IC
Can be used.

[Eighth Embodiment] The liquid crystal display element of the present embodiment has 640 × 480 pixels arranged in a matrix (VGA).

FIG. 18 is a circuit diagram showing an equivalent circuit of a liquid crystal display device according to the eighth embodiment of the present invention. In FIG. 18, the same parts as those in FIG. Since the configuration of the sub-pixel is the same as that of the fifth embodiment, the illustration is omitted.

This embodiment is characterized in that the first scanning line 31
However, it is connected to four second scanning lines 32 of different pixel rows outside the pixel region via the bypass line 54 in which the diode 39 is inserted. Therefore, the second scanning lines 32 include four first scanning lines 31 belonging to different pixel rows.
The book is connected. Note that the four first scanning lines 31 connected to the second scanning lines 32 are continuously selected when displaying an image.

A common terminal for the first and second scanning lines 31 and 32 is provided at the end of the array substrate. That is,
Although the scanning lines of pixel rows × 2 rows are formed on the TFT array substrate, the conventional scanning lines are different from the liquid crystal display elements of one system in that the same number of scanning line elements as the pixel rows are provided. There is no place.

The terminals at the ends of the array substrate are provided separately for the first scanning line 31 and the second scanning line 32, and the bypass line with the diode interposed is provided on the peripheral circuit substrate to form a drive IC.
It is also possible to adopt a method of connecting to the display device, and the same effect as in the above example can be obtained in terms of display characteristics.

The lowermost first scanning line 31 and the uppermost second scanning line 32 are connected to a first dummy scanning line 35 and a second dummy scanning line 36, respectively. Name T
The method for manufacturing the FT element, the liquid crystal material, and the cell was the same as in the fifth embodiment.

The drive system used was VGA compatible (upper and lower two-part drive) with a maximum applied voltage of ± 5 V and a line selection time of 64 μs. The scanning line driving waveform shown in FIG. 19 was input to each first scanning line 31.

A pulse (pulse width 64) is applied to the first scanning line 31.
μs) 38, the pulse 38 is also input to the four second scanning lines 32 connected via the bypass line 54. Accordingly, the second scanning line 32 includes the bypass line 5
Since the pulse 38 is continuously input from the four first scanning lines 31 connected through the line 4, the pulse width 256 (=
A pulse of 64 μs × 4) μs is input, and a reset operation is performed. Also, the liquid crystal is almost reset by continuing to respond while the reset pulse and the write pulse are input.

The reset operation was performed by keeping the potential of the auxiliary capacitance line 13 at the same potential as the potential of the counter electrode without substantially moving the potential, and setting the potential applied to the pixel to around 0V. At the time of the writing operation, the image signal was set to an alternating current with the counter electrode potential as the center, and the pixels were driven by performing pixel inversion (dot inversion) for inverting the signal characteristics for each name pixel in each frame to perform image display. The potential of the auxiliary capacitance line 13 was the same as the potential of the counter electrode, and was kept constant.

As a result of the image display, a contrast ratio of 80: 1 and a response speed of 1 ms or less were obtained, and no afterimage due to the step response was observed. Next, the number of pixels is set to 1024.
× 768 (XGA), and the switching and signal writing TFT elements were changed to those using a poly-Si layer. The circuit configuration was the same as in the above embodiment, but all the peripheral circuits and drive ICs in the above embodiment were installed on an array substrate. Other points such as a liquid crystal material and a cell forming method are the same as those of the above embodiment.

The drive system used was an XGA-compatible (upper and lower two-part drive) with a maximum applied voltage of ± 5 V and a line selection time of 42 μs. The scanning line drive waveform illustrated in FIG. 19 was input to each scanning line 31 of the equivalent circuit, and the writing and resetting operations were performed.

In the case of XGA, the reset pulse width is about 168
The reset time was shorter than that in the case of the VGA, but the liquid crystal was almost reset because the liquid crystal continued to respond between the reset and the writing.

As a result of the image display, the contrast ratio was 70:
1. The response speed was 1 ms or less, and no afterimage due to the step response was observed. According to the present embodiment, the interval between the reset operation and the signal writing operation is the same, and the response of the liquid crystal after the reset operation becomes uniform regardless of the pixel. Also,
By providing the circuits on the array substrate without using the peripheral circuit substrate, the drive circuit portion can be simplified.

[Comparative Example 2-1] One TF per pixel
A cell was prepared under the same conditions as in the fifth embodiment except that a conventional array structure having a T element and one scanning line and one signal line was used. When normal driving was performed without performing the reset operation, the contrast ratio was reduced to 20: 1, and an afterimage due to a step response was observed.

Next, a drive was performed in which the first half of the selection time of one line was used for the reset operation. Although the afterimage due to the step response was eliminated, a contrast ratio of only about 25: 1 was obtained.

[Comparative Example 2-2] The terminals of the first scanning line and the second scanning line at the ends of the array substrate are provided separately from each other without being the same, and the two scanning lines are not connected on the peripheral circuit substrate without being connected. Except for connecting to the driving IC, the same array structure, cell configuration, and circuit configuration as in the sixth embodiment were used, and cells were created under the same conditions. When the same driving as in the sixth embodiment was performed,
The afterimage due to the step response was eliminated, and a contrast ratio of 70: 1 was obtained. Similarly, in the seventh and eighth embodiments, image display was performed under the same conditions except that the same change as described above was performed, and similar results were obtained.

However, it is necessary to develop a dedicated driving circuit system / IC, for example, because the specification of the noise IC is different from the conventional one, the conventional IC cannot be used, and the driving waveform is different.
It has been found that increasing the number increases the cost.

Note that the present invention is not limited to the above embodiment. For example, in the case where the reset operation is performed with the potential of the auxiliary capacitance line set to the same potential as the counter electrode potential and kept constant, the wiring may be wired in parallel with the scanning line as in the related art, or may be wired so as to intersect with the scanning line. It is also possible.

In the fifth to eighth embodiments, a switching element such as TFD and MIM can be used in addition to the TFT element. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0131]

As described above, according to the present invention, two switchings (TFTs) for resetting and signal writing are provided.
By providing the element and performing the reset operation and the signal write operation at the same time, the reduction of the effective applied voltage is prevented, the afterimage due to the "step response" is eliminated, and the high contrast can be obtained at a lower voltage.

[Brief description of the drawings]

FIG. 1 is a plan view showing an array substrate of a liquid crystal display device according to a first embodiment.

FIG. 2 is a diagram showing an equivalent circuit and an input waveform of the liquid crystal display element according to the first embodiment.

FIG. 3 is a plan view showing an array substrate of a liquid crystal display device according to a second embodiment.

FIG. 4 is a view showing an equivalent circuit and an input waveform of a liquid crystal display element according to a second embodiment.

FIG. 5 is a plan view showing an array substrate of a liquid crystal display device according to a third embodiment.

FIG. 6 is a view showing an equivalent circuit and an input waveform of a liquid crystal display element according to a third embodiment.

FIG. 7 is a plan view showing an array substrate of a liquid crystal display device according to a fourth embodiment.

FIG. 8 is a diagram showing an equivalent circuit and an input waveform of a liquid crystal display element according to a fourth embodiment.

FIG. 9 is a plan view showing an array substrate of a liquid crystal display device according to a fifth embodiment.

FIG. 10 is a diagram showing an equivalent circuit of a liquid crystal display element according to a fifth embodiment.

FIG. 11 is a view showing an input waveform to a liquid crystal display element according to a fifth embodiment.

FIG. 12 is a diagram showing an equivalent circuit of a liquid crystal display device according to a sixth embodiment.

FIG. 13 is a view showing an equivalent circuit of a liquid crystal display element according to a sixth embodiment.

FIG. 14 is a view showing an input waveform to a liquid crystal display element according to a sixth embodiment.

FIG. 15 is a view showing an equivalent circuit of a liquid crystal display element according to a seventh embodiment.

FIG. 16 is a diagram showing an equivalent circuit of a liquid crystal display element according to a seventh embodiment.

FIG. 17 is a view showing an input waveform to a liquid crystal display element according to a seventh embodiment.

FIG. 18 is a diagram showing an equivalent circuit of a liquid crystal display element according to the eighth embodiment.

FIG. 19 is a view showing an input waveform to a liquid crystal display element according to an eighth embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 scanning line 12 signal line 13 auxiliary capacitance line 14 n-channel TFT element for signal writing 15 ITO pixel electrode 16 auxiliary capacitance 17 reset p-channel TFT element 21 reset pulse 22 signal writing pulse DESCRIPTION OF SYMBOLS 31 ... 1st scanning line 32 ... 2nd scanning line 33 ... TFT element for signal writing 34 ... TFT element for reset 35 ... 1st dummy scanning line 36 ... 2nd dummy scanning line 37 ... bypass line 38 ... Selection pulse 39 Diode 40 Bypass line 41 First scan line drive IC 42 Second scan line drive IC

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Rieko Iida 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside Toshiba Production Technology Laboratory Co., Ltd.

Claims (3)

[Claims] 1. An active matrix type liquid crystal display device using a thin film transistor and a liquid crystal material of a chiral smectic C phase or a sub phase thereof, comprising a p-channel or n-channel thin film transistor.
Signal writing TFT connected between signal line and pixel electrode
A liquid crystal display element comprising: an element; and a reset TFT element formed of a thin film transistor having a channel different from that of the signal writing TFT element and connected between the pixel electrode and an auxiliary capacitance line. . 2. An active matrix liquid crystal display device using a chiral smectic C phase or a liquid crystal material of a sub phase thereof, wherein the liquid crystal display device is connected between a first scanning line, a signal line, and a pixel electrode,
A switching element for signal writing controlled by the selected first scanning line, a second scanning line, and a switching element connected between the pixel electrode and the storage capacitor, and connected by the selected second scanning line. A liquid crystal display device comprising: a reset switching device to be controlled. 3. A second scanning line of one or more pixel rows is connected to a first scanning line of one or more different pixel rows directly or via a diode. The liquid crystal display device according to claim 2.