JPH11307736A - Method for manufacturing semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Problem] Unless a desired accurate shape or flat surface is obtained, not only does the characteristic of the capacitor vary, making fine patterning difficult, but also an interlayer insulating film and wiring on the capacitor. When applying, the adhesion becomes poor. SOLUTION: After a selection transistor is formed on the surface of a silicon substrate 1 by a known technique, a first silicon oxide film 6 is formed as an interlayer insulating film to form a contact hole. Next, after the polysilicon is buried in the contact hole, the surface is flattened and a polysilicon plug 7 is formed. On this polysilicon plug 7, a tantalum silicon nitride film 8 was formed, and then an iridium film 9 and an iridium oxide film 10 were formed. Next, an SBT film 11 was formed on the iridium oxide film 10. A platinum film is formed on this,
The heat treatment step was performed in oxygen. Next, the platinum film serving as the upper electrode was sequentially processed by a dry etching method in the order of the upper electrode 12, the SBT film 11, the iridium oxide film 10, the iridium film 9, and the tantalum silicon nitride film 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device having a capacitor comprising a lower electrode, a dielectric film and an upper electrode.

[0002]

2. Description of the Related Art EPROM which is a conventional nonvolatile memory
The read time of an EEPROM, an EEPROM, a flash memory, or the like is comparable to that of a DRAM, but the write time is long, and high-speed operation cannot be expected. On the other hand, a non-volatile semiconductor memory device using a ferroelectric capacitor is comparable to a DRAM in both reading and writing, and can be expected to operate at high speed. As an electrode material for a ferroelectric capacitor, platinum has been widely used for both the upper electrode and the lower electrode because of its resistance in a high-temperature oxidizing atmosphere for crystallizing the ferroelectric.

On the other hand, as a ferroelectric material used for a ferroelectric capacitor, PbZr
_x Ti _1-x O ₃ (PZT) or newly SrBi ₂ Ta ₂ O ₉ (S
BT) and Bi ₄ Ti ₃ O ₁₂ (BIT) have attracted attention and are being actively studied.

A method of forming a ferroelectric film is MOD (Met
al Organic Deposition) method, sol-gel method, MOCVD method (Metal Organic)
Chemical Vapor Deposition
There are an n) method, a sputtering method, and the like. In any of the film forming methods, the oxide ferroelectric film needs to be crystallized by heat treatment in a high-temperature oxidizing atmosphere at about 600 ° C. to 800 ° C.

[0005] Among the above ferroelectric films, SBT
Has an advantage that it has better fatigue characteristics and can be driven at a low voltage than PZT, and is expected to be applied to a highly integrated ferroelectric memory device. However, in a state where the SBT film is only crystallized and the upper electrode is formed, there is a problem that the capacitor leakage current is large. Therefore, conventionally, a method has been adopted in which the upper electrode is formed over the entire surface of the substrate, processed into a desired shape, and then subjected to a heat treatment in an oxygen atmosphere to improve the leak current characteristics.

[0006]

However, if a heat treatment step is performed after processing the platinum upper electrode into a desired shape as in the prior art, the platinum of the upper electrode is recrystallized during the heat treatment step, so that grain growth occurs. Then, there is a problem that the end portion is distorted due to contraction from the originally desired shape, or morphology is deteriorated, and flatness is deteriorated.

[0007] In addition, the processing of platinum of the upper electrode is generally performed by using a dry etching method. In this case, the surface of the SBT underlying the upper electrode is also exposed due to overetching during the platinum etching. The exposed SBT surface is smooth because the exposed SBT is etched. However, when the heat treatment step is performed thereafter, there is a problem that the SBT is also recrystallized and the surface morphology is deteriorated.

[0008] As described above, if a desired accurate shape and a flat surface cannot be obtained, not only the characteristics of the capacitor will vary, but also fine patterning will be difficult.
When an interlayer insulating film or wiring is formed on the capacitor, the adhesion is deteriorated, which causes peeling.

On the other hand, in order to realize high integration of ferroelectric memory elements, it is required to adopt a stack type structure. In the case of a stack type structure, electrical conduction between the capacitor portion and the select transistor is obtained using a polysilicon plug or the like. In this case, a barrier metal that prevents the reaction between the lower electrode or the ferroelectric film and the plug and prevents the diffusion of each element constituting the capacitor, and oxygen that diffuses from the atmosphere of the crystallization heat treatment at the time of forming the capacitor. Accordingly, a capacitor lower electrode that does not oxidize itself, the barrier metal, and the plug surface is also required.

However, since the barrier metal and the lower electrode do not have sufficient resistance for a long time in a high-temperature oxidizing atmosphere, it is necessary to lower the temperature of all the heat treatment steps after the formation of the lower electrode. However, if a heat treatment step for reducing leakage after forming the upper electrode is performed, there is a problem that a ferroelectric capacitor having excellent leakage characteristics cannot be obtained.

[0011]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device having a capacitor comprising a lower electrode, a dielectric film, and an upper electrode. After forming the dielectric film, depositing the upper electrode material on the dielectric film, and performing a heat treatment at a predetermined temperature and then patterning the upper electrode material into a predetermined shape to form an upper electrode And characterized in that:

Further, in the method of manufacturing a semiconductor memory device according to the present invention, the heat treatment is performed at 400 ° C. or more and 800 ° C. or less. This is a method for manufacturing an element.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor memory device according to the present invention will be described based on an embodiment.

FIG. 1 is a diagram showing the first half of a manufacturing process of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an n-type silicon substrate, and 2 denotes an element isolation formed on the surface of the n-type silicon substrate. LOCOS oxide film, 3 is a gate oxide film,
4 is a gate electrode, 5 is a source / drain region, 6 is a first silicon oxide film formed as an interlayer insulating film on the silicon substrate 1, and 7 is a contact between the source / drain region 5 and the capacitor lower electrode. 8 is a tantalum silicon nitride film (TaSi) formed as a diffusion barrier on the polysilicon plug.
N) and 9 are an iridium (Ir) film formed as a diffusion barrier and an oxygen blocking film, 10 is a lower electrode of a ferroelectric capacitor and an iridium oxide (IrO _x ) film formed as an oxygen blocking film, and 11 is a lower electrode. An SBT film which is a ferroelectric film formed thereon, 12 an upper electrode using platinum formed on the SBT film, 13 a titanium oxide film for diffusion of the ferroelectric film and prevention of a silicide reaction, 14 is a second silicon oxide film formed as an interlayer insulating film, 15 is a titanium film as an adhesion layer between the second silicon oxide film and the upper electrode, 16 is a platinum film as a drive line, and 17 is an adhesion layer. A titanium nitride film which is an anti-reflection film, 18 is a third silicon oxide film formed as an interlayer insulating film, and 19 is an aluminum film formed for making contact with source / drain regions. A lead-out electrode. In this embodiment, an n-type silicon substrate will be described, but the present invention is not limited to this.

Hereinafter, the manufacturing process of the semiconductor memory device of the present invention will be described with reference to FIG.

First, a LOCOS oxide film 2 having a thickness of about 500 ° is formed on the surface of an n-type silicon substrate 1 to form an element isolation region. Next, after a select transistor including a gate oxide film 3, a gate electrode 4, a source / drain region, and the like is formed by a known technique, a CVD (Che) is used as an interlayer insulating film.
A first silicon oxide film 6 is formed to a thickness of about 5000 ° by a physical vapor deposition method, and a contact hole having a diameter of 0.5 μm is formed by using a photolithography technique and a dry etching technique. Next, after the polysilicon is buried in the contact hole by the CVD method, the surface is flattened by the CMP method, and the polysilicon plug 7 is formed.

On this polysilicon plug 7, a tantalum silicon nitride film 8 having a thickness of 700 ° is formed by DC magnetron reactive sputtering, and then an iridium film 9 having a thickness of 300 ° is formed by DC magnetron reactive sputtering. Was formed, and an iridium oxide film 10 having a thickness of 1000 Å was formed by DC magnetron reactive sputtering.

The formed iridium oxide film 10 is an electrode having very smooth conductivity, and the iridium film 9 thereunder is oxidized on the surface of the tantalum silicon nitride film 8 when the iridium oxide film 10 is formed. And diffusion of oxygen from the oxygen atmosphere during firing of the ferroelectric is prevented. The tantalum silicon nitride film 8 is a barrier metal that prevents a silicide reaction between the iridium film 9 and the polysilicon plug 7.

Next, a MOD raw material solution of SBT is applied onto the iridium oxide film 10 by a MOD method using a spinner.
Coating was performed at 000 rpm, and drying was performed at 250 ° C. for 5 minutes. The first firing is performed at 500 ° C. in an oxygen atmosphere at atmospheric pressure.
Performed for 0 minutes. Then, as a heat treatment for crystallization,
RTA (Rapid Thermal Annealin)
By g) method, a second baking at 670 ° C. for 10 minutes was performed in an atmosphere containing oxygen.

The steps from the application to the heat treatment for crystallization were repeated three or four times so that the SBT film 11 had a desired thickness of about 1800 °. The method of forming the SBT film 11 is not only the MOD method but also the sputtering method and the MOCV method.
The D method may be used. A platinum film was formed on the ferroelectric film by DC magnetron reactive sputtering at 1500 °, and a third film was formed.
Was subjected to a heat treatment step in a furnace at 700 ° C. for 30 minutes in oxygen.

The third firing temperature is 400 ° C. to 80 ° C.
Desirably, the temperature is 0 ° C. At a temperature lower than 400 ° C., there is a problem that the capacitor leakage current is not sufficiently improved. At a temperature higher than 800 ° C., recrystallization of not only the platinum film as the upper electrode but also the ferroelectric SBT film itself is performed. Morphology deteriorates. In addition, problems such as aggregation of the lower electrode and oxidation of the barrier metal also occur, and a problem that capacitor characteristics cannot be obtained also occurs.

Next, using photolithography technology,
Patterning with a photoresist was performed, and a platinum film serving as an upper electrode was processed into a 2.7 μm square by dry etching to form an upper electrode 12. Similarly, the SBT film 11 is 3.2 μm square, and the iridium oxide film 10 serving as a lower electrode is formed.
The iridium film 9 as a diffusion barrier and the tantalum silicon nitride film 8 were processed into a 3.6 μm square.

Thereafter, a titanium oxide film 13 was formed by RF magnetron reactive sputtering to a thickness of 250 ° as a diffusion preventing film for each element constituting the ferroelectric capacitor. An ozone TEOS film having a thickness of 2000 .ANG. Is formed thereon as the second interlayer insulating film 14, and a titanium film 15 is formed thereon by RF magnetron reactive sputtering as a 250 .ANG. did.

Next, a titanium film 15, a second interlayer insulating film 14, and a titanium oxide film 13 are opened to a surface of the upper electrode 12 in a 1.2 μm square from the upper layer.

Next, a platinum film 16 serving as a drive line was formed to a thickness of 1000 ° by a DC magnetron reactive sputtering method. A titanium nitride film 17 was formed on the platinum film 16 by RF magnetron reactive sputtering. This is because the third layer formed on this upper layer
This improves the adhesion to the interlayer insulating film 18 and also functions as an antireflection film in a photolithography process. The titanium nitride film 17, the platinum film 16, and the titanium film 15 were patterned using a photolithography technique and a dry etching technique, and processed into a drive line shape. Here, in order to recover the damage and the ubiquity of the electric charges given to the ferroelectric capacitor in the steps after the processing of the upper electrode 12 to a normal state, the atmosphere is kept at 550 ° C. for 30 seconds in an oxygen atmosphere at atmospheric pressure. Was performed by the RTA method.

Next, a third interlayer insulating film 18 was formed, a contact hole was opened therein, and an aluminum lead electrode 19 from the source / drain region was formed by DC magnetron reactive sputtering.

By applying a triangular wave electric field between the drive line 16 connected to the upper electrode 12 of the ferroelectric capacitor formed by the above-described process and the aluminum extraction electrode 19 from the silicon substrate 1, the hysteresis shown in FIG. A loop was obtained. The applied triangular wave had a frequency of 3 V and a frequency of 75 Hz. As shown in FIG. 2, at 3 V, the saturation polarization value is 12.1 μC / cm ² , the remnant polarization value is 7.2 μC / cm ² , and the capacitor leakage current density is 1.4 × 10 ^{−7 as} shown in FIG. A / cm ² , and ferroelectricity with sufficient properties to be used as a ferroelectric capacitor was obtained.

On the other hand, for comparison, platinum of the upper electrode of the capacitor was processed into 2.7 μm square using the conventional manufacturing method, and then the third baking was performed at 600 ° C. for 10 minutes in an oxygen atmosphere. A sample was prepared. When the leakage current characteristics of this sample were measured, as shown in FIG. 4, a characteristic of 1.2 × 10 ⁻⁶ A / cm ² was obtained in the capacitor leakage current density, which was obtained by the manufacturing process of the present invention. The properties of the sample were shown to be better. FIG. 3A shows the leakage current characteristics when the applied voltage using the present invention is 0 to −10 (V), and FIG. 3B shows the leak current characteristics when the applied voltage using the present invention is 0 to +10 (V). Shows the leakage current characteristics when FIG. 4A shows that the applied voltage using the conventional technique is 0%.
The graph shows leakage current characteristics when the voltage is set to -10 (V), and FIG.
Shows the leakage current characteristics when

The difference in the leakage current mainly depends on the annealing temperature. Since the upper electrode platinum is uniformly deposited on the SBT, the presence of platinum that has entered the grain boundaries of the SBT film concentrates the electric field on that portion, leading to an increase in leakage current.

However, if a heat treatment is performed after the deposition of platinum, the platinum that has entered the SBT grain boundaries due to local aggregation is sucked upward, so that the electric field concentration is alleviated and the leak characteristics are improved. Longer heat treatment temperature and time contribute to the improvement of leakage current characteristics. However, when the effect of the oxygen barrier of iridium and iridium oxide of this structure is not provided with the upper electrode platinum, the heat treatment has already been performed at a high temperature.
When the heat treatment is performed at a high temperature, the tantalum silicon nitride film, which suppresses the silicide reaction, is oxidized, and peels off from the upper portion due to its deposition expansion.

On the other hand, when the platinum as the upper electrode is left on the entire surface as in the present invention, oxygen diffusing from the atmosphere can be relaxed, so that a heat treatment at 700 ° C. is also possible. Further, when the platinum of the upper electrode is processed into a 2.7 μm square according to the SEM and the AFM image, in the conventional method, an average of 0.2 μm from the platinum pattern end of the upper electrode
m, a shrinkage of 0.4 μm at the maximum was observed, and the average particle diameter of platinum was as large as 0.2 μm. However, in the upper electrode obtained by the manufacturing process according to the present invention, shrinkage was observed at the pattern edge. The average particle size of platinum was relatively smooth at 0.15 μm.

[0032] In an embodiment of the present invention, was used SrBi ₂ Ta ₂ O ₉ as the ferroelectric, as another _{dielectric, (Pb x La 1-x} ) (Zr y Ti 1-y) O ₃ , Bi ₄ T
i ₃ O ₁₂ , BaTiO ₃ , LiNbO ₃ , LiTaO ₃ , Y
_{MoO 3, Sr 2 Nb 2 O} 7, SrBi 2 (Ta x Nb 1-x) 2
O ₉ , (0 ≦ x, y ≦ 1), and SrTiO ₃ and (Ba _x Sr _1-x ) TiO ₃ , SrBi ₄ which are high dielectric materials
Similar effects can be obtained with Ti ₄ O ₁₅ (0 ≦ x ≦ 1).

Although the upper electrode is made of Pt, the material is not limited to Pt as long as it can bring out the ferroelectric characteristics. Rh, Ir, Ru or their oxides, alloys, oxides of alloys or Similar effects were obtained by using those combinations.

[0034]

As described above in detail, by subjecting the upper electrode platinum to a heat treatment process and then finely processing, the problem of shrinkage and deterioration of morphology accompanying the grain growth of the finer upper electrode platinum is reduced. I could avoid it. The heat treatment of the upper electrode platinum was performed in an oxygen atmosphere at 700 ° C. for 30 minutes, which was higher than before, to reduce capacitor leakage. Further, after performing the heat treatment step, the platinum of the upper electrode was processed by a dry etching method, and there was no subsequent high-temperature heat treatment step, so that a very smooth surface was obtained in the exposed portion of the SBT surface. Since the capacitor was manufactured with the desired dimensions and shape, there was almost no variation in the characteristics of the capacitor, and even when an interlayer insulating film required for forming wiring was laminated on the capacitor, phenomena such as delamination did not occur. I couldn't see it.

When the memory cell has a stack type structure, oxygen diffuses into the barrier metal thereunder through the SBT and the lower electrode, and hillocks are generated.
Heat treatment in a high-temperature oxidizing atmosphere is difficult due to limitations in oxidation resistance and heat resistance, but diffusion of oxygen to the capacitor lower electrode is eased by platinum in the upper electrode.

Therefore, conventionally, only a short heat treatment of about 600 ° C. could be performed at the highest, but the heat treatment can be performed in a high-temperature oxidizing atmosphere according to the present invention. Was achieved.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a semiconductor memory device having a ferroelectric capacitor.

FIG. 2 is a diagram showing a steeresis loop of ferroelectric characteristics of a ferroelectric capacitor using the present invention.

FIG. 3 (a) shows an applied voltage of 0 to -10 using the present invention.
FIG. 6 is a diagram showing a leakage current characteristic when (V) is set;
(B) is a diagram showing the leakage current characteristics when the applied voltage using the present invention is 0 to +10 (V).

FIG. 4 (a) shows an applied voltage of 0 to -1 using the prior art.
FIG. 9 is a diagram illustrating a leakage current characteristic when the voltage is set to 0 (V);
(B) shows an applied voltage of 0 to +10 (V) using the prior art.
FIG. 9 is a diagram showing a leakage current characteristic when “1” is set.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 n-type silicon substrate 2 LOCOS oxide film 3 gate oxide film 4 gate electrode 5 source / drain region 6 first silicon oxide film 7 polysilicon plug 8 tantalum silicon nitride film 9 iridium film 10 iridium oxide film 11 SBT film 12 upper electrode Reference Signs List 13 titanium oxide film 14 second silicon oxide film 15 titanium film 16 platinum film 17 titanium nitride film 18 third silicon oxide film 19 aluminum extraction electrode

Claims (2)

[Claims] 1. A method for manufacturing a semiconductor memory device having a capacitor comprising a lower electrode, a dielectric film, and an upper electrode, comprising: forming the dielectric film on the lower electrode; A method for manufacturing a semiconductor memory device, comprising: a step of depositing an upper electrode; and a step of forming a top electrode by performing a heat treatment at a predetermined temperature and then patterning it into a predetermined shape. 2. The method according to claim 1, wherein the heat treatment is performed at a temperature of 400.degree.
The method according to claim 1, wherein the method is performed at a temperature of 0 ° C or lower.