JPH11306134A - Serial communication system and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hold one of plural types of input information and to eliminate the need for adding a new signal against an instruction given from a master station, by allowing a slave station to send to information to the master station in response to a specified timing that is detected based on a control signal received from the master station. SOLUTION: A input selector circuit 1 of a slave station inputs information of parallel inputs A and B to an input latch circuit 2 in each bit via an AND-OR circuit and then selects information on the input A or B by means of a communication reset signal received from a master station and inputted to a counter circuit 6. In a communication operation mode, a communication reset signal is turned on and the parallel input information to be returned on decided by the execution of serial communication. When the information on the input B is selected, the communication reset signal is turned off. When the information of the input A is selected, a transfer clock is directly turned on and the count value of a master station timing counter is increased. Then the output equivalent to a single transfer clock is over. Thus, it's possible to omit the addition of a new control signal for selection of the parallel input information by setting a reset timing which is different from the transfer timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication apparatus and method for exchanging input / output information between a central processing unit and other electric units in the apparatus.

[0002]

2. Description of the Related Art Conventionally, a serial communication device in a device starts from a main device of serial communication called a master station of a central processing unit of the device and starts a serial communication device called a slave station of another electric unit. And a ring-shaped loop-type transmission path connected to the master station again via a plurality of slave stations. The means for exchanging information between the master station and a plurality of slave stations basically includes a shift register circuit for the slave station. On the other hand, the master station sequentially transfers the serial transmission data in synchronization with the serial transfer clock, and the slave station is configured such that the information exchange means performs a sequential shift operation on the transferred serial transfer data with the serial transfer clock. Have been. Further, the slave station latches (holds) the serial data when predetermined transfer data to be transferred to itself is shifted in, and outputs the parallel output of the slave station in a serial-parallel conversion manner. On the other hand, the parallel input data from the slave station to the master station is latched (held) at a preset timing, and before the transfer operation of the serial transfer data starts, or the transfer data from the master station is latched (held).
After that, the serial communication system is configured such that information is exchanged between the master station and a plurality of slave stations by loading the data into the shift register circuit of the slave station, synchronizing with the serial transfer clock, and returning the information to the master station. .

Next, in the case of a serial communication configuration in which the return information has an identifier code indicating the type of the slave station other than the parallel input data in order to identify the type of information returned from the slave station to the master station, Is a set of parallel output data and an identifier code, and from a slave station is a set of parallel input data and an identifier code, and one set of data for all slave stations is collected into a data length for serial communication. Information was exchanged by means. However, in recent years, since the identifier code of the slave station is invariable while the device is operating, information exchange is performed in advance by serial communication means using only the identifier code, and after the slave station arrangement order is recognized, the slave station It is configured to execute information exchange by serial communication means with a data length of input / output information in the arrangement order. As a result, the number of bits of the data length to be transferred is reduced, the time required for one serial communication is reduced, and the small number of bits reduces the probability of malfunction due to noise and the circuit cost due to the reduction in the size of component circuits. The configuration has many advantages such as reduction.

[0004] That is, one of the first parallel input information and the second parallel input information is selected and serially transferred from the slave station to the master station. If necessary, one of them is instructed by the master station. There has been proposed a serial communication system that selects selected parallel input information and performs information exchange with a master station based on the parallel input information. The contents of the configuration will be described below.

In the parallel input circuit configuration of the slave station, the input selector circuit selects the designated parallel input information content in accordance with an instruction signal transmitted from the master station, and transmits it to the next-stage input latch circuit. The input latch circuit latches and holds input information selectively transmitted by the input selector circuit at a timing controlled by a control unit that executes a timing shift for processing a serial communication signal of a slave station. Then, as load data of the shift register circuit located at the next stage, the data is latched and held at least until the timing at which the shift load is executed by the control means for executing timing output for processing the serial communication signal of the slave station. The parallel input information data loaded into the shift register is shifted back to the master station along with execution of the shift operation of the transfer data from the master station. As described above, since the master station instructs the slave station information required by its own control means and executes information exchange by serial communication, serial communication in which the number of bits of the transfer data length is reduced can be realized.

[0006]

However, when the signal processing circuit of the slave station is constituted by a gate array IC in the above conventional example, there are the following disadvantages.

A serial communication system has a plurality of slave stations and is attached to an electric unit base. Therefore, the serial communication system is configured by a gate array IC, thereby realizing low cost and space saving.

Further, a gate array IC constituting a slave station
As far as possible, it is inevitably required that a small-scale circuit and a small package can reduce cost and space as much as possible. Here, the circuit scale can be made small, but the problem is that the IC package is reduced to a small package as much as possible. The cost of the gate array IC is determined by the size of the silicon wafer used and the number of terminals of the IC package. In particular, the cost determined by the number of terminals of the IC package causes a stepwise cost difference, and In the case of using a plurality of slave stations, the apparatus cost is greatly affected.

For example, when the number of slave terminals in serial communication of a 4-bit configuration is calculated, power supply, ground, parallel input 4
Bits, parallel output 4 bits, input transfer data, output transfer data, transfer clock, and a minimum of 13 terminals are required. Further, based on the count value of the transfer clock timing counter means, a slave station signal processing timing in a series of serial communication is calculated, and slave station communication processing control means for executing serial communication signal processing is provided. In the case of the slave station configuration which realizes the above, three counters, that is, a counter reset, a count execution / interruption instruction signal, and a reset of the entire slave station circuit, are required as control of the counter means. Further, when a communication request signal for taking a bidirectional transmission form of serial communication, a feedback timing signal at a predetermined count value for detecting a communication error, and the like are added, 18 terminals are required. If 4 bits of the identifier code are required, the number of terminals increases to 22.

If the number of control terminals is deleted, the serial communication function will be reduced accordingly. If the number of control terminals is coded, the control signal of the counter means, which is the input control signal of the slave station, is reduced to three. One can be configured with two terminals (in this case, four status indications of counter reset, count execution, count interruption, and reset of the entire slave station circuit are required for code support), and two output control signals are configured with one terminal. ,
If you need a total of 16 terminals or 4 bits of identifier code,
It can be configured with a margin code value of zero with a total of 20 terminals and the minimum number of terminals.

However, the input selector circuit selects the specified parallel input information content according to the instruction signal transmitted from the master station to the parallel input circuit configuration of the slave station as described in the above-mentioned conventional example. By implementing the configuration of transmitting the signal to the input latch circuit, the number of control signals from the master station to the slave station increases, and the package constituting the gate array IC goes up by one step, resulting in a cost increase. Of course, if only one kind of parallel input information is used, there is a disadvantage that the function as a serial communication device is deteriorated.

In view of the above, it is an object of the present invention to select and hold either the first input information or the second input information in the input latch circuit means of the slave station. It is an object of the present invention to provide a serial communication system and a method in which an instruction can be performed without adding a new signal.

[0013]

In order to achieve the above object, according to the present invention, one master station and one or more slave stations are connected to a transmission line, and the master station and the slave stations are connected to each other. Along with transferring information in serial communication in synchronization with a transfer clock transmitted from the master station, information from a plurality of types of information predetermined in accordance with an instruction from the master station is selectively transmitted from the slave station. In the serial communication system for transmitting to the master station, a specific timing determined by a control signal transmitted from the master station to the slave station in relation to the transfer clock is associated with each of the plurality of types of information. A timing detecting means for detecting the specific timing based on the control signal; and, when the specific timing is detected, information of a type corresponding to the specific timing. Characterized in that comprises a transmission means for transmitting to.

According to a second aspect of the present invention, in the serial communication system according to the first aspect, the slave station has a counter for use in serial communication, and resets the counter at a first specific timing. A timing other than the reset timing is set as a second specific timing.

According to a third aspect of the present invention, in the serial communication system according to the second aspect, a control signal for resetting the counter is transmitted from the master station to the slave station.

According to a fourth aspect of the present invention, in the serial communication system according to the second aspect, the presence or absence of a state change of information transmitted between each of the first specific timing and / or the second specific timing is determined. The slave station has monitoring means for monitoring, and when the monitoring means detects that the information has changed, the slave station transmits a communication request signal to the master station.

According to a fifth aspect of the present invention, in the serial communication system according to the fourth aspect, the monitoring means has a latch circuit for latching information to be transmitted to the master station, and the information before latching is performed by the latch circuit. It is characterized in that the state change is detected by comparing the information with the latched information.

According to a sixth aspect of the present invention, in the serial communication system according to the fourth aspect, the master station determines whether or not a communication processing error has occurred on the slave station based on the timing of generation of the communication request signal received from the slave station. It is characterized by further comprising means for detecting.

According to a seventh aspect of the present invention, one master station and one or more slave stations are connected to a transmission line, and information between the master station and the slave stations is synchronized with a transfer clock transmitted from the master station. A serial communication method, and selectively transmits information among a plurality of types of information predetermined by an instruction from the master station from the slave station to the master station. A specific timing determined by a control signal transmitted from the master station to the slave station in association with each of the plurality of types of information,
The slave station detects the specific timing based on the control signal, and transmits the type of information corresponding to the specific timing to the master station when the specific timing is detected.

According to an eighth aspect of the present invention, in the serial communication method according to the seventh aspect, the slave station has a counter for use in serial communication, and resets the counter at a first specific timing. A timing other than the reset timing is set as a second specific timing.

According to a ninth aspect of the present invention, in the serial communication method according to the eighth aspect, a control signal for resetting the counter is transmitted from the master station to the slave station.

According to a tenth aspect of the present invention, in the serial communication method according to the eighth aspect, the presence or absence of a state change of information transmitted between each of the first specific timing and / or the second specific timing is determined. Monitoring by the slave station,
The slave station transmits a communication request signal to the master station when the monitoring detects that the information has changed.

According to an eleventh aspect of the present invention, in the serial communication method according to the tenth aspect, the slave station has a latch circuit for latching information to be transmitted to the master station, and the information before the information is latched by the latch circuit. And the information after the latch is detected to detect the presence of a state change.

According to a twelfth aspect of the present invention, in the serial communication method according to the tenth aspect, the master station determines whether or not a communication processing error has occurred on the slave station based on the generation timing of the communication request signal received from the slave station. It is characterized by detecting.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a specific circuit configuration of an input circuit of a slave station according to this embodiment. FIG. 2 shows a functional configuration of the input circuit of the slave station. FIG. 3 shows a system configuration of a serial communication device implementing the present embodiment.

1 and 2, reference numeral 1 denotes an input selector circuit, 2 denotes an input latch circuit, and 3 denotes a shift register (circuit) for executing serial information transfer. Reference numeral 4 denotes a twice-read latch circuit that holds the first data of the serial information read by the shift register circuit 3. When the result of the coincidence comparison between the second serial data read by the shift register circuit 3 and the first serial data held by the second read latch circuit 4 shows that the contents of the two data match,
The data held in the twice-read latch circuit 4 is output to the output latch circuit 5
And output as a parallel output. The circuit for comparing the first data and the second data is shown in FIG.
In FIG. 2, an exclusive OR circuit (hereinafter, referred to as an EXOR circuit) is used. However, in the block diagram of FIG. Absent. 6 is a counter circuit.
A decoding circuit 7 outputs a predetermined timing pulse from the count output of the counter circuit 6. The decoding circuit 7 outputs a timing return output (signal) for outputting a timing pulse at a predetermined timing which is returned to the main station.

In such a slave station configuration, the counter circuit 6 operates as transfer clock timing counter means controlled by a control signal issued from the master station, and the counter circuit 6 counts the transfer clock and outputs the control signal (transfer clock). Signal), it is controlled so as to execute or interrupt counting and to perform a count value clearing operation. The decode circuit 7 outputs a timing pulse for controlling the serial communication processing of the slave station from the count output of the counter circuit 6,
It operates as slave communication processing control that outputs a timing signal to each of the input selector circuit 1, the input latch circuit 2, the shift register circuit 3, the twice-read latch circuit 4, and the output latch circuit 5 at a preset timing. On the other hand, the decode circuit 7 also detects a decode value for outputting a specific timing to the master station, and also operates as a timing recognition output means for outputting a timing signal for each timing, and outputs a timing return output to return to the master station. Occur. Further, the input selector circuit 1 detects a communication request, that is, a change in the signal state of the parallel input information for each bit, and outputs a communication request when any one of the constituent bits changes. You.

In FIG. 3, reference numeral 10 denotes a main station,
1, 12, 13, 14, and 15 are each slave stations.

In this embodiment, for the sake of simplicity, the configuration of the slave station is shown as a 4-bit configuration.
It may be a bit and is not particularly limited.

With the above configuration, the slave stations 11 to 15 in FIG.
Reads the transfer data from the main station 10 in synchronization with the transfer clock and outputs it as a parallel output. The parallel input is loaded into the shift register circuit 3 before receiving the transfer data from the master station, and is sent to the master station 10 during the shift operation of receiving the transfer data from the master station 10. I have.

Next, the system features of the serial communication device according to the present embodiment will be briefly described with reference to FIG. In the figure, a timing return output (expressed as TIMING in the figure) and a communication request output (expressed as REQUEST in the figure) input to the master station 10 and issued from each slave station are shown.
Wired OR circuit 1 by transistor in each slave station
1A to 15A. Here, the wired OR configuration is a circuit that is turned on when at least one bit of a plurality of bit signals changes. Therefore, when one or more bits in the timing return output change, the
The MING input is turned on. Also, one of the communication request outputs
If more than one bit changes, the REQUEST of the main station 10
Input turns on. Thereby, regardless of the number of slave stations, the input signal to the master station 10 is constituted by one each. That is, the number of input terminals for the timing return output and the communication request output to the master station 10 can be set to 2 instead of the number of slave stations, and the number of CPU ports of the master station 10 can be saved. In addition,
In FIG. 3, the signal of the count state instruction control means for controlling the transfer clock timing counter means of the slave station is denoted by S in the figure.
& P and RESET.

In this wired OR in which all the timing return outputs from all the slave stations are detected by one signal source, if the output timing from each slave station is the same, if the system is operating normally, the wired OR is output at a predetermined timing.
The output turns on, and turns off except at the predetermined timing. However, when the phase of the count value of the counter circuit 6 of the slave station shifts due to noise or the like, the wired OR output is turned on at a timing that should be off. In other words, when the output of any one of the slave stations out of the timing of the timing return output from all the slave stations is shifted, the wired OR output is turned on at the shifted phase and is transmitted to the master station 10.
Therefore, the master station 10 checks that the wired OR outputs from all the slave stations are turned on at a predetermined timing, and checks that they are turned off at other timings.
It is possible to determine whether a phase shift has occurred in the output signal timing of the timing recognition output means of any of the slave stations, that is, whether or not a communication processing error has occurred. Therefore, the main station 10
Can detect and determine in real time whether or not the state of the parallel input terminals of all slave stations has changed.

Finally, the operation of this embodiment will be described with reference to FIGS. 1, 4, 5, and 6.

FIG. 1 is a circuit diagram showing an input circuit configuration of a slave station according to the present embodiment, and specifically shows a part of the block diagram shown in FIG. 2 in a circuit diagram. 1 and 2, an input selector circuit 1 is configured by an AND-OR circuit that outputs parallel input A and parallel input B information.
Input to the input latch circuit 2. Further, each information of the parallel input A and the parallel input B is set so that either one is selected by a communication reset signal from the master station input to the counter circuit 6.

In this circuit, for convenience, the parallel input A is selected during communication reset, and the parallel input B is selected otherwise. Further, the counter circuit 6 resets the count value (= 00H) at the leading edge of the ON of the communication reset signal from the main station. Further, the latch operation of the input latch circuit 2 and the count operation of the counter circuit 6 are configured to operate at the leading edge of the transfer clock.

On the other hand, the latch input and output of the input latch circuit 2 are input to an EXOR circuit in the input latch circuit 2 on a bit-by-bit basis, and are configured to compare whether the signal states match or not. Each output of the EXOR circuit is input to a multi-input NAND circuit and transmitted to the master station as a communication request signal. With this configuration, the communication request signal
It is turned on in real time when the state of the latch input and output of the input latch circuit 2 is different, that is, when a change occurs in the parallel input signal. After that, when the latch operation of the input latch circuit 2 is executed to execute the serial communication (the result is that the input is latched and output and the result is the same), the communication request signal is turned off and the state change is detected again. Will be.

Next, the shift register 3 is controlled by the decode circuit 7 to determine whether to shift serial data or load shift the output data from the input latch circuit 2.
The selector has an ND-OR circuit configuration. The shift operation is configured to operate at the trailing edge of the transfer clock, load shifts the output data from the input latch circuit 2 at a predetermined timing, and thereafter shifts the output data until the input of the transfer clock ends. Continue performing the action. Note that this shift operation is controlled by the master station, and outputs a communication reset to reset the count value of the counter circuit 6 to 00H.
After that, the number of transfer clocks corresponding to the number of transfer data bits is output and can be tracked.

Finally, the decoding circuit 7 outputs the timing for executing the communication processing control of the slave station based on the count value from the counter circuit 6. In the present embodiment, since it relates to the control of the parallel input information, the details of the count interruption control by the instruction signal for controlling the count operation are omitted. However, description of the instruction signal at the time of the control operation of the parallel input information will not be omitted. The decoding circuit 7
When the count value of the counter circuit 6 is 00H, it is decoded and synchronized with the transfer clock by an AND circuit.
The other is configured to output output data of the shift register 3 as a timing signal for instructing load shift.

Next, the parallel input information remote selection control means of the master station will be described with reference to the flowchart of FIG. The parallel input information remote selection control means is a CPU
Is realized by executing the processing program shown in the flowchart of FIG. In addition, the flowchart of FIG.
In the serial communication control, processing related to parallel input information remote selection control is shown, and other communication control processing is omitted in a subroutine expression of normal serial communication execution for ease of explanation.

In FIG. 4, when the communication operation starts, the communication reset signal is turned on in step 20 and the master station timing value for use in normal serial communication execution is cleared in step 21. Then, proceed to Step 22,
The instruction signal for controlling the counting operation of the counter circuit 6 of the slave station is turned off, and the counting operation is suspended. In step 23, similarly to step 21, the address pointer setting for use in loading and storing the transfer data is initialized by executing the normal serial communication, and the process proceeds to step 24. In step 24, the parallel input information to be returned is determined by the execution of the serial communication.

In the case of the parallel input B, step 25
To turn off the communication reset signal and proceed to step 26. On the other hand, in the case of the parallel input A, the process proceeds to step 26, where the transfer clock is turned on to start the communication operation. Then, the master station timing counter value is incremented in step 27, the transfer clock is turned off in step 28, and the output of one transfer clock is completed. In step 29, the communication reset signal is turned off. This corresponds to the case where the communication reset signal is not turned off in step 25. However, even if the communication reset signal is turned off in step 25, the turned off signal may be turned off again regardless of the turned off signal. This is merely for the convenience of the program processing. Finally, in step 30, the instruction signal for controlling the counting operation of the counter circuit 6 of the slave station is turned on, the interruption of the counting operation is released, and the counting execution state is indicated. Thereafter, the procedure proceeds to a subroutine of executing normal serial communication in step 31, and a series of subsequent serial communication controls are executed.

With the control configuration described above, the master station executes output control in which the phase relationship between the reset timing of the counter and the transfer clock timing is made different, thereby controlling selection of parallel input information in accordance with instructions from the master station. Because you can
It is not necessary to add a new control signal for selecting the parallel input information. Hereinafter, a specific operation will be described with reference to timing charts of FIGS. FIG. 5 is a timing chart when the parallel input A is selected, and FIG. 6 is a timing chart when the parallel input B is selected.

First, a case where the parallel input A is selected will be described with reference to FIG. When the communication reset is turned on, the parallel input A is selected for the input selector circuit 1, and
The count value of the counter circuit 6 is set to 00H. When the transfer clock is turned on while the instruction signal is off, the parallel input A is latched and held in the input latch circuit 2 at the leading edge of the transfer clock as shown in FIG. On the other hand, the count value of the counter circuit 6 is 0
It remains at 0H. Then, when the transfer clock is turned off, the parallel input A, which is the latch data of the input latch circuit 2, is shift-loaded into the shift register circuit 3 because of the trailing edge of the count value 00H. Then, when the communication reset is turned off and the instruction signal is turned on, the counter circuit 6 can execute the counting operation. The above is the operation when the parallel input A is selected, and thereafter, information exchange by serial transfer starts from the second transfer clock.

Subsequently, when the second clock of the transfer clock is turned on, the parallel input B is latched and held in the input latch circuit 2, but the parallel register A is already loaded in the shift register circuit 3, so the effect is not affected. Absent. On the other hand, the count value is
Since the count is increased to 01H and the second transfer clock is turned off, the shift register circuit 3 does not execute the load to execute the data shift operation. Therefore,
In the normal serial communication execution, the transfer data is output when the second transfer clock is turned on, and the return data is read after the second transfer clock is turned off, whereby the first data shift is completed. Thereafter, the same control is repeated up to a predetermined number of bits of the transfer data to be exchanged, and the process is repeatedly executed.

In FIG. 5, the control signal for interrupting the counting operation may be kept on from the time of communication reset, and is operated at the above timing for the convenience of the master station program.

Next, a case where the parallel input B is selected will be described with reference to FIG. When the communication reset is turned on, the parallel input A is selected for the input selector circuit 1, and the count value of the counter circuit 6 is set to 00H. here,
Unlike the control described above, the communication reset is canceled without turning on the transfer clock during the communication reset. After the release, the transfer clock is turned on while the instruction signal remains off, as in the previous control. As a result, since the parallel input B is selected for the input selector circuit 1 as shown in FIG. 6, the parallel latch B is latched and held in the input latch circuit 2 at the leading edge of the transfer clock. On the other hand, the count value of the counter circuit 6 is 00
H remains maintained. After that, when the transfer clock is turned off, the parallel input B, which is the latch data of the input latch circuit 2, is shifted into the shift register circuit 3 because the trailing edge of the count value is 00H.

Then, the communication reset is turned off.
In the case of the operation in the above, since the communication reset is once turned off, the turning off here is an operation for the convenience of the master station program and can be ignored in the control operation. When the instruction signal is turned on, the counter circuit 6 can execute the count operation. The above is the operation when the parallel input A is selected, and thereafter, information exchange by serial transfer is started from the second transfer clock as in the control with the parallel input A. Similarly, in normal serial communication execution, transfer data is output when the second transfer clock is turned on, and return data is read after the second transfer clock is turned off.

As described above, in the present embodiment, shift return is performed depending on whether the first transfer clock is turned on during communication reset or the first transfer clock is turned on after communication reset is released. The selection of the parallel input information is determined by the main station remote operation. Thus, there is no need to newly add a control signal for selecting the parallel input information.

(Second Embodiment) Next, a second embodiment will be described with reference to FIGS. 7, 8, 9, and 10. FIG.

The difference between the first embodiment and the second embodiment is that the content of the master station control signal to the counter circuit 6 is different. That is, in the second embodiment, there is no instruction signal for instructing the count interruption of the counter circuit 6 and the parallel input information remote control in a configuration in which the transfer clock input to the slave station is always counted up. This describes selection control means. Therefore, the same reference numerals in FIG. 7 denote the same parts as in the first embodiment, but the slave station configuration and the serial communication device are almost the same as those in the first embodiment in FIGS. .

FIG. 7 is a circuit diagram showing an input circuit configuration of a slave station in the second embodiment. In the figure, an input selector circuit 1 outputs information of a parallel input A and a parallel input B to A.
The input is input to the input latch circuit 2 for each bit received by the ND-OR circuit. The input selector circuit 1 is configured to select one of the parallel input A and the parallel input B based on a communication reset signal from the master station input to the counter circuit 6. In this circuit, for convenience, the parallel input A is selected during communication reset, and the parallel input B is otherwise selected.
Is configured to be selected. Also, the counter circuit 6
Resets the count value (= 00H) at the leading edge of the ON of the communication reset signal from the master station.

The latch of the input latch circuit 2 is configured to operate at the trailing edge of the transfer clock. The latch input and output of the input latch circuit 2 are input to the EXOR circuit bit by bit, and the signal state is matched. , The input latch circuit 2 is configured to compare non-coincidence. And this EXO
Each output of the R circuit is input to a multi-input NAND circuit and transmitted to the master station as a communication request signal. With this configuration, the communication request signal is turned on in real time when the state of the latch input and the output of the input latch circuit 2 are different, that is, when a change occurs in the parallel input signal. Thereafter, when the latch operation of the input latch circuit 2 is executed for executing the serial communication, the communication request signal is turned off and the state change is detected again.

Next, the shift register 3 controls whether the serial data or the output data from the input latch circuit 2 is load-shifted by the decode circuit 7.
The selector has an ND-OR circuit configuration. The shift operation is performed in the same manner as the count operation of the counter circuit 6.
Is configured to operate on the leading edge of the transfer clock,
The output data from the input latch circuit 2 is load-shifted at a predetermined timing, and thereafter, the execution of the shift operation is continued until the input of the transfer clock ends.

Note that this shift operation is controlled by the master station. After outputting a communication reset to set the count value of the counter circuit 6 to 00H, the shift clock number corresponding to the number of transfer data bits is output. That's the end. Finally, the decoding circuit 7 outputs the timing for executing the communication processing control of the slave station based on the count value from the counter circuit 6.

In the present embodiment, since it relates to the control of the parallel input information, only the control operation of the parallel input information will be described. When the count value of the counter circuit 6 is 00H, the decode circuit 7 synchronizes with the inverted signal of the transfer clock (for the trailing edge of the transfer clock) by the AND circuit. As the timing signal for holding, the other
Is output as a timing signal (corresponding to the leading edge of the transfer clock) for instructing a load shift.

Next, the processing contents of the parallel input information remote selection control means of the master station will be described with reference to the flowchart of FIG. The flowchart in FIG.
In the serial communication control, the content of the processing for the parallel input information remote selection control means is shown.
In order to facilitate the description, the description is usually omitted in a subroutine expression of serial communication execution.

In FIG. 8, when the communication operation is started, the communication reset signal is turned on in step 120, and the master station timing counter value used for normal serial communication execution is cleared in step 121. Then, the process proceeds to step 140 to turn on the transfer clock. In step 123,
As in step 121, the address pointer setting for use in loading and storing the transfer data is initialized by executing the normal serial communication, and the process proceeds to step 141. Step 1
At 41, the parallel input information to be returned is determined by executing this serial communication. In the case of the parallel input A, the transfer clock is turned off in step 142 and the process proceeds to step 143.

On the other hand, in the case of the parallel input B, step 143
To turn off the communication reset. Then, the master station timing counter value is incremented in step 27,
In step 128, the transfer clock is turned off, and the output of the first transfer clock is completed. The transfer clock off in step 128 corresponds to the case where the transfer clock is not turned off in step 142. However, even when the transfer clock is turned off in step 142, the turned off signal is turned off again. Regardless, it is merely for the convenience of program processing. Thereafter, the process proceeds to a subroutine of executing normal serial communication in step 131,
A series of subsequent serial communication controls are executed.

With the control configuration described above, the master station executes output control in which the phase relationship between the reset timing of the counter and the transfer clock timing is made different, thereby controlling the selection of parallel input information in accordance with an instruction from the master station. it can. Thus, there is no need to add a new control signal for selecting parallel input information. Hereinafter, a specific operation will be described with reference to timing charts of FIGS. FIG.
FIG. 10 is a timing chart when the parallel input A is selected, and FIG. 10 is a timing chart when the parallel input B is selected.

First, the case of selecting the parallel input A will be described with reference to FIG.

When the communication reset is turned on, the parallel input A is selected for the input selector circuit 1, and the count value of the counter circuit 6 is set to 00H. When the transfer clock is turned on, it is not determined by the shift register circuit 3 at the leading edge of the transfer clock as shown in FIG. 9 (UNKOW in FIG. 9).
The value (indicated by N) is shift loaded.

On the other hand, the count value of the counter circuit 6 remains at 00H because the communication is being reset. Thereafter, when the transfer clock is turned off, the parallel input A is latched and held in the input latch circuit 2 at the trailing edge of the transfer clock because the trailing edge of the count value is 00H. Next, when the communication reset is turned off, the counter circuit 6 can execute the count operation. The above is the operation when the parallel input A is selected, and thereafter, information exchange by serial transfer starts from the second transfer clock. However, at this stage, the parallel input A has not been shifted into the shift register circuit 3, so that the operation will be further described.

Subsequently, when the second clock of the transfer clock is turned on, the parallel input A latched and held in the input latch circuit 2 is shift-loaded into the shift register circuit 3. Further, the count value is counted up to 01H, and the latch operation to the input latch circuit 2 when the second transfer clock is turned off is eliminated. As described above, in the present embodiment, the shift load to the shift register circuit 3 is performed twice, but there is no problem because the second shift load data (parallel input A) is used for the subsequent shift operation.

Further, with respect to transmission and reception of transfer data at the main station, in the first embodiment, after setting transfer data, the second transfer clock is turned on (= leading edge),
Then, the return data is read and the second transfer clock is turned off (= trailing edge). However, in the second embodiment, the phase of the transfer clock is shifted by half as much as the shift operation is set to the trailing edge. It is. Therefore, when the second transfer clock is turned on (= leading edge), the transfer data is set, and after the second transfer clock is turned off (= tail edge), the return data may be read. Therefore, the transfer data may be executed by executing the normal serial communication as in the first embodiment.

Next, a case where the parallel input B is selected will be described with reference to FIG.

When the communication reset is turned on, the parallel input A is selected for the input selector circuit 1, and the count value of the counter circuit 6 is set to 00H. When the transfer clock is turned on, it is not determined by the shift register circuit 3 at the leading edge of the transfer clock as shown in FIG. 10 (UNKO in the figure).
The value (indicated by WN) is shift loaded.

On the other hand, the count value of the counter circuit 6 remains at 00H because the communication is being reset. Here, unlike the control in FIG. 9, the communication reset is turned off before the transfer clock is turned off. As a result, the input selector circuit 1 accesses the parallel input B, and the parallel latch B is latched and held in the input latch circuit 2 by the subsequent OFF operation of the transfer clock.

That is, as shown in FIG. 10, instead of turning on / off the first transfer clock during the communication reset, control is performed so that the communication reset is turned on / off during transmission of the first transfer clock. You do it. On the other hand, when the communication reset is turned off, the counter circuit 6 can execute the count operation. The above is the operation when the parallel input B is selected. Thereafter, information exchange by serial transfer is started from the second transfer clock.

However, at this stage, the parallel input B has not been shifted into the shift register circuit 3, so that the operation will be further described. Then, transfer clock 2
When the output is turned on, the parallel input B latched and held in the input latch circuit 2 is shift-loaded into the shift register circuit 3. Further, the count value is counted up to 01H, and the latch operation to the input latch circuit 2 when the second transfer clock is turned off is eliminated. The following is the same as FIG.

The above is the second embodiment. That is, the first transfer clock is turned on and off during the communication reset, or the first transfer clock is turned on during the communication reset. Depending on whether the transfer clock is turned off after canceling the communication reset, the selection of the parallel input information to be shifted back is determined by the remote operation of the master station. Therefore, it is not necessary to newly add a control signal for selecting the parallel input information.

(Third Embodiment) Finally, a third embodiment will be described.

In the third embodiment, the first and second
In the embodiment, the input latch processing error is detected in the selection processing of the parallel input information returned by the shift operation by the remote operation of the master station. This embodiment will be described based on the first embodiment.

The means for detecting an error in the input latch processing is provided in the master station, and utilizes a communication request signal transmitted in real time from the slave station. Normally, when this communication request signal is turned on, the main station, although not specifically shown,
Immediately execute the communication operation with the slave station. However, when the parallel input information remote selection control for outputting the communication reset and outputting the first transfer clock is being executed, the communication request signal is used as the judgment signal of the input latch processing error detecting means.

That is, in FIG. 5, the input latch circuit 2
The input signal at is represented by the input select in the figure,
The output signal from the input latch circuit 2 is represented by an input latch in the figure.
Matching and non-matching occur from the first transfer clock to the second transfer clock, and the second and subsequent transfer clocks are transmitted according to an algorithm called matching. By determining whether the order of the coincidence and the non-coincidence is correct, it is possible to detect the dense fog in the input latch process. On the other hand, in the case of FIG. 6, transmission is performed from the first transfer clock by an algorithm called coincidence. In other words, if the master station monitors the communication request signal up to the second transfer clock for executing the parallel input information remote selection control means and determines the order of coincidence and non-coincidence, it is easy to determine the input latch processing error. I understand.

As described above, the input latch processing error detection means can be realized by software processing, and does not have a dedicated circuit for error detection. It can be easily realized only by using the control processing.

As described above, in the above-described embodiment, the output timing of the transfer clock among the master station control signals output from the master station and controlling the transfer clock timing counter means for controlling the communication processing of the slave station is described. By controlling the phase relationship of the output timing of the communication reset for clearing the counter value, the selection of the parallel input information from the master station can be controlled. This has the effect of eliminating the need to add a control signal for selecting parallel input information. Therefore, even if a means for selecting parallel input information is added to the slave station in which the number of terminals of the gate array IC is clearly set, selection control can be performed indirectly without increasing the number of terminals of the IC in a stepwise manner. Cost increase can be suppressed.

Further, by using the conventional communication request signal and the parallel input information remote selection control means of the present invention, it is possible to easily determine an error in the selection control of the parallel input information by the master station. Accordingly, even if the parallel input information remote selection means is added, there is no need to newly create an error detection circuit in the selection-based configuration in the slave station configuration, which is advantageous in terms of cost.

[0079]

As described above, according to the first and seventh aspects of the present invention, a plurality of types of information can be selectively transferred at a specific timing using a conventional control signal. Thus, there is no need to newly provide a signal line for selecting the type of information or a dedicated signal.

According to the second, third, eighth, and ninth aspects of the present invention, transmission can be performed during a period in which no communication is performed by the conventional reset processing, so that a larger amount of information can be transmitted than before. Further, by giving a reset instruction on the master station side, the type of information to be transmitted on the master station side can be specified.

According to the fourth and tenth aspects of the present invention, when the state of information to be transmitted changes in the slave station and communication becomes impossible, a communication request can be generated and communication can be restarted.

According to the fifth and eleventh aspects of the present invention, since the same information to be transferred by different transfer clocks exists before and after the latch circuit, these two pieces of information are compared to be essentially the same. It can detect that the information to be changed has changed.

According to the sixth and twelfth aspects of the present invention, the communication request signal generated due to the information error on the slave station is different from the communication request signal generated in the normal state. An error on the slave station side can be detected from the timing.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an input circuit configuration of a slave station according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a slave station configuration according to the embodiment of the present invention.

FIG. 3 is a system block diagram of a serial communication device according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating an operation of a master station according to the first embodiment of the present invention.

FIG. 5 is a timing chart in a slave station circuit according to the first embodiment of the present invention.

FIG. 6 is a timing chart in a slave station circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing an input circuit configuration of a slave station according to a second embodiment of the present invention.

FIG. 8 is a flowchart illustrating an operation of a master station according to the second embodiment of the present invention.

FIG. 9 is a timing chart of a slave station circuit according to the second embodiment of the present invention.

FIG. 10 is a timing chart in a slave station circuit according to the second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input selector circuit 2 Input latch circuit 3 Shift register circuit 4 Double read latch circuit 5 Output latch circuit 6 Counter circuit 7 Decode (decoder) circuit 10 Master station 11, 12, 13, 14, 15 Slave station

Claims (12)

[Claims] 1. A master station and one or more slave stations are connected to a transmission line, and information is transferred between the master station and the slave stations by serial communication in synchronization with a transfer clock transmitted from the master station. And a serial communication system for selectively transmitting information among a plurality of types of predetermined information in accordance with an instruction from the master station to the master station from the slave station. A specific timing determined by a control signal transmitted from a station to the slave station and the plurality of types of information are associated with each other. The slave station detects timing of the specific timing based on the control signal. Transmitting means for transmitting, to the master station, information of a type corresponding to the specific timing when the timing is detected. M 2. The serial communication system according to claim 1, wherein the slave station has a counter for use in serial communication, and resets the counter at a first specific timing and a timing other than the reset timing. Is a second specific timing. 3. The serial communication system according to claim 2, wherein a control signal for resetting said counter is transmitted from said master station to said slave station. 4. The serial communication system according to claim 2, further comprising a monitoring unit that monitors whether there is a change in the state of information transmitted between each of the first specific timing and / or the second specific timing. The serial communication system according to claim 1, wherein the slave station has a slave station, and when the monitoring means detects a change in the state of the information, the slave station transmits a communication request signal to the master station. 5. The serial communication system according to claim 4, wherein said monitoring means has a latch circuit for latching information to be transmitted to said master station, and information before and after latching by said latch circuit. A serial communication system for detecting presence of a state change by comparing with information. 6. The serial communication system according to claim 4, wherein said master station further includes means for detecting whether or not a communication processing error has occurred on the slave station side based on the generation timing of a communication request signal received from said slave station. A serial communication system comprising: 7. A master station and one or more slave stations are connected to a transmission line, and information is transferred between the master station and the slave stations by serial communication in synchronization with a transfer clock transmitted from the master station. A serial communication method for selectively transmitting information among a plurality of types of information predetermined in accordance with an instruction from the master station from the slave station to the master station. A specific timing determined by a control signal transmitted from a station to the slave station and the plurality of types of information are associated with each other, and the slave station detects the specific timing based on the control signal, and the specific timing is detected. Transmitting a type of information corresponding to the specific timing to the master station. 8. The serial communication method according to claim 7, wherein the slave station has a counter for use in serial communication, and resets the counter at a timing other than the first specific timing and the reset timing. A second specific timing. 9. The serial communication method according to claim 8, wherein a control signal for resetting the counter is transmitted from the master station to the slave station. 10. The serial communication method according to claim 8, wherein the slave station monitors whether or not there is a change in the state of information transmitted between each of the first specific timing and / or the second specific timing. And a serial communication method, wherein, when the monitoring detects that the information has changed, the slave station transmits a communication request signal to the master station. 11. The serial communication method according to claim 10, wherein the slave station has a latch circuit for latching information to be transmitted to the master station, and information before and after latching by the latch circuit. A serial communication method characterized by detecting the presence of a state change by comparing 12. The serial communication method according to claim 10, wherein the master station detects whether or not a communication processing error has occurred on the slave station side based on the generation timing of a communication request signal received from the slave station. Serial communication method.