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JPH11297883A - Stackable semiconductor devices and these semiconductor device modules - Google Patents

Stackable semiconductor devices and these semiconductor device modules

Info

Publication number
JPH11297883A
JPH11297883A JP10101382A JP10138298A JPH11297883A JP H11297883 A JPH11297883 A JP H11297883A JP 10101382 A JP10101382 A JP 10101382A JP 10138298 A JP10138298 A JP 10138298A JP H11297883 A JPH11297883 A JP H11297883A
Authority
JP
Japan
Prior art keywords
insulating substrate
external terminals
semiconductor device
semiconductor
external terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10101382A
Other languages
Japanese (ja)
Other versions
JP3180758B2 (en
Inventor
Toshishige Yamamoto
利重 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Industries Ltd filed Critical Sumitomo Metal Industries Ltd
Priority to JP10138298A priority Critical patent/JP3180758B2/en
Publication of JPH11297883A publication Critical patent/JPH11297883A/en
Application granted granted Critical
Publication of JP3180758B2 publication Critical patent/JP3180758B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】 LLCCタイプのパッケージは、外部端子がパッ
ケージ周辺部に1列に形成されているために、外部端子
を増加できず、また必然的に第2絶縁基板を必要として
いた。外部端子数が増加でき、単一の絶縁基板から構成
できるようにする。 【解決手段】 中央に開口部を有する絶縁基板を用い、
その表面に複数の金属導体層は、それに接続された第1
外部端子と、この第1外部端子から前記絶縁基板を貫通
して裏面の第2外部端子に接続されている。各外部端子
は、格子状に配置されているから、同じピッチでも数を
増加でき、対向する各半導体装置を球状金属を介してそ
のような外部端子同士を接続すれば、十分な離間距離を
確保しながらモジュール化が可能となる。
(57) [Problem] To provide an LLCC type package, external terminals cannot be increased because external terminals are formed in a line in the periphery of the package, and a second insulating substrate is necessarily required. Was. The number of external terminals can be increased, and a single insulating substrate can be used. SOLUTION: An insulating substrate having an opening in the center is used,
A plurality of metal conductor layers on its surface have a first
An external terminal is connected to the second external terminal on the back surface through the insulating substrate from the first external terminal. Since the external terminals are arranged in a lattice pattern, the number can be increased even with the same pitch, and if the external terminals are connected to each other via a spherical metal, a sufficient separation distance is secured. Modularization becomes possible.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、積層可能な半導体
装置およびそれらを積層した半導体装置モジュールに関
し、より詳しくは、半導体素子を搭載した半導体装置を
複数重ね合わせたBGA(Ball Grid Array)タイプの積層構
造を備えた半導体装置モジュールに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stackable semiconductor device and a semiconductor device module in which the devices are stacked, and more particularly, to a BGA (Ball Grid Array) type in which a plurality of semiconductor devices on which semiconductor elements are mounted are stacked. The present invention relates to a semiconductor device module having a laminated structure.

【0002】[0002]

【従来の技術】半導体素子、特にDRAM等の半導体記憶装
置は、例えばCPU モジュール等に使用される場合に、1
つではなく、多数個使用されることが一般的である。こ
のとき、これらの半導体記憶装置を積層して実装するこ
とができれば、より高密度な実装基板を実現することが
できる。
2. Description of the Related Art A semiconductor device, particularly a semiconductor memory device such as a DRAM, is used for a CPU module or the like.
Instead of one, it is common to use many. At this time, if these semiconductor storage devices can be stacked and mounted, a higher-density mounting substrate can be realized.

【0003】一方、例えばDRAM等の半導体記憶装置で
は、例えば電源等に接続されて電力を供給する電極を半
導体素子の中央に配置する方が素子の性能が向上するこ
とが知られている。
On the other hand, in a semiconductor memory device such as a DRAM, for example, it is known that the performance of an element is improved when an electrode connected to a power supply or the like and supplying power is arranged at the center of the semiconductor element.

【0004】したがって、このような目的と要求によ
り、例えば特開平9−139441号公報に記載されている従
来より使用されている半導体装置のパッケージ40の構造
は、図4に示すように、底面を構成する第1絶縁基板41
とその表面の外周部に設けられた第2絶縁基板42とから
成り、第1絶縁基板41は底面が凹部を構成しており、そ
の中央には開口部Hが設けられている。かかるパッケー
ジ40では、開口部Hを中心に第1絶縁基板41の底面に半
導体素子46の表面側を接着することで、半導体素子46の
表面中央に設けられた電極 (図示せず) を開口部内に露
出させる。第1絶縁基板41の表面に形成された金属導体
層43と前記半導体素子46の電極とを銅線48で接続すると
ともに、金属導体層43をこのパッケージ40の端部まで引
き出し、側面を経由して第1絶縁基板41の底面およびこ
の第1絶縁基板上に形成された第2絶縁基板42の側面に
外部端子44、45をそれぞれ一体的に形成し、これらの外
部端子44、45を介してパッケージ40が順次積層できるよ
うにしている。これは、いわゆるLLCC(Leadless Chip C
arrier) タイプのパッケージである。
[0004] Therefore, due to such objects and demands, the structure of a conventionally used semiconductor device package 40 described in, for example, JP-A-9-139441 has a bottom surface as shown in FIG. First insulating substrate 41 to be constituted
And a second insulating substrate 42 provided on an outer peripheral portion of the surface thereof. The first insulating substrate 41 has a concave portion on the bottom surface, and an opening H is provided at the center thereof. In such a package 40, an electrode (not shown) provided at the center of the surface of the semiconductor element 46 is attached to the inside of the opening by bonding the front side of the semiconductor element 46 to the bottom surface of the first insulating substrate 41 around the opening H. Exposure to The metal conductor layer 43 formed on the surface of the first insulating substrate 41 and the electrode of the semiconductor element 46 are connected by a copper wire 48, and the metal conductor layer 43 is pulled out to the end of the package 40 and passed through the side surface. External terminals 44 and 45 are integrally formed on the bottom surface of the first insulating substrate 41 and the side surface of the second insulating substrate 42 formed on the first insulating substrate, respectively. The packages 40 can be sequentially stacked. This is the so-called LLCC (Leadless Chip C
arrier) type package.

【0005】図5には、金属導体層43を介して半導体素
子46からパッケージ側面の外部端子44、45までを電気的
に接続する導体の配置の拡大図を示す。図5に示すよう
に、半導体素子46の電極51は、銅線48により第1絶縁基
板41の上の金属導体層43に接続されている。第1絶縁基
板41の周辺部は第2絶縁基板42によって被覆されてお
り、上記金属導体層43もこの周辺部では第2絶縁基板42
によって被覆されている。このパッケージ40の側面の外
部端子44、45を形成する導体は、第2絶縁基板42の端部
を半円形に切り出して形成したその側面に形成されてい
る。
FIG. 5 is an enlarged view of an arrangement of conductors for electrically connecting the semiconductor element 46 to the external terminals 44 and 45 on the side surface of the package via the metal conductor layer 43. As shown in FIG. 5, the electrode 51 of the semiconductor element 46 is connected to the metal conductor layer 43 on the first insulating substrate 41 by a copper wire 48. The peripheral portion of the first insulating substrate 41 is covered with a second insulating substrate 42, and the metal conductor layer 43 is also covered by the second insulating substrate 42 in this peripheral portion.
Covered by The conductors forming the external terminals 44 and 45 on the side surface of the package 40 are formed on the side surface of the second insulating substrate 42 formed by cutting out the end of the second insulating substrate 42 into a semicircle.

【0006】[0006]

【発明が解決しようとする課題】図5からも分かるよう
に、従来の半導体装置にあっては、外部端子の数は、上
述の半円形の形成ピッチ以上に増やすことができない。
As can be seen from FIG. 5, in the conventional semiconductor device, the number of external terminals cannot be increased beyond the above-mentioned semicircular formation pitch.

【0007】また、図5の外観を見てわかるように、外
部端子44、45はパッケージ周辺に1列になって形成され
ている。また、このパッケージがLLCCタイプであるた
め、積層構造体とするには上下のパッケージの接続形態
がはんだ接続となる。はんだ接続の場合は、隣接する端
子同士が短絡するハンダブリッジという問題があり、や
はり、外部端子のピッチを狭くすることには一定の制限
があり、結局、外部端子の増大には限界がある。
As can be seen from the appearance of FIG. 5, the external terminals 44 and 45 are formed in a row around the package. Further, since this package is of LLCC type, the connection form of the upper and lower packages is a solder connection in order to form a laminated structure. In the case of the solder connection, there is a problem of a solder bridge in which adjacent terminals are short-circuited. Again, there is a certain limitation in narrowing the pitch of the external terminals, and there is a limit in increasing the number of external terminals.

【0008】一方で、ますます半導体素子は微細化が進
み、近年それに伴って必要な外部端子数が増大する傾向
にあり、LLCCタイプにおける上述の欠点は、致命的であ
る。さらに、従来のパッケージでは第2絶縁基板が必要
である。その理由は以下のようである。
On the other hand, semiconductor devices have been increasingly miniaturized and the number of necessary external terminals has tended to increase in recent years, and the above-mentioned disadvantages of the LLCC type are fatal. Furthermore, the conventional package requires a second insulating substrate. The reason is as follows.

【0009】すなわち、第1絶縁基板の表面には接続用
導体層および保護用封止樹脂が形成されており、この上
方にLLCCタイプのパッケージを直接、積層接続すること
はできない。そのため、その上に第2絶縁基板を形成
し、高さを稼ぐことにより、上下方向の実装を実現して
いる。また、LLCCという表面実装タイプのパッケージに
したために、本来は無用の第2絶縁基板を必要としてお
り、高価にならざるを得ない。さらに、第1絶縁基板を
凹部を有する形状に加工する理由も同様である。これも
製造コストを上昇させる原因である。
That is, a connecting conductor layer and a protective sealing resin are formed on the surface of the first insulating substrate, and an LLCC type package cannot be directly stacked and connected above the connecting conductor layer and the protective sealing resin. Therefore, the second insulating substrate is formed thereon and the height is increased, thereby realizing the mounting in the vertical direction. In addition, since the package is a surface mount type package called LLCC, an originally useless second insulating substrate is required, and it is inevitably expensive. Further, the reason for processing the first insulating substrate into a shape having a concave portion is also the same. This is also a factor that increases the manufacturing cost.

【0010】また、他方では、LLCCタイプのパッケージ
は凹凸部がなく、積み重ねるとすきまなく積層されるた
め、半導体素子から放出される熱が十分拡散できないと
いう問題も有していた。
[0010] On the other hand, since the LLCC type package has no irregularities and is stacked without gaps when stacked, there is also a problem that heat released from the semiconductor element cannot be sufficiently diffused.

【0011】このように、従来のLLCCタイプのパッケー
ジでは、パッケージの上下方向の導通をとるための導体
が側面を経由していること、そして、外部端子がパッケ
ージ周辺部に1列に形成されていることのために、近年
の外部端子増加要求に十分応えられないという問題があ
った。
As described above, in the conventional LLCC type package, the conductor for conducting the package in the vertical direction passes through the side surface, and the external terminals are formed in a line in the periphery of the package. Therefore, there has been a problem that the recent demand for increasing the number of external terminals cannot be sufficiently satisfied.

【0012】また、保護用封止樹脂等が第1絶縁基板の
表面よりも高くなるため、LLCCタイプのパッケージで
は、必然的に第2絶縁基板を必要とし、その結果、絶縁
基板の構造が複雑になり、高価になることも問題であっ
た。
Further, since the protective sealing resin and the like are higher than the surface of the first insulating substrate, the LLCC type package necessarily requires the second insulating substrate, and as a result, the structure of the insulating substrate is complicated. And it was also a problem that it became expensive.

【0013】本発明の目的は、外部端子数が多くなって
も、容易に積層することができ、高密度の実装基板を実
現でき、熱放出性の高い、かつ安価な半導体装置および
半導体装置モジュールを提供することである。
An object of the present invention is to provide a semiconductor device and a semiconductor device module which can be easily stacked even when the number of external terminals is large, realize a high-density mounting substrate, and have high heat emission and a low cost. It is to provide.

【0014】[0014]

【課題を解決するための手段】本発明者は、上記課題を
解決するために、半導体装置 (パッケージ) 自体の構造
を基本的に見直した。まず、半導体装置の側面に外部端
子を配置していることが、外部端子数増加の障害になっ
ていると考えた。側面に配置するということは、すなわ
ち、外部端子を、一次元的あるいは直線的に配置してい
るということである。外部端子を一次元的に配置し、外
部端子間のピッチを小さくするとそれだけハンダブリッ
ジの危険性も出てくる。そこで、外部端子を二次元的に
配置すればより多くの外部端子を配置でき、外部端子間
のピッチも余裕をもたせることができると考えた。
The present inventor basically reviewed the structure of the semiconductor device (package) itself in order to solve the above problems. First, it was considered that arranging external terminals on the side surface of the semiconductor device was an obstacle to increasing the number of external terminals. Arranging on the side surface means that the external terminals are arranged one-dimensionally or linearly. If the external terminals are arranged one-dimensionally and the pitch between the external terminals is reduced, the danger of a solder bridge also appears. Therefore, it has been considered that by arranging the external terminals two-dimensionally, more external terminals can be arranged, and the pitch between the external terminals can be given a margin.

【0015】次に、製造工程が複雑になり、コスト高に
つながる第1絶縁基板の凹部および第2絶縁基板をなく
すことを構造面から検討した。従来の半導体装置では完
全に凹凸のない形状をしていた。これは、保護用樹脂封
入と側面での接続の関係上、このような構造を取らざる
を得なかった。よって、半導体装置に凹凸があっても、
半導体装置同士が接続できるようにするにはどのように
したらよいか検討した。
Next, it was examined from a structural point of view to eliminate the concave portion of the first insulating substrate and the second insulating substrate, which would complicate the manufacturing process and increase the cost. The conventional semiconductor device has a completely uneven shape. For this reason, such a structure has to be adopted due to the relationship between the encapsulation of the protective resin and the connection at the side surface. Therefore, even if the semiconductor device has irregularities,
We examined how to connect semiconductor devices.

【0016】上記の考察から、半導体装置同士をハンダ
ボールで接続し、ハンダボールに高さを調整する役割を
もたせればよいと考えた。そこで、本発明は次の通りで
ある。
From the above consideration, it has been considered that the semiconductor devices should be connected to each other with solder balls, and the solder balls should have a role of adjusting the height. Then, the present invention is as follows.

【0017】(1) 表面に電極を有する半導体素子と、開
口部を有するとともに表面に第1外部端子、裏面に第2
外部端子を備えた絶縁基板とから構成され、前記半導体
素子は前記電極が前記開口部内に配置されるようにその
表面が前記絶縁基板の底面に接着されており、前記絶縁
基板は、表面に複数の金属導体層を備え、前記電極は前
記開口部を通る導線により該金属導体層に接続され、前
記金属導体層は前記第1外部端子に接続されるととも
に、該第1外部端子と前記第2外部端子は前記絶縁基板
を貫通する導体部を経由して接続されていることを特徴
とする半導体装置。
(1) A semiconductor device having an electrode on the front surface, a first external terminal on the front surface having an opening, and a second external terminal on the back surface.
An insulating substrate provided with external terminals, wherein the semiconductor element has a surface adhered to a bottom surface of the insulating substrate so that the electrode is disposed in the opening, and the insulating substrate has a plurality of insulating surfaces on the surface. Wherein the electrode is connected to the metal conductor layer by a conducting wire passing through the opening, the metal conductor layer is connected to the first external terminal, and the first external terminal and the second external terminal are connected to the first external terminal. The semiconductor device according to claim 1, wherein the external terminals are connected via a conductor portion penetrating the insulating substrate.

【0018】(2) 前記第1端子および第2端子が格子状
に配置されていることを特徴とする上記(1) 記載の半導
体装置。(3) 上記(1) または(2) 記載の複数の半導体装
置を積層し、対向する各半導体装置を球状金属を介して
前記外部端子同士を接続したことを特徴とする半導体装
置モジュール。
(2) The semiconductor device according to (1), wherein the first terminal and the second terminal are arranged in a lattice. (3) A semiconductor device module, wherein a plurality of the semiconductor devices according to the above (1) or (2) are stacked, and the external terminals are connected to each of the opposing semiconductor devices via a spherical metal.

【0019】このように、本発明によれば、パッケージ
上下面に形成された外部端子と金属導体層との接続を、
パッケージ側面を経由せずに、絶縁基板内部を貫通する
導体によって行うと共に、パッケージの上下面に形成さ
れた外部端子を格子状に配置することにより、端子ピッ
チを広げても端子数の増大に対応できるようにし、はん
だブリッジの危険性を低減できる。
As described above, according to the present invention, the connection between the external terminals formed on the upper and lower surfaces of the package and the metal conductor layer is established.
By using conductors that pass through the inside of the insulating substrate without passing through the package side surface, and by arranging external terminals formed on the top and bottom surfaces of the package in a grid pattern, it is possible to increase the number of terminals even if the terminal pitch is widened And the risk of solder bridges can be reduced.

【0020】また、格子状に配置された外部端子同士の
接続を、球状の金属を介して行うことで、上下のパッケ
ージの離間距離に余裕を持たせながら実現し、従来の第
2絶縁基板の必要性をなくし、安価なパッケージを実現
できる。
Further, the connection between the external terminals arranged in a lattice is made through a spherical metal, thereby realizing a sufficient space for the separation between the upper and lower packages. The necessity is eliminated and an inexpensive package can be realized.

【0021】さらに第1絶縁基板からも凹部を設ける必
要性を取り除き、一層安価なパッケージを実現できる。
加えて、このような半導体装置構造としたことで、半導
体素子から発生する熱放出の問題も解決できる。
Further, the necessity of providing a concave portion from the first insulating substrate is eliminated, and a more inexpensive package can be realized.
In addition, with such a semiconductor device structure, the problem of heat release generated from the semiconductor element can be solved.

【0022】[0022]

【発明の実施の形態】本発明による半導体装置では、半
導体素子を底面に接着する絶縁基板は、その中央に開口
部を有する。これは、素子特性向上のために、半導体素
子の電極を素子中央に形成することに対応したものであ
り、またその電極を露出させるためである。しかし、本
発明の場合、従来のように底面に半導体素子収容用の凹
部を設ける必要はない。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, an insulating substrate for bonding a semiconductor element to a bottom surface has an opening at the center. This corresponds to forming an electrode of a semiconductor element at the center of the element in order to improve element characteristics, and to expose the electrode. However, in the case of the present invention, it is not necessary to provide a recess for accommodating a semiconductor element on the bottom surface as in the related art.

【0023】絶縁基板の表面には、複数の金属導電層
(配線) が形成されており、その先端部と半導体素子の
電極とが導体によって接続される。通常はワイヤーボン
ドによって導線を使って接続される。
A plurality of metal conductive layers are provided on the surface of the insulating substrate.
(Wiring) is formed, and the tip of the wiring is connected to the electrode of the semiconductor element by a conductor. Usually, connection is made using a conductive wire by wire bonding.

【0024】また、金属導体層の個々の配線は、放射状
に広がり、絶縁基板の周縁部に配置された第1外部端子
の設置位置にまで延設される。本発明における外部端子
の配置については、格子状に配置することが好ましい。
ここで、格子状配置とは何列かにわたって存在する外部
端子を互い違いに配置することを意味する。例えば、外
部端子を図2に示すように2列に配置する場合、便宜
上、同一サイズの金属導体層および端子を用いるとする
と、ほぼ2倍の数の金属導体層および端子を設けること
ができる。このような外部端子は3列以上でも構わな
い。もちろん、外部端子数が少ない場合は、格子状にす
る必要はなく、1列であってもよい。
Further, the individual wirings of the metal conductor layer are spread radially and extend to a position where the first external terminal disposed on the periphery of the insulating substrate is provided. The arrangement of the external terminals in the present invention is preferably arranged in a lattice.
Here, the lattice arrangement means that the external terminals existing over several rows are alternately arranged. For example, when the external terminals are arranged in two rows as shown in FIG. 2, if metal conductor layers and terminals of the same size are used for convenience, the number of metal conductor layers and terminals can be almost doubled. Such external terminals may be provided in three or more rows. Of course, when the number of external terminals is small, it is not necessary to form a grid, and a single row may be used.

【0025】このように絶縁基板の表面に形成された第
1外部端子は、金属導電層に接続されると共に、絶縁基
板を貫通する導体によって、絶縁基板裏面に形成された
第2外部端子に接続される。
The first external terminal thus formed on the surface of the insulating substrate is connected to the metal conductive layer and connected to the second external terminal formed on the back surface of the insulating substrate by a conductor penetrating the insulating substrate. Is done.

【0026】絶縁基板を貫通する導体は、絶縁基板がセ
ラミックス基板の場合はビアホール、プラスチック基板
の場合はスルーホールであることが一般的である。この
ようにして、第1、第2外部端子の上下の導通を図る。
The conductor penetrating the insulating substrate is generally a via hole when the insulating substrate is a ceramic substrate, and a through hole when the insulating substrate is a plastic substrate. In this way, the first and second external terminals are electrically connected in the vertical direction.

【0027】絶縁基板の開口部はワイヤボンディング後
に樹脂等で保護する必要があり、ポッティング等により
樹脂封止する。このため、封止樹脂の高さは、絶縁基板
表面より高くなる。また、絶縁基板裏面も、半導体素子
が露出しており、樹脂等で封止する必要がある。従っ
て、裏面封止樹脂の高さも、絶縁基板裏面よりも低くな
る。
It is necessary to protect the opening of the insulating substrate with resin or the like after wire bonding, and the resin is sealed by potting or the like. For this reason, the height of the sealing resin is higher than the surface of the insulating substrate. Further, the semiconductor element is also exposed on the back surface of the insulating substrate, and needs to be sealed with a resin or the like. Therefore, the height of the back surface sealing resin is also lower than the back surface of the insulating substrate.

【0028】このため、本発明の半導体装置を積層構造
体とするには、ある程度高さを有する接続方法が必要と
なる。したがって、本発明では、球状の金属を介して接
続した、いわゆるBGA 構造を採用する。球状金属とし
て、高温ハンダボールやCuボール等が望ましい。外部端
子と球状金属は共晶ハンダや導電性樹脂によって接続さ
れる。これらの方法は実装温度が低く、球状金属を溶か
さず、高さが維持されるので好ましい。
Therefore, in order to make the semiconductor device of the present invention a laminated structure, a connection method having a certain height is required. Therefore, the present invention employs a so-called BGA structure connected through a spherical metal. As the spherical metal, a high-temperature solder ball, a Cu ball, or the like is desirable. The external terminal and the spherical metal are connected by eutectic solder or conductive resin. These methods are preferable because the mounting temperature is low, the spherical metal is not melted, and the height is maintained.

【0029】一方で、球状金属に共晶はんだを使用する
方法もある。この場合、はんだボールは溶けるが、上下
に形成された封止樹脂が接続高さを維持する働きをす
る。また、表面の露出した金属導体層および第1、第2
外部端子は外部との接続に必要な部分だけを残して、樹
脂等で保護することが望ましい。
On the other hand, there is a method of using eutectic solder for the spherical metal. In this case, the solder balls are melted, but the sealing resin formed above and below functions to maintain the connection height. In addition, the first and second metal conductor layers having exposed surfaces are provided.
It is desirable that the external terminals be protected with resin or the like, except for portions required for connection to the outside.

【0030】このような構造とすることで、安価で多端
子化に対応した積層構造体の半導体装置モジュールを提
供することができる。また、外部端子の配置を格子状と
することにより、その外部端子の配置密度は同一サイズ
の金属導体層および端子を用いた場合、単純にほぼ倍
に、あるいは金属導体層および端子のサイズを小さくす
れば、それ以上の外部端子を配置することができる。
With such a structure, it is possible to provide a semiconductor device module having a laminated structure that is inexpensive and can accommodate multiple terminals. In addition, by arranging the external terminals in a lattice shape, the arrangement density of the external terminals can be almost doubled or the size of the metal conductor layers and the terminals can be reduced simply when the metal conductor layers and the terminals of the same size are used. Then, more external terminals can be arranged.

【0031】[0031]

【実施例】本発明の実施形態について、図1を参照して
説明する。図1は、本発明にかかる半導体装置の断面図
である。まず、本発明の第1の実施形態として絶縁基板
1がプリント基板の場合について説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional view of a semiconductor device according to the present invention. First, a case where the insulating substrate 1 is a printed circuit board will be described as a first embodiment of the present invention.

【0032】図示のように、開口部を有する絶縁基板1
には、所望の金属導体層3、第1外部端子4、5、絶縁
基板1を貫通するスルーホール6、7、第2外部端子
8、9が形成されている。スルーホール6、7は穴側面
がCu等の金属で皮膜されるとともに導電性材料で穴埋め
されている。後で説明するように、金属ボールを実装を
するために、スルーホール6、7は上記のように導電性
材料で穴埋めされていることが望ましい。
As shown, an insulating substrate 1 having an opening
Are formed with desired metal conductor layers 3, first external terminals 4, 5, through holes 6, 7 penetrating the insulating substrate 1, and second external terminals 8, 9. The side surfaces of the through holes 6 and 7 are coated with a metal such as Cu and filled with a conductive material. As will be described later, it is preferable that the through holes 6 and 7 are filled with a conductive material as described above in order to mount a metal ball.

【0033】さらに、これらの金属パターン部のうち露
出させる必要がない部分は、樹脂部11、12、13、14、1
5、16で被覆して保護する。この状態で、LSI 素子であ
る半導体素子2を絶縁基板1の底面にこの素子の電極端
子 (図示せず) が開口部に露出するように接着剤 (図示
せず) で固着し、ワイヤ10で金属導体層3に接続する。
同時に、樹脂17a、17bにより、ワイヤ接続部および半
導体素子(LSI素子)2を封止し、保護する。
Further, the portions of these metal pattern portions which do not need to be exposed are the resin portions 11, 12, 13, 14, 1
Cover with 5, 16 to protect. In this state, the semiconductor element 2, which is an LSI element, is fixed to the bottom surface of the insulating substrate 1 with an adhesive (not shown) so that the electrode terminals (not shown) of the element are exposed in the openings, and the wires 10 are used. Connect to metal conductor layer 3.
At the same time, the resin 17a, 17b seals and protects the wire connection portion and the semiconductor element (LSI element) 2.

【0034】図示するように、第1および第2外部端子
は格子状に配置されているため、小型のパッケージであ
っても多数の外部端子を取り出すことができ、しかも端
子ピッチを広くできるために、信頼性も高い。
As shown in the figure, the first and second external terminals are arranged in a lattice, so that a large number of external terminals can be taken out even in a small package, and the terminal pitch can be widened. , High reliability.

【0035】次に、絶縁基板1がアルミナセラミック基
板の場合である本発明の第2の実施形態について、構造
が実質上同一であるため、同じく図1に基づいて、説明
する。ただし、上述のスルーホール6、7は本例ではビ
アホール6、7とする。
Next, a second embodiment of the present invention in which the insulating substrate 1 is an alumina ceramic substrate will be described with reference to FIG. 1 because the structure is substantially the same. However, the above-mentioned through holes 6 and 7 are the via holes 6 and 7 in this example.

【0036】まず、アルミナのグリーンシートに穴空け
加工を施し、ワイヤ接続のための開口部およびビアホー
ル6、7の穴部を形成する。次に、スクリーン印刷等の
方法により、高融点金属ペーストを用いて、金属導体層
3、第1外部端子4、5、ビアホール6、7の内部金属
層、第2外部端子8、9を形成する。さらに、これら金
属パターンを保護する目的で、アルミナペーストを印刷
する等の方法により、保護膜11、12、13、14、15、16を
形成し、その後、焼成する。さらに、露出した金属パタ
ーン部にNi/Auめっきを施す。半導体素子2を絶縁基板
1の底面に固着し、ワイヤ10を形成するとともに、封止
樹脂17a、17bを用いて、ワイヤ接続部および半導体素
子2 を保護する。
First, a hole is formed in a green sheet of alumina to form openings for wire connection and holes of via holes 6 and 7. Next, the metal conductor layer 3, the first external terminals 4 and 5, the internal metal layers of the via holes 6 and 7, and the second external terminals 8 and 9 are formed using a high-melting metal paste by a method such as screen printing. . Further, for the purpose of protecting these metal patterns, protective films 11, 12, 13, 14, 15, and 16 are formed by a method such as printing an alumina paste, and then firing. Further, Ni / Au plating is applied to the exposed metal pattern portion. The semiconductor element 2 is fixed to the bottom surface of the insulating substrate 1, the wires 10 are formed, and the wire connection portions and the semiconductor element 2 are protected by using the sealing resins 17a and 17b.

【0037】図示例では、金属パターンは絶縁基板1の
表裏面にしか形成されていないが、電気特性向上や多数
の配線を引き回すこと等を目的に、多層構造としても差
し支えない。
In the illustrated example, the metal pattern is formed only on the front and back surfaces of the insulating substrate 1. However, a multi-layer structure may be used for the purpose of improving electric characteristics and arranging a large number of wirings.

【0038】次に、本発明の半導体装置同士を積層する
ために用いる接続部材について図2を用いて説明する。
なお、本例では図2の半導体装置の構造それ自体は図1
のそれに同じである。
Next, a connecting member used for laminating the semiconductor devices of the present invention will be described with reference to FIG.
In this example, the structure itself of the semiconductor device of FIG.
Is the same as that of

【0039】図2の断面図より明らかなように、本発明
の半導体装置は絶縁基板1の表裏面にそれぞれ凸部を有
する。従って、これらを積層するためには、凸部の高さ
よりも高い接続部材を必要とする。本例ではそのような
凸部の高さよりも大きな直径を持った高温ハンダボール
18、19を接続部材として用いる。半導体装置は、そのよ
うな外部端子と共晶はんだ等の導電性接着剤により接続
される。従って、あらかじめ、外部端子表面に共晶はん
だ等の導電性接着剤を印刷等の方法により塗布しておく
ことが望ましい。
As is clear from the cross-sectional view of FIG. 2, the semiconductor device of the present invention has convex portions on the front and back surfaces of the insulating substrate 1, respectively. Therefore, in order to stack them, a connecting member that is higher than the height of the projection is required. In this example, a high-temperature solder ball having a diameter larger than the height of such projections
18 and 19 are used as connecting members. The semiconductor device is connected to such external terminals by a conductive adhesive such as eutectic solder. Therefore, it is desirable to apply a conductive adhesive such as eutectic solder to the surface of the external terminal in advance by printing or the like.

【0040】次に、本発明の半導体装置を用いたモジュ
ールについて、図3の略式断面図を用いて説明する。本
発明の半導体装置をマザー基板29に3層に積層した状態
の略式断面図を図3に示す。符号20、21、22は本発明の
半導体装置をその略式断面で示している。これらを高温
ハンダボール23〜28を介して接続することにより、図示
する積層構造体、つまり半導体装置モジュールを実現す
ることができる。各半導体装置と高温はんだボールは共
晶はんだ等により接続される。
Next, a module using the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG. FIG. 3 is a schematic cross-sectional view showing a state where the semiconductor device of the present invention is laminated on the mother substrate 29 in three layers. Reference numerals 20, 21, and 22 indicate the semiconductor device of the present invention in a schematic cross section. By connecting these via the high-temperature solder balls 23 to 28, the illustrated laminated structure, that is, the semiconductor device module can be realized. Each semiconductor device and the high-temperature solder ball are connected by eutectic solder or the like.

【0041】図示するようにパッケージ間の接続部材
を、高さのある球状金属とすることにより、前述の図4
に示すような従来例のように絶縁基板1に凹部を形成し
たり、絶縁基板2を形成したりする必要もなく、安価に
提供できる。
As shown in the figure, the connecting member between the packages is made of a spherical metal having a height, so that the above-mentioned FIG.
It is not necessary to form a concave portion in the insulating substrate 1 or to form the insulating substrate 2 as in the conventional example shown in FIG.

【0042】また、外部端子の配置を格子状とすること
により、その配置密度は同一条件であれば、単純に云え
ばほゞ倍にまで増加することができ、これによって各半
導体素子の集積度向上に対処できることになる。
In addition, by arranging the external terminals in a grid pattern, the arrangement density can be simply increased by a factor of approximately under the same conditions, thereby increasing the integration degree of each semiconductor element. You can cope with the improvement.

【0043】[0043]

【発明の効果】以上のように、本発明の半導体装置で
は、従来のように複雑な構造をした絶縁基板を使用する
ことなく、積層構造体を提供できるため、安価である。
また、外部端子を二次元的に配置するため、外部端子の
数を多くすることができ、特に、外部端子を格子状に配
置することにより多数の外部端子が必要な場合でも小型
のパッケージで適用可能である。さらに、積層化に当っ
ても半導体装置同士が十分な高さをもった球状金属で接
続されているので、積層構造も簡単で、しかも空間がで
き、熱放出性もよい。
As described above, according to the semiconductor device of the present invention, a laminated structure can be provided without using an insulating substrate having a complicated structure as in the prior art, so that it is inexpensive.
Also, since the external terminals are arranged two-dimensionally, the number of external terminals can be increased.Especially, by arranging the external terminals in a lattice shape, it can be applied to a small package even when many external terminals are required. It is possible. Further, even in the case of lamination, since the semiconductor devices are connected to each other by the spherical metal having a sufficient height, the lamination structure is simple, a space is formed, and the heat releasing property is good.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例に係る半導体装置の断面図であ
る。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

【図2】本発明の実施例に係る半導体装置の接続部材を
示した断面図である。
FIG. 2 is a cross-sectional view illustrating a connection member of the semiconductor device according to the embodiment of the present invention.

【図3】本発明の実施例に係る半導体装置を使用し、構
成された半導体装置モジュールを模式的に示す略式断面
図である。
FIG. 3 is a schematic cross-sectional view schematically showing a semiconductor device module configured using a semiconductor device according to an embodiment of the present invention.

【図4】従来の半導体装置の断面図である。FIG. 4 is a cross-sectional view of a conventional semiconductor device.

【図5】従来の半導体装置の側面を経由する外部端子の
拡大図である。
FIG. 5 is an enlarged view of an external terminal passing through a side surface of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1:絶縁基板 (プリント基板あるいはアルミナ等のセラ
ミック基板) 2:LSIの半導体素子 3:複数の金属導電層 4、5:第1外部端子 (絶縁基板表面) 6、7:絶縁基板を貫通する導体 (スルーホールあるい
はビアホール) 8、9:第2外部端子 (絶縁基板裏面) 10:接続部材 (ワイヤ) 11〜16:保護部材 (樹脂あるいはアルミナ) 17a, 17b:封止樹脂 18、19:接続用球状金属 (高温はんだボール等) 20〜22:本発明の半導体装置 23〜28:接続用球状金属 (高温ハンダボール等) 29:マーザ基板( プリント基板)
1: Insulating substrate (printed substrate or ceramic substrate such as alumina) 2: Semiconductor element of LSI 3: Plural metal conductive layers 4, 5: First external terminal (surface of insulating substrate) 6, 7: Conductor penetrating insulating substrate (Through hole or via hole) 8, 9: Second external terminal (backside of insulating substrate) 10: Connection member (wire) 11-16: Protective member (resin or alumina) 17a, 17b: Sealing resin 18, 19: For connection Spherical metal (high-temperature solder ball, etc.) 20-22: Semiconductor device of the present invention 23-28: Spherical metal for connection (high-temperature solder ball, etc.) 29: Marza board (printed board)

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 表面に電極を有する半導体素子と、開口
部を有するとともに表面に第1外部端子、裏面に第2外
部端子を備えた絶縁基板とから構成され、前記半導体素
子は前記電極が前記開口部内に配置されるようにその表
面が前記絶縁基板の底面に接着されており、前記絶縁基
板は、表面に複数の金属導体層を備え、前記電極は前記
開口部を通る導線により該金属導体層に接続され、前記
金属導体層は前記第1外部端子に接続されるとともに、
該第1外部端子と前記第2外部端子は前記絶縁基板を貫
通する導体部を経由して接続されていることを特徴とす
る半導体装置。
1. A semiconductor device having an electrode on a front surface, and an insulating substrate having an opening, a first external terminal on a front surface, and a second external terminal on a back surface, wherein the semiconductor element has the electrode. The surface is adhered to the bottom surface of the insulating substrate so as to be disposed in the opening, and the insulating substrate includes a plurality of metal conductor layers on the surface, and the electrode is formed by a conductive wire passing through the opening. And the metal conductor layer is connected to the first external terminal,
The semiconductor device according to claim 1, wherein the first external terminal and the second external terminal are connected via a conductor penetrating the insulating substrate.
【請求項2】 前記第1端子および第2端子が格子状に
配置されていることを特徴とする請求項1記載の半導体
装置。
2. The semiconductor device according to claim 1, wherein said first terminal and said second terminal are arranged in a lattice.
【請求項3】 請求項1または2記載の複数の半導体装
置を積層し、対向する各半導体装置を球状金属を介して
前記外部端子同士を接続したことを特徴とする半導体装
置モジュール。
3. A semiconductor device module comprising: a plurality of the semiconductor devices according to claim 1 or 2 stacked; and the external terminals connected to each of the opposing semiconductor devices via a spherical metal.
JP10138298A 1998-04-13 1998-04-13 Stackable semiconductor devices and their semiconductor device modules Expired - Fee Related JP3180758B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10138298A JP3180758B2 (en) 1998-04-13 1998-04-13 Stackable semiconductor devices and their semiconductor device modules

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10138298A JP3180758B2 (en) 1998-04-13 1998-04-13 Stackable semiconductor devices and their semiconductor device modules

Publications (2)

Publication Number Publication Date
JPH11297883A true JPH11297883A (en) 1999-10-29
JP3180758B2 JP3180758B2 (en) 2001-06-25

Family

ID=14299231

Family Applications (1)

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Country Status (1)

Country Link
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005150748A (en) * 2003-11-18 2005-06-09 Samsung Electronics Co Ltd Semiconductor chip package having decoupling capacitor and manufacturing method thereof
JP2005150719A (en) * 2003-11-13 2005-06-09 Samsung Electronics Co Ltd Double stacked BGA package and multiple stacked BGA package
JP2006032379A (en) * 2004-07-12 2006-02-02 Akita Denshi Systems:Kk Laminate semiconductor device and its manufacturing method
JP2006080521A (en) * 2004-09-10 2006-03-23 Samsung Electronics Co Ltd Stack board on chip package having mirror structure and double-sided mounting memory module having the same mounted thereon
JP2007103681A (en) * 2005-10-05 2007-04-19 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2009054741A (en) * 2007-08-27 2009-03-12 Powertech Technology Inc Semiconductor package
JP2009054684A (en) * 2007-08-24 2009-03-12 Powertech Technology Inc Semiconductor pop device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005150719A (en) * 2003-11-13 2005-06-09 Samsung Electronics Co Ltd Double stacked BGA package and multiple stacked BGA package
JP2005150748A (en) * 2003-11-18 2005-06-09 Samsung Electronics Co Ltd Semiconductor chip package having decoupling capacitor and manufacturing method thereof
JP2006032379A (en) * 2004-07-12 2006-02-02 Akita Denshi Systems:Kk Laminate semiconductor device and its manufacturing method
JP2006080521A (en) * 2004-09-10 2006-03-23 Samsung Electronics Co Ltd Stack board on chip package having mirror structure and double-sided mounting memory module having the same mounted thereon
JP2007103681A (en) * 2005-10-05 2007-04-19 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2009054684A (en) * 2007-08-24 2009-03-12 Powertech Technology Inc Semiconductor pop device
JP2009054741A (en) * 2007-08-27 2009-03-12 Powertech Technology Inc Semiconductor package

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