JPH11288839A - Laminated chip type electronic component and manufacture thereof - Google Patents
Laminated chip type electronic component and manufacture thereofInfo
- Publication number
- JPH11288839A JPH11288839A JP10104075A JP10407598A JPH11288839A JP H11288839 A JPH11288839 A JP H11288839A JP 10104075 A JP10104075 A JP 10104075A JP 10407598 A JP10407598 A JP 10407598A JP H11288839 A JPH11288839 A JP H11288839A
- Authority
- JP
- Japan
- Prior art keywords
- component
- component body
- external connection
- electrodes
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000010030 laminating Methods 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 abstract description 19
- 239000010410 layer Substances 0.000 description 11
- 238000005520 cutting process Methods 0.000 description 9
- 238000005476 soldering Methods 0.000 description 8
- 238000010304 firing Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 239000006071 cream Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000004931 aggregating effect Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002003 electrode paste Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、内部電極と誘電体
層とから交互に積層形成された部品本体を有し、その内
部電極と電気的に接続された外部接続電極を導電パター
ンのランド部と半田付け固定することにより回路基板の
板面上に搭載される積層チップ型の電子部品及びその製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a component body which is formed by alternately laminating internal electrodes and dielectric layers, and externally connecting electrodes which are electrically connected to the internal electrodes. The present invention relates to a multilayer chip type electronic component mounted on a board surface of a circuit board by soldering and fixing, and a method of manufacturing the same.
【0002】[0002]
【従来の技術】一般に、積層チップコンデンサを例示す
ると、内部電極と誘電体層とを上下交互に積層させて直
方体形状の部品本体を形成し、この部品本体の両端部に
露出する内部電極の端部と電気的に接続させて外部電極
が部品本体の両端部に設けられている。その外部電極は
内部電極の端部と電気的に接続される端面部分と、この
端面部分から部品本体の端部縁近く面内に回る周面部分
とから部品本体の両端部を覆うよう形成されている。2. Description of the Related Art In general, when a multilayer chip capacitor is exemplified, an internal electrode and a dielectric layer are alternately stacked up and down to form a rectangular parallelepiped component body, and ends of the internal electrode exposed at both ends of the component body. External electrodes are provided at both ends of the component body so as to be electrically connected to the component. The external electrode is formed so as to cover both ends of the component body from an end surface portion electrically connected to the end portion of the internal electrode and a peripheral surface portion turning from the end surface portion to a surface near an end edge of the component body. ing.
【0003】その積層チップコンデンサの搭載用とし、
主に、外部電極の端面部分と半田付け固定することか
ら、回路基板の板面には搭載される部品本体の両端縁よ
り側方に広げて導電パターンのランド部を設けることが
行われている。この回路基板においては、積層チップコ
ンデンサを板面に半田付けすると、導電パターンのラン
ド部に印刷された半田ペーストが外部電極の端面部分に
沿って表面張力で盛り上がり凝集し、半田フィレットが
部品本体の両端部より張り出すよう形成される。[0003] For mounting the multilayer chip capacitor,
Mainly, since it is fixed by soldering to the end face portion of the external electrode, a land portion of the conductive pattern is provided on the board surface of the circuit board so as to extend laterally from both end edges of the mounted component body. . In this circuit board, when the multilayer chip capacitor is soldered to the board surface, the solder paste printed on the lands of the conductive pattern swells and aggregates due to surface tension along the end surfaces of the external electrodes, and the solder fillet is formed on the component body. It is formed to protrude from both ends.
【0004】これでは部品本体より側方に広がり位置す
る導電パターンのランド部と共に、相隣接する他の電子
部品を回路基板の板面上で半田フィレットからも離して
搭載しなければならないため、電子部品を回路基板の限
られた板面の面積内に複数搭載する高密度実装の妨げと
なる。In this case, adjacent electronic components must be mounted on the board surface of the circuit board, apart from the solder fillet, together with the land portions of the conductive pattern that extend to the side of the component body. This hinders high-density mounting of a plurality of components within a limited area of the board surface of the circuit board.
【0005】上述した部品本体の両端部を覆うのに代え
て、外部電極を回路基板の板面と相対する部品本体の面
内に設ける表面実装型の電子部品が提案されている(特
開平2−156514号)。A surface-mount type electronic component has been proposed in which external electrodes are provided on the surface of the component main body opposite to the board surface of the circuit board, instead of covering both ends of the component main body described above (Japanese Patent Laid-Open No. Hei 2 (1994)). -156514).
【0006】その電子部品では、外部電極を部品本体の
一面に設けるのみであるから、装着向きが一方向に限ら
れてしまう。このため、その電子部品を回路基板の板面
上に実装しようとすると、外部電極が形成されている面
を基板側に合わせる工程が必要となり、また、一般に用
いられている電子部品の表面実装装置を使用できない場
合も生ずる。In this electronic component, since the external electrodes are only provided on one surface of the component body, the mounting direction is limited to one direction. Therefore, in order to mount the electronic component on the board surface of the circuit board, a process of aligning the surface on which the external electrodes are formed with the board side is required, and a commonly used electronic component surface mounting apparatus is used. May not be used.
【0007】それに加えて、上述した電子部品では外部
電極が回路基板の板面と相対する部品本体の面内でも、
縁回りを部品本体の外郭縁に合わせて端部寄りに設けら
れている。また、半田ペーストが外部電極の端面回りに
凝集することを考慮し、導電パターンのランド部が部品
本体より側方に広げて回路基板の板面上に形成されてい
る。このため、依然として部品本体の側方にはみ出す半
田フィレットが生ずるのを避けられない。In addition, in the above-described electronic component, the external electrodes are disposed on the surface of the component body facing the plate surface of the circuit board.
The periphery is provided near the end so as to match the outer edge of the component body. Also, in consideration of the solder paste aggregating around the end surface of the external electrode, the land portion of the conductive pattern is formed on the board surface of the circuit board so as to extend laterally from the component body. For this reason, it is inevitable that a solder fillet still protrudes to the side of the component body.
【0008】その電子部品を製造するのに、内部電極と
誘電体グリーンシートとを交互に複数積層させて多数個
取り用の誘電材ブロックを得、この誘電材ブロックを複
数個一列に多数列並ぶ単位毎に切断して内部電極の端部
が素体面の少なくとも一面に露出する素体を得、外部電
極形成用の導電性ペーストを内部電極の多数列並ぶ端部
の各列毎に塗布してから素体を部品素体単位に個々に切
断し、その後に導電性ペーストと共に部品素体を焼成処
理することが提案されている(特開平9ー260187
号)。In order to manufacture the electronic component, a plurality of dielectric blocks are obtained by alternately laminating a plurality of internal electrodes and dielectric green sheets, and a plurality of dielectric blocks are obtained. Obtain an element body in which the ends of the internal electrodes are exposed on at least one surface of the element body surface by cutting for each unit, and apply a conductive paste for forming external electrodes to each row of end rows of the internal electrodes in many rows. It has been proposed that the element body be cut into individual component element units, and then the component element be fired together with a conductive paste (Japanese Patent Laid-Open No. 9-260187).
issue).
【0009】然し、その電子部品の製造方法では素体を
切断するのに伴って生ずる切断屑が予め塗布された導電
性ペーストに付着し残るため、外部電極を精度よく形成
するのが困難であり、焼成における誘電体層と外部電極
の焼成縮率の違いにより、内部電極との電気的な接続性
が悪くなって電気的特性に影響を与える。また、部品素
体と同時に、外部電極も部品素体の焼成に要する100
0℃以上の高温で加熱処理されることになるから、通常
用いられるガラスフリット入りの導電性ペーストや銀電
極ペーストを用いることができない。[0009] However, in the method of manufacturing an electronic component, since cutting chips generated as a result of cutting the element body adhere to and remain on the previously applied conductive paste, it is difficult to accurately form the external electrodes. In addition, the difference in firing shrinkage between the dielectric layer and the external electrode during firing deteriorates the electrical connectivity with the internal electrode and affects the electrical characteristics. Also, at the same time as the component element body, the external electrodes are also required for firing the component element body.
Since the heat treatment is performed at a high temperature of 0 ° C. or more, a conductive paste containing a glass frit and a silver electrode paste that are generally used cannot be used.
【0010】[0010]
【発明が解決しようとする課題】本発明は、通常の装着
方向性を有し、また、部品本体の側方にはみ出す半田フ
ィレットをなくすことにより相隣接する電子部品との搭
載間隔を狭く設定でき、回路基板の限られた板面の面積
内をより有効活用可能な高密度実装に適した積層チップ
型の電子部品を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has a normal mounting direction and eliminates the solder fillet protruding to the side of the component body, thereby making it possible to narrow the mounting interval between adjacent electronic components. It is another object of the present invention to provide a multilayer chip-type electronic component suitable for high-density mounting that can more effectively utilize the limited area of the circuit board.
【0011】本発明は電気的特性を損なうことなく、通
常用いられる導電性ペーストから外部接続電極を精度よ
く形成可能な積層チップ型電子部品の製造方法を提供す
ることを目的とする。An object of the present invention is to provide a method of manufacturing a laminated chip electronic component capable of accurately forming external connection electrodes from a commonly used conductive paste without impairing electrical characteristics.
【0012】また、本発明は内部電極の端部と外部接続
電極とを電気的に確実に接続させて電気的特性の良好な
ものに形成可能な積層チップ型電子部品の製造方法を提
供することを目的とする。Further, the present invention provides a method of manufacturing a laminated chip type electronic component capable of forming an electrical component having good electrical characteristics by securely connecting the end of an internal electrode and an external connection electrode. With the goal.
【0013】更に、本発明は外部接続電極を能率よく容
易に形成可能な積層チップ型電子部品の製造方法を提供
することを目的とする。It is a further object of the present invention to provide a method for manufacturing a laminated chip type electronic component capable of forming external connection electrodes efficiently and easily.
【0014】[0014]
【課題を解決するための手段】本発明の請求項1に係る
積層チップ型電子部品においては、内部電極と誘電体層
とを交互に複数積層させて部品本体を形成すると共に、
互いに電気的に接続されない内部電極の端面の一部を、
その端面と平行する部品本体の両端部寄りに、各面内で
隔離して露出し、且つ、部品本体の外周縁より各面内に
距離を保って内部電極の各端部と電気的に接続する外部
接続電極を部品本体の上下各面で夫々同形態に設けるこ
とにより構成されている。According to a first aspect of the present invention, there is provided a multilayer chip type electronic component in which a plurality of internal electrodes and dielectric layers are alternately laminated to form a component body.
Part of the end faces of the internal electrodes that are not electrically connected to each other,
Near each end of the component body parallel to its end face, it is separated and exposed in each plane, and is electrically connected to each end of the internal electrode at a distance within each plane from the outer peripheral edge of the component body. The external connection electrodes are formed in the same form on the upper and lower surfaces of the component body.
【0015】本発明の請求項2に係る積層チップ型電子
部品の製造方法においては、内部電極と誘電体グリーン
シートとを交互に複数積層させて多数個取り用の積層体
を得て、その積層体を部品素体単位に個々に切断してか
ら焼成処理し、互いに電気的に接続されない内部電極の
端面の一部を、その端面と平行する部品本体の両端部寄
りに、各面内で隔離して露出する部品本体を得た後、部
品本体の外周縁より各面内に距離を保って内部電極の各
端部と電気的に接続する外部接続電極を部品本体の上下
各面で夫々同形態に形成するようにされている。According to a second aspect of the present invention, there is provided a method of manufacturing a multilayer chip type electronic component, wherein a plurality of internal electrodes and dielectric green sheets are alternately laminated to obtain a multi-cavity laminate. The body is individually cut into component body units and then fired, and a part of the end faces of the internal electrodes that are not electrically connected to each other are separated in each plane near both ends of the component body parallel to the end faces. After obtaining the exposed component body, the external connection electrodes that are electrically connected to each end of the internal electrode while maintaining a distance within each plane from the outer peripheral edge of the component body are the same on each of the upper and lower surfaces of the component body. It is adapted to be formed into a form.
【0016】本発明の請求項3に係る積層チップ型電子
部品の製造方法においては、内部電極の各端部が露出す
る部品素体の各面を研削処理した後に焼成処理し、外部
接続電極を該研削された部品本体の各面に形成するよう
にされている。In the method of manufacturing a multilayer chip electronic component according to a third aspect of the present invention, each surface of the component body in which each end of the internal electrode is exposed is ground and then fired to form the external connection electrode. It is formed on each surface of the ground component body.
【0017】本発明の請求項4に係る積層チップ型電子
部品の製造方法においては、焼成処理した部品本体を治
具で複数個整列保持すると共に、導電性ペーストを部品
本体の上下各面に塗布し、その導電性ペーストを焼付け
処理して外部接続電極を形成するようにされている。In the method of manufacturing a multilayer chip electronic component according to a fourth aspect of the present invention, a plurality of fired component bodies are aligned and held by a jig, and a conductive paste is applied to upper and lower surfaces of the component body. Then, the conductive paste is baked to form external connection electrodes.
【0018】[0018]
【発明の実施の形態】以下、添付図面を参照して説明す
ると、図示実施の形態は積層チップコンデンサ,チップ
抵抗,チップインダクタ,チップフィルタ等の積層チッ
プ型電子部品のうちで、この代表例として積層チップコ
ンデンサ(以下、単に「チップ部品」という。)を示
す。そのチップ部品は、図1,図2で示すように部品本
体1が複数枚の誘電体層(符号なし、以下、同じ)と内
部電極2,2’…とを交互に積層させて燒結することに
より直方体形状を呈するよう形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the accompanying drawings, the illustrated embodiment is a typical example of a multilayer chip electronic component such as a multilayer chip capacitor, a chip resistor, a chip inductor, and a chip filter. 1 shows a multilayer chip capacitor (hereinafter simply referred to as “chip component”). As shown in FIGS. 1 and 2, the component body 1 is formed by alternately laminating a plurality of dielectric layers (not numbered, the same applies hereinafter) and the internal electrodes 2, 2 '. Are formed so as to have a rectangular parallelepiped shape.
【0019】その部品本体1は、誘電体層と内部電極
2,2’…とを交互に積層し、互いに電気的に接続され
ない内部電極2,2’…の端面の一部2a,2b、2
a’,2b’を、その端面と平行する部品本体1の両端
部寄りに、各面内で隔離して露出することにより形成さ
れている。この内部電極2,2’…は、後で詳述する如
く各端部2a,2b、2a’,2b’が部品本体1の上
下各面側に引き出されるT字状等の電極パターンで誘電
体層となる誘電体グリーンシートに印刷し、その電極パ
ターンを逆向きに印刷した誘電体グリーンシートを複数
積層することから形成できる。The component body 1 is formed by alternately laminating dielectric layers and internal electrodes 2, 2 '..., And a part 2a, 2b, 2 of the end face of the internal electrodes 2, 2'.
The components a 'and 2b' are formed by exposing the components a in a plane near both ends parallel to the end faces thereof. The internal electrodes 2, 2 '... Are formed by a T-shaped electrode pattern in which each end 2a, 2b, 2a', 2b 'is drawn out to the upper and lower surfaces of the component body 1 as described in detail later. It can be formed by printing on a dielectric green sheet to be a layer, and laminating a plurality of dielectric green sheets each having an electrode pattern printed in the opposite direction.
【0020】その部品本体1においては、図3で示すよ
うに左右対の外部接続電極3a,3b、4a,4bが部
品本体1の上下各面に設けられている。この対の外部接
続電極3a,3b、4a,4bは上述した互いに電気的
に接続されない内部電極2,2’…の端面の一部2a,
2b、2a’,2b’と夫々個別に電気的に接続するも
ので、部品本体1の外周縁より各面内に距離L1 ,L2
を保って部品本体1の上下各面で夫々同形態を呈するよ
うに設けられている。In the component body 1, a pair of left and right external connection electrodes 3a, 3b, 4a, 4b are provided on the upper and lower surfaces of the component body 1 as shown in FIG. The pair of external connection electrodes 3a, 3b, 4a, 4b are part of the end surfaces 2a, 2a,
2b, 2a ', 2b' and each intended individually electrically connected, the distance to each plane of the outer periphery of the component body 1 L 1, L 2
While maintaining the same shape on the upper and lower surfaces of the component body 1.
【0021】そのチップ部品の搭載用とし、回路基板P
の板面には図1で示す如く各対の外部接続電極3a,3
b、4a,4bが渡るよう位置合わせて導電パターンの
ランド部R1 ,R2 が印刷形成されている。このランド
部R1 ,R2 は半田ペーストが外部接続電極3a,3
b、4a,4bの厚み面回りに凝集することを考慮し、
外部接続電極3a,3b、4a,4bが部品本体1の外
郭辺より内側に隔てる距離L1 ,L2 の範囲内において
外部接続電極3a,3b、4a,4bよりも広面積に広
げて形成することができる。なお、この回路基板Pは導
電パターンのランド部R1 ,R2 を除き、板面がソルダ
ーレジスト膜(図示せず)で被覆されている。For mounting the chip component, the circuit board P
As shown in FIG. 1, each pair of external connection electrodes 3a, 3
The land portions R 1 , R 2 of the conductive pattern are printed and formed so as to be positioned so as to cross over the lines b, 4a, 4b. The land portions R 1 and R 2 are made of solder paste on the external connection electrodes 3 a and 3.
In consideration of aggregation around the thickness plane of b, 4a, 4b,
External connection electrodes 3a, 3b, 4a, 4b to form spread in a wider area than the external connection electrodes 3a, 3b, 4a, 4b within the range of the distance L 1, L 2 that separates from the outer sides of the component body 1 inside be able to. The board surface of the circuit board P is covered with a solder resist film (not shown) except for the land portions R 1 and R 2 of the conductive pattern.
【0022】上述したチップ部品は、リフローソルダリ
ングで回路基板Pの板面に半田付け固定することができ
る。このリフローソルダリングでは、まず、クリーム半
田を導電パターンのランド部R1 ,R2 に印刷する。次
に、チップ部品を回路基板Pの板面に載置するが、その
チップ部品は外部接続電極3a,3b、4a,4bが部
品本体1の上下各面で同形態に設けられているため、部
品本体1の上下各面のいずれかからでも回路基板Pの板
面に向けて載置することにより、外部接続電極3a,3
bまたは4a,4bをクリーム半田に接触させて仮止め
することができる。それと同様に、他の電子部品も回路
基板Pの板面上に載置したならば、赤外線の照射炉に送
り込んでクリーム半田を溶融することにより半田付け処
理すればよい。The above-mentioned chip component can be fixed by soldering to the plate surface of the circuit board P by reflow soldering. In this reflow soldering, first, cream solder is printed on the lands R 1 and R 2 of the conductive pattern. Next, the chip component is placed on the plate surface of the circuit board P. Since the external connection electrodes 3a, 3b, 4a, and 4b are provided on the upper and lower surfaces of the component body 1 in the same form, the chip component is mounted. The external connection electrodes 3a, 3 can be placed on the circuit board P from any one of the upper and lower surfaces of the component body 1.
b or 4a, 4b can be temporarily fixed by contacting with cream solder. Similarly, if other electronic components are also mounted on the board surface of the circuit board P, the soldering process may be performed by sending the electronic components to an infrared irradiation furnace and melting the cream solder.
【0023】この半田付け処理に伴ってはクリーム半田
が溶融固化することにより半田フィレットS1 ,S2 が
形成されるが、その半田フィレットS1 ,S2 は部品本
体1の外郭辺より内側に離隔位置する外部接続電極3
a,3bまたは4a,4bとの間に形成されるため、少
なくとも部品本体1より側方にはみ出さない。また、こ
の半田フィレットS1 ,S2 が外部接続電極3a,3b
または4a,4bの厚み面回りに凝集しても、ランド部
R1 ,R2 の面積を越えないから部品本体1より側方に
はみ出ない。During this soldering process, the solder fillets S 1 and S 2 are formed by melting and solidifying the cream solder. The solder fillets S 1 and S 2 are located inside the outer side of the component body 1. External connection electrode 3 located at a distance
a, 3b or 4a, 4b, it does not protrude at least laterally from the component body 1. The solder fillets S 1 and S 2 are connected to the external connection electrodes 3a and 3b.
Alternatively, even if the agglomerates around the thickness planes of 4a and 4b, they do not exceed the area of the lands R 1 and R 2 and do not protrude from the component body 1 to the side.
【0024】従って、上述した構成のチップ部品による
と、導電パターンのランド部R1 ,R2 として回路基板
Pの板面上で部品本体1より側方に広げるよう形成しな
いでよいばかりでなく、半田フィレットS1 ,S2 も部
品本体1より側方にはみ出さないから、相隣接する電子
部品の搭載位置乃至は導電パターンのランド部は部品本
体1より卑近の狭間位置に設定することができる。これ
により、回路基板の限られた板面の面積内を有効活用で
きて高密度実装可能な積層チップ型電子部品として構成
できる。Therefore, according to the chip component having the above-described configuration, not only the land portions R 1 and R 2 of the conductive pattern need not be formed so as to extend laterally than the component body 1 on the board surface of the circuit board P, but also. Since the solder fillets S 1 and S 2 do not protrude to the side from the component body 1, the mounting positions of the adjacent electronic components or the lands of the conductive patterns can be set at narrower positions closer to the component body 1. . This makes it possible to effectively utilize the limited area of the board surface of the circuit board and configure a multilayer chip electronic component that can be mounted at high density.
【0025】このチップ部品を製造するには、まず、誘
電材ペーストからグリーンシートを得た後に、内部電極
をCu,Ag,Pd,Ni等の導電性ペーストを誘電体
グリーンシートのシート面にスクリーン印刷することに
より内部電極を形成する。その内部電極は、T字状を呈
する電極パターンのものではT字の頭部辺で横方向に連
続させて複数個分を一列に並べることにより複数列を共
通パターンで誘電体グリーンシートのシート面に形成す
ることができる。To manufacture this chip component, first, a green sheet is obtained from a dielectric material paste, and then an internal electrode is screened with a conductive paste such as Cu, Ag, Pd, or Ni on the sheet surface of the dielectric green sheet. An internal electrode is formed by printing. In the case of an electrode pattern having a T-shape, the internal electrodes are laterally continuous at the head side of the T-shape, and a plurality of the inner electrodes are arranged in a single row. Can be formed.
【0026】その内部電極の形成後に、誘電体グリーン
シートは図4で示すように複数層1a,1b…を内部電
極2,2’…と交互になるよう上下に積層する。この積
層にあたっては、内部電極2,2’が上下の相対する誘
電体グリーンシート1a,1b…の間で逆向きの電極パ
ターンとなるよう位置し、所定枚複数層を順次に重ね合
わせてプレス成形することにより多数個取り用の積層体
1’として形成する。なお、特に図示しないが、積層体
1’の最外層には誘電体の保護層が積層されている。After the formation of the internal electrodes, the dielectric green sheet is formed by laminating a plurality of layers 1a, 1b... Alternately with the internal electrodes 2, 2 '... As shown in FIG. In this lamination, the internal electrodes 2, 2 'are positioned so as to form an electrode pattern in the opposite direction between the upper and lower dielectric green sheets 1a, 1b,... By doing so, it is formed as a multilayer body 1 'for multi-cavity production. Although not particularly shown, a dielectric protective layer is laminated on the outermost layer of the laminate 1 '.
【0027】その積層体1’は、図5で示すように部品
素体単位に個々に切断する。この切断は、上述したT字
の頭部辺で横方向に連続させたものでは各T字の頭部辺
毎に切断する方向C1 と、複数列形成したT字毎に切断
する方向C2 とに沿って夫々行うことにより、互いに電
気的に接続されない内部電極2,2’…の端面の一部2
a,2b、2a’,2b’が上下二面の各面内で両端部
寄りに露出する部品素体を得ることができる。また、そ
の切断は積層体1’が未焼成の生の状態で行うため、通
常の直線刃状のスライサーを用いて容易に行うことがで
きる。The laminate 1 'is cut into individual parts as shown in FIG. This cutting is performed in the direction in which the head side of the T-shape is continuous in the lateral direction, and the cutting direction C 1 for each T-head side and the cutting direction C 2 for each T-shape formed in a plurality of rows. , The inner electrodes 2, 2 ′ that are not electrically connected to each other
It is possible to obtain a component body in which a, 2b, 2a ', and 2b' are exposed near both ends in each of the upper and lower surfaces. Further, since the cutting is performed in a green state in which the laminate 1 ′ is not fired, it can be easily performed using a normal straight-blade-shaped slicer.
【0028】その部品素体単位に切断後、内部電極の端
面の一部が露出するように研削仕上する。この後に、各
部品素体は焼成炉に送り込むことにより焼成処理を施
す。その焼成処理は1000〜1400℃程度の温度で
行い、誘電体層を一体に焼結する。これにより、図2で
示すような内部電極2,2’の互いに電気的に接続され
ない端面の一部2a,2b、2a’,2b’が上下二面
の各面内で両端部寄りに露出する部品本体1を得ること
ができる。After cutting into component parts, grinding is performed so that part of the end face of the internal electrode is exposed. Thereafter, each component body is subjected to a firing process by being sent to a firing furnace. The firing process is performed at a temperature of about 1000 to 1400 ° C., and the dielectric layers are integrally sintered. Thereby, parts 2a, 2b, 2a ', 2b' of the end faces of the internal electrodes 2, 2 'which are not electrically connected to each other as shown in FIG. 2 are exposed near both ends in each of the upper and lower surfaces. The component body 1 can be obtained.
【0029】その焼成処理後の部品本体1,1…に対
し、Ag,Cu等の導電性ペーストを塗布することによ
り外部接続電極を形成する。この電極形成は、図6で示
すように部品本体1,1…を凹部10a,10b…に収
容させて複数整列保持するパレット状の治具10と、部
品本体1,1…の研削面に露出する内部電極の各端部と
対応する開孔部11a,11b…を有するメタルマスク
11と、導電性ペーストGを移動するスキージ12とを
用い、部品本体1,1…を治具10で反転させることに
より部品本体1,1…の両面に印刷処理することができ
る。その印刷処理によると、複数個の部品本体を治具1
0で整列保持することにより一括処理できるばかりでな
く、導電性ペーストGを部品本体1,1…の研削面に高
精度に塗布することができる。An external connection electrode is formed by applying a conductive paste such as Ag, Cu or the like to the component bodies 1, 1... As shown in FIG. 6, the electrodes are formed by pallet-shaped jigs 10 for accommodating a plurality of component bodies 1, 1,... In recesses 10a, 10b. Are turned over by a jig 10 using a metal mask 11 having openings 11a, 11b... Corresponding to the respective ends of the internal electrodes to be formed, and a squeegee 12 for moving the conductive paste G. .. Can be printed on both sides of the component bodies 1, 1,. According to the printing process, the plurality of component bodies are
By keeping the alignment at 0, not only batch processing can be performed, but also the conductive paste G can be applied to the ground surfaces of the component bodies 1, 1,... With high accuracy.
【0030】その印刷された導電性ペーストGには50
0〜900℃程度の温度で焼付け処理を施し、Ni,S
n,半田等でメッキ処理することにより外部接続電極3
a,3b、4a,4bとして設けることができる。この
外部接続電極3a,3b、4a,4bは導電性ペースト
Gの焼付けに必要な温度で加熱するのみであるから、電
気的特性の劣化は勿論、内部電極との導電不良を生ずる
ことがなく、上述したように部品本体1,1…の外周縁
より各面内に距離を保って内部電極の端面の一部と電気
的に接続する外部接続電極を部品本体の上下各面で夫々
同形態に形成できる。The printed conductive paste G has 50
Baking treatment at a temperature of about 0 to 900 ° C.
n, external connection electrodes 3 by plating with solder or the like.
a, 3b, 4a, and 4b. Since the external connection electrodes 3a, 3b, 4a, and 4b are only heated at the temperature required for baking the conductive paste G, the electrical characteristics are not deteriorated, and the conduction with the internal electrodes is not caused. As described above, the external connection electrodes electrically connected to a part of the end surface of the internal electrode while maintaining a distance in each plane from the outer peripheral edge of the component main bodies 1, 1. Can be formed.
【0031】なお、上述したチップ部品の構造並びに製
造方法を適用すると、図7で示すような部品本体の高さ
Hとのバランスで幅Wの狭いチップ部品を構成すること
ができる。このチップ部品は部品の小型化,低背化を図
れるため、高密度実装により好適である。When the above-described structure and manufacturing method of a chip component are applied, a chip component having a narrow width W can be formed in balance with the height H of the component body as shown in FIG. This chip component is suitable for high-density mounting because the component can be reduced in size and height.
【0032】[0032]
【発明の効果】以上の如く、本発明の請求項1に係る積
層チップ型電子部品に依れば、内部電極と誘電体層とを
交互に複数積層させて部品本体を形成すると共に、互い
に電気的に接続されない内部電極の端面の一部を、その
端面と平行する部品本体の両端部寄りに各面内で隔離し
て露出し、この内部電極の端面の一部と電気的に接続す
る外部接続電極を部品本体の上下各面に同形態に設ける
ため、表面実装時の装着向きが限定されない。また、外
部接続電極は部品本体の外周縁より各面内に距離を保っ
て設けることから、半田付けに要する導電パターンのラ
ンド部として回路基板の板面上で部品本体より側方に広
げないでよく、半田フィレットも部品本体より側方には
み出さないため、回路基板の限られた板面の面積内を有
効活用できて高密度実装を図れる。As described above, according to the multilayer chip type electronic component of the first aspect of the present invention, the component main body is formed by alternately laminating a plurality of internal electrodes and dielectric layers, and the electrical components are electrically connected to each other. A part of the end face of the internal electrode which is not electrically connected is exposed in the respective planes near both ends of the component body which is parallel to the end face, and is externally connected to a part of the end face of the internal electrode. Since the connection electrodes are provided on the upper and lower surfaces of the component body in the same form, the mounting direction at the time of surface mounting is not limited. In addition, since the external connection electrodes are provided at a distance within each plane from the outer peripheral edge of the component body, do not spread laterally from the component body on the board surface of the circuit board as land portions of conductive patterns required for soldering. Often, the solder fillet does not protrude from the side of the component body, so that the limited area of the board surface of the circuit board can be effectively utilized and high-density mounting can be achieved.
【0033】本発明の請求項2に係る積層チップ型電子
部品の製造方法に依れば、内部電極と誘電体グリーンシ
ートとを交互に複数積層させて多数個取り用の積層体を
得、その積層体を部品素体単位に個々に切断して焼成処
理した後、外部接続電極を内部電極の端面の一部が露出
する部品面に設けることにより、外部接続電極を形成す
る導電性ペーストを焼付けに必要な温度で熱処理できる
から、電気的特性の劣化は勿論、内部電極との導電不良
を生ずることがなく、外部接続電極を良好なものに形成
することができる。According to the method for manufacturing a multilayer chip electronic component according to the second aspect of the present invention, a plurality of internal electrodes and dielectric green sheets are alternately laminated to obtain a multi-cavity laminate. After the laminate is individually cut into component element units and fired, the external connection electrodes are provided on the component surface where a part of the end face of the internal electrode is exposed, so that the conductive paste forming the external connection electrodes is baked. Since the heat treatment can be performed at a temperature required for the semiconductor device, it is possible to form a good external connection electrode without deteriorating the electrical characteristics as well as causing poor conductivity with the internal electrode.
【0034】本発明の請求項3に係る積層チップ型電子
部品の製造方法に依れば、内部電極の各端部が露出する
素体面を研削処理した後に焼成処理し、外部接続電極を
研削された部品本体の本体面に形成するため、外部接続
電極を形成する導電性ペーストを高精度に印刷形成する
ことができる。According to the method of manufacturing a multilayer chip electronic component according to a third aspect of the present invention, the element body surface on which each end of the internal electrode is exposed is ground and then fired to grind the external connection electrode. Since the conductive paste for forming the external connection electrode is formed on the main body surface of the component main body, the conductive paste for forming the external connection electrode can be printed and formed with high precision.
【0035】本発明の請求項4に係る積層チップ型電子
部品の製造方法に依れば、焼成処理した部品本体を治具
で複数個整列保持することにより導電性ペーストを能率
よく部品本体の上下各面に塗布できて外部接続電極を容
易に形成することができる。According to the method of manufacturing a multilayer chip electronic component according to the fourth aspect of the present invention, the conductive paste is efficiently placed on the upper and lower sides of the component main body by aligning and holding a plurality of fired component main bodies with a jig. An external connection electrode can be easily formed by coating on each surface.
【図1】本発明の一実施の形態に係る積層チップ型電子
部品を基板実装状態で示す説明図である。FIG. 1 is an explanatory view showing a laminated chip type electronic component according to an embodiment of the present invention in a board mounted state.
【図2】同積層チップ型電子部品における内部電極の積
層構造を示す部品本体の斜視図である。FIG. 2 is a perspective view of a component body showing a laminated structure of internal electrodes in the multilayer chip electronic component.
【図3】同積層チップ型電子部品における外部接続電極
の形態を示す部品本体の斜視図である。FIG. 3 is a perspective view of a component main body showing a form of an external connection electrode in the multilayer chip electronic component.
【図4】同積層チップ型電子部品を製造する積層体の積
層方法を示す説明図である。FIG. 4 is an explanatory view showing a method of laminating a laminate for producing the laminated chip electronic component.
【図5】同積層チップ型電子部品を製造する積層体の切
断方法を示す説明図である。FIG. 5 is an explanatory view showing a method of cutting a laminate for producing the laminated chip electronic component.
【図6】同積層チップ型電子部品の外部接続電極を形成
する導電性ペーストの塗布方法を示す説明図である。FIG. 6 is an explanatory view showing a method of applying a conductive paste for forming external connection electrodes of the multilayer chip electronic component.
【図7】本発明の別の形態に係る積層チップ型電子部品
における内部電極の積層構造を示す部品本体の斜視図で
ある。FIG. 7 is a perspective view of a component body showing a laminated structure of internal electrodes in a laminated chip electronic component according to another embodiment of the present invention.
1 部品本体 1a,1b… 誘電体グリーンシ
ート 1’ 積層体 2,2’… 内部電極 2a,2b、2a’,2b’ 内部電極の端面の
一部 3a,3b、4a,4b 外部接続電極 P 回路基板 L1 ,L2 外部接続電極の距
離 10 治具DESCRIPTION OF SYMBOLS 1 Component main body 1a, 1b ... Dielectric green sheet 1 'Laminated body 2, 2' ... Internal electrode 2a, 2b, 2a ', 2b' Part of the end surface of internal electrode 3a, 3b, 4a, 4b External connection electrode P circuit Board L 1 , L 2 Distance between external connection electrodes 10 Jig
Claims (4)
させて部品本体を形成すると共に、互いに電気的に接続
されない内部電極の端面の一部を、その端面と平行する
部品本体の両端部寄りに、各面内で隔離して露出し、且
つ、部品本体の外周縁より各面内に距離を保って該内部
電極の端面の一部と電気的に接続する外部接続電極を部
品本体の上下各面で夫々同形態に設けたことを特徴とす
る積層チップ型電子部品。1. A component body is formed by alternately laminating a plurality of internal electrodes and dielectric layers, and a part of an end face of an internal electrode that is not electrically connected to each other is partially connected to both ends of the component body parallel to the end face. An external connection electrode that is separated and exposed in each plane near the part and that is electrically connected to a part of the end surface of the internal electrode while maintaining a distance in each plane from the outer peripheral edge of the component body. Characterized in that the upper and lower surfaces are provided in the same form, respectively.
互に複数積層させて多数個取り用の積層体を得、その積
層体を部品単位に個々に切断してから焼成処理し、互い
に電気的に接続されない内部電極の端面の一部を、その
端面と平行する部品本体の両端部寄りに、各面内で隔離
して露出する部品本体を得た後、部品本体の外周縁より
各面内に距離を保って該内部電極の端面の一部と電気的
に接続する外部接続電極を部品本体の上下各面で夫々同
形態に形成するようにしたことを特徴とする積層チップ
型電子部品の製造方法。2. An internal electrode and a plurality of dielectric green sheets are alternately laminated to obtain a multi-cavity laminated body, and the laminated body is cut into individual parts and then fired to be electrically connected to each other. A part of the end face of the internal electrode that is not connected to both ends of the component body parallel to the end face is obtained near the both ends of the component body, and the exposed component body is separated and exposed in each plane. An external connection electrode electrically connected to a part of an end face of the internal electrode while keeping a distance between the upper and lower surfaces of the component body. Production method.
体の各面を研削処理した後に焼成処理し、外部接続電極
を該研削された部品本体の各面に形成するようにしたこ
とを特徴とする請求項2に記載の積層チップ型電子部品
の製造方法。3. A grinding process for each surface of the component body where each end of the internal electrode is exposed, followed by a baking process to form an external connection electrode on each surface of the ground component body. The method for manufacturing a multilayer chip electronic component according to claim 2, wherein:
個整列保持すると共に、導電性ペーストを部品本体の上
下各面に塗布し、その導電性ペーストを焼付け処理して
外部接続電極を形成するようにしたことを特徴とする請
求項2または3に記載の積層チップ型電子部品の製造方
法。4. A plurality of the baked component bodies are aligned and held by a jig, a conductive paste is applied to upper and lower surfaces of the component body, and the conductive paste is baked to form external connection electrodes. The method for manufacturing a multilayer chip electronic component according to claim 2, wherein the method is performed.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10104075A JPH11288839A (en) | 1998-03-31 | 1998-03-31 | Laminated chip type electronic component and manufacture thereof |
US09/282,415 US6380619B2 (en) | 1998-03-31 | 1999-03-31 | Chip-type electronic component having external electrodes that are spaced at predetermined distances from side surfaces of a ceramic substrate |
EP99302518A EP0949642B1 (en) | 1998-03-31 | 1999-03-31 | Chip-type electronic component and method for producing the same |
DE69942902T DE69942902D1 (en) | 1998-03-31 | 1999-03-31 | Electronic chip-type device and method for its production |
US10/014,856 US6576497B2 (en) | 1998-03-31 | 2001-12-14 | Chip-type electronic component |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10104075A JPH11288839A (en) | 1998-03-31 | 1998-03-31 | Laminated chip type electronic component and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11288839A true JPH11288839A (en) | 1999-10-19 |
Family
ID=14371042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10104075A Pending JPH11288839A (en) | 1998-03-31 | 1998-03-31 | Laminated chip type electronic component and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11288839A (en) |
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US6967827B2 (en) | 2003-11-14 | 2005-11-22 | Murata Manufacturing Co., Ltd. | Laminated capacitor |
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US20140268488A1 (en) * | 2013-03-15 | 2014-09-18 | Murata Manufacturing Co., Ltd. | Monolithic capacitor |
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