JPH11288374A - Simulator for digital computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily analyze simulation results by giving no instructions following an instruction that stops the execution of simulation to a pipeline when execution of simulation is stopped and accordingly eliminating influences of subsequent instructions when execution of simulation is stopped by a specific instruction. SOLUTION: It's decided whether the instruction of a stage A, i.e., the first one of pipeline processing stages satisfies the execution termination condition (instruction 1). If the instruction does not satisfy the instruction 1, execution of simulation is carried on as it is. If the instruction satisfies the instruction 1, a flag, i.e., a NOPFLG 21 is set to make the next instruction wait for the stage A. Then the subsequent instructions are stopped until the instruction 1 finishes the final stage D or the steps are carried on with insertion of the substitute NOP steps. Then the NOPFLG 21 is reset and program execution is stopped. Thus, it's possible to stop the steps in a state where the subsequent instructions are not processed at a STOP time point.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital computer simulator used for developing software for operating a digital computer having a pipeline structure.

[0002]

2. Description of the Related Art In developing software for digital computers such as microcomputers and microprocessors, a software simulator that faithfully reproduces the operation of the software is essential. At this time, in order to improve the efficiency of software development, a function of stopping execution by an arbitrary instruction and outputting the resulting internal state is indispensable.

In recent years, in a digital computer, in order to speed up the operation, a method of processing an instruction in a pipeline structure internally has been generally used.
Therefore, it is impossible for a simulator (instruction execution type simulator) that executes instructions independently one by one in order to faithfully reproduce an operation (operation at the time of an interrupt, etc.) that depends on a pipeline structure. It is necessary to simulate the structure faithfully.

However, in the case of a simulator that faithfully reproduces the pipeline structure, when the execution of the simulation is stopped at the time when a specified instruction is completed and the internal state is output, the instruction following the instruction is already executed. A problem arises in that the result of processing of the subsequent instruction that has flowed through the pipeline and has been performed halfway is reflected in the output.

FIG. 1 shows an example of a processing flow when a pipeline has a four-stage structure. A to D shown in the vertical direction indicate pipeline processing stages (hereinafter, referred to as stages), and instruction processing is performed step by step in the order of A, B, C, and D. In addition, every time the entire process advances by one step, the process advances by one in the right direction in the figure. The numbers written above are the instruction numbers, 0, 1,
It is assumed that the program is executed so as to be executed in order as shown in 2 and 3.

For example, in step 11 in FIG. 1, instruction 3 executes the processing of the stage of stage A, instruction 2 executes the processing of the stage of stage B, instruction 1 executes the processing of the stage of stage C, and instruction 0 executes the processing of the stage of stage C. This indicates that the processes in the stage D are performed simultaneously. Next step (Step 1 in FIG. 1)
In 2), each instruction proceeds one by one, and instruction 3 performs the processing of stage B, instruction 2 performs the processing of stage C, instruction 1 performs the processing of stage D, and instruction 4 newly performs the processing of stage A. to go into. The instruction 1 has completed all the processing here, and if "I want to stop the execution at the end of the instruction 1", the execution is stopped here.

FIG. 8 is a flow chart showing the configuration of a conventional system which is designed to stop execution when a specific instruction is completed. Each time the instruction is executed one step, it is determined whether or not the instruction specified in step 81 has been completed.
To stop all processing, and if not finished, continue execution and go to the next step.

[0008]

However, in the configuration of the conventional system as described above, as can be seen from step 12 in FIG.
This means that the processing of 4 has already started.

As a result, even if the internal state is output here,
The user has to analyze the output result in consideration of the influence of the subsequent instructions 2, 3, and 4, which causes a problem that software debugging becomes difficult.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. The present invention solves the above problem by analyzing the simulation result by preventing the subsequent instruction from being affected when a specific instruction is stopped in a simulation reproducing a pipeline structure. And a digital computer simulator that can improve the development efficiency in software development by the user.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a digital computer simulator according to the present invention checks in advance in an initial stage of pipeline processing whether an instruction satisfies a simulator execution stop condition. In such a case, the subsequent instruction is not executed until the operation of the instruction is completely completed and the simulation is stopped, or an instruction that does nothing (hereinafter, NOP) is inserted, and the execution is stopped when the instruction is executed again. The subsequent instruction is executed again from the stage where the instruction was stopped. When the simulator execution is stopped, the instruction following the instruction to be stopped is not sent to the pipeline, so that the subsequent instruction is not executed. It is characterized in that the effect can be eliminated and the execution result can be analyzed without the user being aware of the pipeline operation.

As described above, when stopping at a specific instruction in a simulation that reproduces a pipeline structure, the effect of a subsequent instruction does not occur, and the analysis of the simulation result can be facilitated. Can improve development efficiency.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital computer simulator according to claim 1 of the present invention is a digital computer simulator used for developing software for operating a digital computer having a pipeline structure, wherein the pipeline computer has a pipeline structure. At the initial stage of processing in the structure, it checks whether an instruction that satisfies the condition for stopping execution has been received, and if so, stops the execution of the subsequent instruction until the instruction is completed, or executes an Configure to be inserted.

According to this configuration, when the execution of the simulator is stopped, the instruction following the instruction to be stopped is not sent to the pipeline, so that the influence of the instruction following the instruction is eliminated, and the user can execute the pipeline operation. Make it possible to analyze execution results without being conscious.

Hereinafter, a digital computer simulator according to an embodiment of the present invention will be specifically described with reference to the drawings. FIG. 2 shows the flow of instructions when the execution of a program is to be stopped when the instruction of instruction 1 is completely completed, assuming a pipeline having a four-stage configuration. The processing procedure is shown in the flowchart of FIG. In FIG. 2, 21 to 26 represent N
The reference numeral 21 denotes a code attached to the processing for stopping the execution of the normal instruction to which the OP insertion processing has been added, and 21 denotes a flag (NOPFLG)
, And 22 to 26 indicate each processing. In FIG. 9, reference numerals 91 to 99, 9a, and 9b denote the respective processes of the execution stop when the flag to which the NOP insertion process is added is used.

First, it is determined whether or not the instruction at the stage A, which is the first processing stage in the pipeline processing, satisfies the execution end condition (instruction number = 1, simply referred to as instruction 1). At this time, if the conditions are not satisfied, the execution of the simulation proceeds as it is. If the condition is satisfied, a flag (hereinafter, referred to as NOPFLG) for waiting for the next instruction to come to stage A is set.

Then, the subsequent instruction is stopped until the instruction 1 completes the final stage (stage D), or NO
Step forward while inserting P step, then N
Reset the OPFLG to stop the program execution.

As a result, as shown in FIG. 2, the processing of the subsequent instruction can be stopped at the time of the STOP without any execution. Thereafter, when the execution is resumed again, the subsequent instruction is executed from the stage A.

FIG. 3 shows an instruction flow when the instruction to be stopped is a multi-cycle instruction. In FIG. 3, reference numerals 31 to 35 denote the respective processes of the execution stop in a plurality of cycles including the NOP insertion process.

Even if it is determined that instruction 1 has reached stage A,
The flag (NOPFLG) is not set in the first step in which the processing in the stage A is not completely completed, and the flag (NOPFLG) is set in the next cycle in which all the processing in the stage A is completed.

FIG. 4 shows the flow of instructions when the instruction to be stopped is an instruction dependent on the flow of the pipeline. In addition, in FIG.
This is a code attached to each process of stopping execution in the case of an instruction that cannot be inserted with NOP added with OP insertion processing.

If it is determined that the instruction 1 has arrived at the stage A, it is checked whether there is any harm caused by inserting the NOP, and if so, the user is warned of the harm,
After performing the exception processing for shifting the stop instruction to the next instruction (instruction 2), the execution is continued without inserting the NOP. When the instruction 2 reaches the stage A, the flag (NOPFL) is renewed.
G) is set, and when the instruction 2 has completed the stage D, the flag (NOPFLG) is reset to stop the execution.

In the embodiment of the present invention, the above N
Instead of using a flag like OPFLG, a counter can be used to insert a NOP. FIG. 5 shows the flow of instructions and changes in the counter when a counter is used, and FIG. 10 is a flowchart showing a processing procedure for realizing the flow. In FIG. 5,
Numerals 51 to 56 denote symbols attached to the execution stop processing when the counter to which the NOP insertion processing is added is used.
Numeral 3 indicates a counter, and others indicate each processing. In FIG. 10, reference numerals 101 to 109 and 10a to 10c denote NO.
This is a code given to each processing of execution stop when the counter to which the P insertion processing is added is used.

First, the counter is usually set to zero. Then, when the instruction to be stopped comes to the stage A, the counter is set to (the number of pipeline stages -1). Thereafter, the counter is decreased by one at a time until the value becomes zero, and if the NOP is inserted or the subsequent instruction is stopped, the subsequent instruction does not enter the pipeline until the instruction to be stopped comes to stage D.

FIG. 6 shows the flow of instructions when the instruction to be stopped is a multi-cycle instruction by a method using a counter. In addition, in FIG.
Reference numeral 66 denotes a code attached to processing for stopping execution of a plurality of cycle instructions when a counter to which NOP insertion processing is added is used, reference numeral 64 denotes a counter, and the other denotes each processing.

Even if it is determined that instruction 1 has reached stage A,
In the first step where the processing in the stage A is not completed, the counter is not set, and the flag (NOPFLG) is set in the next cycle in which all the stages A are completed.

FIG. 7 shows an instruction flow in the case where the instruction to be stopped is an instruction that depends on the flow of the pipeline in the method using the counter. In FIG. 7, reference numerals 71 to 76 denote symbols attached to processing for stopping execution of an instruction that cannot be inserted with NOP when a counter to which NOP insertion processing is added is used. Indicates processing.

When it is determined that the instruction 1 has arrived in the stage A, it is checked whether there is any harm caused by inserting the NOP, and if so, the user is warned of the harm,
After performing the exception processing for shifting the stop instruction to the next instruction (instruction 2), the execution is continued without inserting the NOP. Then, when the instruction 2 reaches the stage A, the counter is set again,
Execution stops when instruction 2 finishes stage D.

[0029]

As described above, according to the present invention, when the execution of the simulator is stopped, the instruction following the instruction to be stopped is not sent to the pipeline, thereby eliminating the influence of the subsequent instruction. Thus, the execution result can be analyzed without the user being aware of the pipeline operation.

Therefore, when stopping at a specific instruction in a simulation reproducing the pipeline structure, it is possible to prevent the influence of a subsequent instruction from appearing and to facilitate the analysis of the simulation result. Development efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a program flow when execution is stopped in a conventional digital computer simulator.

FIG. 2 is an explanatory diagram of a program flow when execution of a normal instruction is stopped in the digital computer simulator according to the embodiment of the present invention;

FIG. 3 is an explanatory diagram of a program flow when execution is stopped by a multi-cycle instruction in the embodiment.

FIG. 4 is an explanatory diagram of a trouble avoiding operation when NOP is inserted into a command to be stopped in the embodiment.

FIG. 5 is an explanatory diagram of a program flow when execution of a normal instruction is stopped when a counter is used in the embodiment;

FIG. 6 is an explanatory diagram of a program flow when execution is stopped by a multi-cycle instruction when a counter is used in the embodiment.

FIG. 7 is an explanatory diagram of a trouble avoiding operation when a NOP is inserted into a stop target instruction when a counter is used in the embodiment.

FIG. 8 is a flowchart showing a configuration for stopping execution at a specific instruction in the conventional method.

FIG. 9 is an example of a flowchart showing a configuration of a simulator of the digital computer according to the embodiment of the present invention;

FIG. 10 is an example of a flowchart in the case where a counter is used in the embodiment.

[Explanation of symbols]

 21 Flag (NOPFLG) 53, 64, 74 Counter

Claims (1)

[Claims] 1. A simulator for a digital computer used for developing software for operating a digital computer having a pipeline structure, wherein an instruction that satisfies an execution stop condition is received at an initial stage of processing in the pipeline structure. Check if it is satisfied, and if it satisfies, perform processing to stop execution of the subsequent instruction until the instruction is completed,
Or a digital computer simulator characterized by inserting an instruction to do nothing.