JPH11288247A - Electronic source driving device, method therefor and image forming device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the distribution of the light emitting luminance of a display panel and to uniformize luminance by varying the appearing order of pulses with plural types of time margins in a column driving means. SOLUTION: A modulation signal generation part 480 generates pulses to 480 column direction wirings X1 from X480 at specified timing. Length obtained by dividing a period 1H when a prescribed row direction wiring is selected into eight wirings is set to be a basic pulse period t0. A pulse period corresponding to the respective bits of picture data shown by eight gradations, namely, three bits is set. A driving signal is applied in the pulse period corresponding to the bit whose value is '1'. Namely, the pulse period corresponding to the bit whose value is '1' is turned on. The generation periods of the pulses corresponding to the respective bits are dispersed for the respective column direction wirings. Thus, the luminance irregularity of a picture is reduced by dispersing the position of the pulses in the period 1H when the prescribed row direction wiring is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron source driving apparatus and method, and an image forming apparatus as an application thereof.

[0002]

2. Description of the Related Art In recent years, research and development of thin and large screen display devices have been actively conducted. The present inventor has been conducting research using a cold cathode device as an electron source as a thin large-screen display device.

Conventionally, two types of electron-emitting devices, a hot cathode device and a cold cathode device, are known. Among these, among the cold cathode devices, for example, a surface conduction type emission device, a field emission type device (hereinafter referred to as FE type), a metal / insulating layer / metal type emission device (hereinafter referred to as MIM type), and the like are known. I have.

As a surface conduction type emission element, for example,
M. I. Elinson, Radio Eng. Ele
ctron Phys. , 10, 1290, (196
5) and other examples described later are known.

[0005] The surface conduction electron-emitting device utilizes a phenomenon in which electron emission occurs when a current flows in a small-area thin film formed on a substrate in parallel with the film surface. As this surface conduction type emission element, Sn described by Elinson et al.
In addition to those using an O2 thin film, those using an Au thin film [G. Dittmer: "Thin Solid Fi
lms ", 9,317 (1972)] and In2O3 /
According to SnO2 thin film [M. Hartwell an
d C.I. G. FIG. Fonstad: "IEEE Tran
s. ED Conf. , 519 (1975)] and those using carbon thin films [Hisashi Araki et al .: Vacuum, Vol. 26,
No. 1, 22 (1983)].

[0006] As a typical example of the element structure of these surface conduction electron-emitting devices, FIG. Hartwel
1 shows a plan view of an element according to the present invention. In FIG.
Reference numeral 1 denotes a substrate, and reference numeral 3004 denotes a conductive thin film made of a metal oxide formed by sputtering. The conductive thin film 3004 is formed in an H-shaped planar shape as shown. An electron emission portion 3005 is formed by performing an energization process called energization forming described later on the conductive thin film 3004. The interval L in the figure is 0.5 to 1 [mm], and W is
It is set at 0.1 [mm]. In addition, for convenience of illustration, the electron emitting portion 3005 is shown in a rectangular shape at the center of the conductive thin film 3004, but this is a schematic one, and the position and shape of the actual electron emitting portion are faithfully represented. Not necessarily.

M. In the above-described surface conduction electron-emitting device including the device by Hartwell et al., The electron-emitting portion 3005 is formed by subjecting the conductive thin film 3004 to an energization process called energization forming before electron emission.
It was common to form That is, the energization forming is to form an electron emission portion by energization. For example, a constant DC voltage is applied to both ends of the conductive thin film 3004, or a voltage is increased at a very slow rate of, for example, about 1 V / min. Energized by applying a DC voltage
The electron emitting portion 30 in a state where the conductive thin film 3004 is locally destroyed, deformed or deteriorated, and is in an electrically high resistance state.
05 is formed. Note that a part of the conductive thin film 3004 that has been locally broken, deformed, or altered includes
Cracks occur. When an appropriate voltage is applied to the conductive thin film 3004 after the energization forming, electron emission is performed in the vicinity of the crack.

An example of the FE type is disclosed in, for example, W.S. P.
Dyke & W. W. Dolan, "Field emi
session ", Advance in Electro
nPhysics, 8, 89 (1956), or C.I. A. Spindt, "Physicalpr
operations of thin-film figure
ld emissioncathodes with
molybdenium cones ", J. App.
l. Phys. , 47, 5248 (1976).

As a typical example of the FE type device configuration, FIG. A. 1 shows a cross-sectional view of a device by Spindt et al. In the figure, reference numeral 3010 denotes a substrate;
Is an emitter wiring made of a conductive material, 3012 is an emitter cone, 3013 is an insulating layer, and 3014 is a gate electrode. This device comprises an emitter cone 3012 and a gate electrode 3
By applying an appropriate voltage during 014, field emission is caused from the tip of the emitter cone 3012.

FIG. 4 shows another element structure of the FE type.
There is also an example in which an emitter and a gate electrode are arranged on a substrate almost in parallel with the plane of the substrate, instead of the laminated structure shown in FIG.

As an example of the MIM type, for example,
C. A. Mead, “Operation of tun
nel-emission Devices, J. et al. Ap
pl. Phys. , 32, 646 (1961). FIG. 49 shows a typical example of an MIM type element configuration.
Shown in The figure is a sectional view, in which 3020 is a substrate, 3021 is a lower electrode made of metal, 3022 is a thin insulating layer having a thickness of about 100 Å, 3023
Is an upper electrode made of a metal having a thickness of about 80 to 300 angstroms. In the MIM type, the upper electrode 3023
By applying an appropriate voltage between the upper electrode 3023 and the lower electrode 3021, electrons are emitted from the surface of the upper electrode 3023.

The above-mentioned cold cathode device can obtain electrons at a lower temperature than the hot cathode device, and therefore does not require a heater for heating. Therefore, the structure is simpler than that of the hot cathode element, and a fine element can be produced. Also,
Even if a large number of elements are arranged on a substrate at a high density, problems such as thermal melting of the substrate hardly occur. In addition, unlike the hot cathode device, which operates by heating the heater, the response speed is slow, and the cold cathode device also has the advantage that the response speed is fast.

For this reason, research for applying the cold cathode device has been actively conducted.

For example, a surface conduction electron-emitting device has the advantage that a large number of devices can be formed over a large area because it has a particularly simple structure and is easy to manufacture among cold cathode devices. Therefore, for example, Japanese Patent Application Laid-Open No.
As disclosed in 332, methods for arranging and driving a large number of elements are being studied.

As for the application of the surface conduction electron-emitting device, for example, an image forming apparatus such as an image display device and an image recording device, a charged beam source, and the like have been studied.

In particular, as an application to an image display device, as disclosed in US Pat. No. 5,066,883, JP-A-2-257551 and JP-A-4-28137 filed by the present applicant, a surface conduction type emission element is disclosed. An image display device using a combination of a phosphor that emits light by irradiation with an electron beam has been studied. An image display device using a combination of a surface conduction electron-emitting device and a phosphor is expected to have better characteristics than other conventional image display devices. For example, compared to a liquid crystal display device that has become widespread in recent years, it can be said that it is superior in that it does not require a backlight because it is a self-luminous type and that it has a wide viewing angle.

A method of driving a large number of FE types is disclosed in US Pat. No. 4,904,89 by the present applicant.
5 is disclosed. Further, as an example in which the FE type is applied to an image display device, for example, R.F. The flat panel display reported by Meyer et al. Is known [R. Meye
r: "Recent Development M
microtips Display at LETI ",
Tech. Digest of 4th Int. V
acuum Microele-tronics C
onf. , Nagahama, pp .; 6-9 (199
1)].

An example in which a number of MIM types are arranged and applied to an image display device is disclosed in, for example, Japanese Patent Application Laid-Open No.
55738.

[0019]

SUMMARY OF THE INVENTION The present inventors have developed various materials, including those described in the above-mentioned prior art.
We have tried cold cathode devices with manufacturing method and structure. Furthermore, research has been conducted on a multi-electron beam source in which a large number of cold cathode devices are arranged, and on an image display device using the multi-electron beam source.

The inventors have tried a multi-electron beam source by an electric wiring method shown in FIG. 50, for example. That is, it is a multi-electron beam source in which a large number of cold cathode devices are two-dimensionally arranged and these devices are wired in a matrix as shown.

In the figure, 4001 schematically shows a cold cathode element, 4002 shows a wiring in the row direction, and 4003 shows a wiring in the column direction. Row direction wiring 4002 and column direction wiring 400
3 actually has a finite electrical resistance,
In the drawing, they are shown as wiring resistances 4004 and 4005. The above-described wiring method is called simple matrix wiring.

Although a 6 × 6 matrix is shown for convenience of illustration, the size of the matrix is not limited to this. For example, in the case of a multi-electron beam source for an image display device, a desired image is displayed. Elements that are sufficient for displaying are arranged and wired.

In a multi-electron beam source in which cold cathode elements are arranged in a simple matrix, a row-direction wiring 4002 and a column-direction wiring 400 are used to output a desired electron beam.
3 is applied with an appropriate electric signal. For example, to drive one row of the cold cathode devices in the matrix, a selection voltage Vs is applied to the row direction wiring 4002 of the selected row,
At the same time, the non-selection voltage Vns is applied to the row direction wiring 4002 of the non-selected row. In synchronization with this, the column direction wiring 4003
Is applied with a drive voltage Ve for outputting an electron beam. According to this method, wiring resistances 4004 and 4004
If the voltage drop due to 5 is ignored, the voltage of Ve-Vs is applied to the cold cathode elements of the selected row, and the voltage of Ve-Vns is applied to the cold cathode elements of the non-selected rows. V
If e, Vs, and Vns are set to voltages of appropriate magnitudes, an electron beam of a desired intensity should be output only from the cold cathode elements in the selected row, and a different drive voltage Ve is applied to each of the column wirings. If applied, each of the elements in the selected row should output a different intensity electron beam. Further, if the length of time during which the drive voltage Ve is applied is changed, the length of time during which the electron beam is output should be changed.

In the above description, Ve-
Electrons are emitted by applying an element application voltage Vf of Vs. Another method of obtaining an electron beam from a multi-electron beam source with a simple matrix wiring is a voltage source for applying a drive voltage Ve to column-directional wiring. There is also a method of driving by connecting a current source for supplying a current necessary to output a desired electron beam instead of connecting the current source. In this case, the current flowing through the electron beam source is hereinafter referred to as element current If, and the amount of emitted electron beam is the emission current Ie.
Call.

Therefore, a multi-electron beam source in which cold cathode elements are arranged in a simple matrix wiring has various applications. For example, if an electric signal corresponding to image information is appropriately applied, it is suitable as an electron source for an image display device. Can be used.

However, a multi-electron beam source in which cold-cathode devices are wired in a simple matrix actually has the following problems.

According to the research of the present researchers, the cause of the uneven brightness is that a voltage drop occurs due to the electric resistances 4004 and 4005 of the wiring and is smaller than the drive signal originally intended for each surface conduction electron-emitting device. It turned out that it was because only the voltage was applied. This will be described in detail below. Note that a signal applied to the row direction wiring 4002 is referred to as a scanning signal, and a signal applied to the column direction wiring 4003 is referred to as a modulation signal.

In the multi-electron beam source as described above,
In general, the image display is basically performed by changing the length of time during which the drive voltage Ve is applied to change the length of time during which the electron beam is output. First, this image display driving will be described with reference to FIGS. 51 and 52 showing a general driving mode of a multi-electron beam source.

In FIG. 51, Dy1 to DyN represent modulation signal supply terminals, and Dx1 to DxM represent scan signal supply terminals.
In addition, all the surface conduction electron-emitting devices 4001 have substantially equal resistance values Rd. The scanning signal supply terminals Dx1 to Dxm are sequentially selected, and a negative pulse (voltage Vs) as a scanning signal is applied. A positive pulse (voltage Ve) having a desired length is applied to each of the modulation signal supply terminals Dy1 to Dyn.

FIG. 52 is a time chart for explaining a scanning signal and a modulation signal in a general pulse width modulation driving method. As shown in FIG. 52, in the period K, the cold cathode elements in the first row in FIG. 51 are driven, in the period K + 1, the cold cathode elements in the second row are driven, and in the period K + 2, the cold cathode elements in the third row are driven. And the row direction wiring 4002
, A modulation signal is applied to the column wiring 4003. As the modulation signal, for example, as shown in FIG. 52, pulses having different time widths with rising edges are applied. Here, the image is displayed by controlling the amount of emitted electrons by modulating the pulse width of the modulation signal in accordance with the image signal to make it longer or shorter. A pulse having a polarity opposite to the above-described modulation signal is applied to the row direction wiring 4002 of the selected row, and the row direction wiring of the row not selected is grounded to the ground potential. As shown in FIG. 52, the driving circuit on the row direction wiring side switches the selected row every one horizontal scanning period and applies this voltage.

The cold cathode device used in the above-mentioned multi-electron beam source generally has the following characteristics. That is, first, a certain voltage (this is called a threshold voltage Vth)
When a voltage having the above magnitude is applied to the element, the emission current Ie sharply increases. On the other hand, at a voltage lower than the threshold voltage Vth, the emission current Ie is hardly detected.

That is, the non-linear element has a clear threshold voltage Vth with respect to the emission current Ie.

Second, since the emission current Ie changes depending on the voltage Vf (Ve-Vs) applied to the device, the voltage V
The magnitude of the emission current Ie can be controlled by f.

Third, since the response speed of the current Ie emitted from the device is fast with respect to the voltage Vf applied to the device, the amount of charge of the electrons emitted from the device depends on the length of time during which the voltage Vf is applied. Can control.

Fourth, when a voltage higher than the threshold voltage Vth is applied to the element, the element current If rapidly increases.
On the other hand, the element current flowing below the threshold voltage is very small.

In particular, according to the first and fourth characteristics, when Vth is applied to the cold-cathode device, almost no current flows when the device current If or the emission current Ie is applied. × Vth), the amounts of If and Ie increase sharply.

By setting the peak values of the scanning signal and the modulation signal to -Vth and + Vth, respectively, in the above-mentioned time chart, the time width of the modulation signal from the cold cathode device arranged in the selected row is adjusted. Thus, an image can be displayed line by line by emitting electrons, and an image of the entire screen can be displayed by switching the selected line every horizontal period.

Now, let us consider a case where the multi-beam electron source shown in FIG. 51 is driven row by row as described above, that is, when one of the row direction wirings 4002 is selected. At this time,
Wiring resistances 4004 and 40 of row and column wirings themselves
05 causes a voltage drop there. On the other hand, the drive current flowing through each surface conduction electron-emitting device on the line injected from the column direction wiring 4003 flows through the selected row direction wiring 4002. Accordingly, the voltage drop particularly in the row direction wiring 4002 becomes a non-negligible magnitude, and a distribution is generated in the voltage applied to the surface conduction electron-emitting device connected to the selected row direction wiring 4002. This causes a problem that uniform electron emission cannot be obtained.

As described above, the magnitude of the resistance component of the cold cathode device changes depending on the voltage applied to both ends of the device. That is, in the state of receiving the semi-selective driving in the simple matrix driving, the resistance component shows a value larger than that in the case of receiving the selective driving. Therefore, the element that has been subjected to the half-select driving can be regarded as being in the released state, and the equivalent circuit of the multi-beam electron source having the M-row and N-column surface conduction electron-emitting element is selectively driven with reference to FIG. It can be shown by the equivalent circuit of FIG. 53 using only the elements on the line. In the figure, a wiring resistance 4006 indicates a cumulative resistance from a driving end of each column direction wiring 4003 to a driven element. The drive current flowing through each row direction wiring 4003 and flowing to each element merges with the row direction wiring 4002 and flows.

As a result, a voltage drop occurs due to the wiring resistance 4004 of the row wiring 4002. Therefore,
Focusing on a certain row, plotting the potential on the scanning signal line side of each surface conduction electron-emitting device results in FIG. here,
The change in the potential is not uniform because the current flowing through the scanning signal line increases as the position approaches the scanning signal supply terminals Dx1 to Dxm, and the voltage drop also increases. Since the potentials on the modulation signal line side are equal, the voltage applied to each surface conduction electron-emitting device is eventually as shown in FIG. As a result, the beam current of the electron beam emitted from each surface conduction electron-emitting device is
The value increases on the side closer to the scanning signal supply terminals Dx1 to Dxm, and decreases on the far side.

These variations in the beam current amount are extremely inconvenient because they appear as brightness variations when applied to an image display device. In particular, when a large-capacity display device with a large number of pixels is to be realized, the ratio of the above-mentioned variation becomes remarkable, and the uniformity of the display luminance distribution when an image is displayed is deteriorated. is there.

As a method for solving the above-mentioned problem of voltage drop, it has been proposed to apply a scanning signal to both ends of the row wiring.

FIG. 56 is a diagram for explaining a method of driving by applying a scanning signal to both sides of the row direction wiring. In this figure, 1
The cold-cathode elements of the row are driven, and a scanning signal (peak value-Vth) is applied to both ends of the row-directional wiring of the first row, and a modulation signal (peak value + Vth) is applied to each column-directional wiring. Therefore,
Ideally, a voltage of 2 × Vth is applied to the cold cathode elements in the first row, and a voltage of Vth or less is applied to the cold cathode elements in the other rows. However, as shown in FIG. Due to the voltage drop, on both ends of the first row in the row direction wiring, -V
Even at th, the potential increases at the center. For this reason, as for the voltage applied to each cold cathode element in the first row, a voltage of 2 × Vth is applied to the element close to the end of the row direction wiring, while the applied voltage is 2 × V to the central cold cathode element. It was lower than Vth.

Due to the distribution of the applied voltage as described above, there has been a problem that the emission current Ie also becomes small at the center portion under the influence of the applied voltage. As described above, even when a configuration in which a scanning signal is applied to both ends is employed, the effect of the voltage drop still appears, and problems such as uneven brightness have occurred.

As described above, when an image is formed by using a large number of electron-emitting devices, the power consumption as a sum thereof also poses a serious problem. That is, the emitted electron beam is accelerated by a high anode voltage (hereinafter referred to as Va) and collides with the phosphor. However, as the number of electron-emitting devices increases, the power consumption of the device increases. Assuming that the number of the electron-emitting devices is (m × n), the power consumption W generated in the high voltage portion is W = (m × n) × Ie × Va. Further, when the time component during driving is taken into consideration, the power consumption W is expressed as follows: W = ｍ (m × n) × Ie × Va 、 dt, for example, an electron-emitting device when applied to an image device for displaying a Tv signal or a computer signal. , The power consumption becomes a serious problem. There is also a problem that the heat generated by the fluorescent plate that is hit by the electron beam increases.

The present invention has been made in view of the above problems, and improves the distribution of light emission luminance of a display panel caused by the resistance of the row wiring, makes the luminance uniform, and improves the luminance of the entire image display device. It is an object of the present invention to provide an electron source driving apparatus and method and an image forming apparatus that reduce the non-uniformity of the electron source.

Another object of the present invention is to solve the problem of causing uneven brightness in an image and greatly improve the practical performance of a thin, large-area, large-capacity image forming apparatus.

Another object of the present invention is to reduce the number of elements that are simultaneously energized during a period in which a certain row-direction wiring is selected, and to reduce the amount of current flowing through the selected row-direction wiring. Another object of the present invention is to reduce the effect of voltage drop due to wiring resistance.

Another object of the present invention is to suppress the magnitude of an input signal so that the total amount of electron emission does not exceed a certain value. An object of the present invention is to reduce the non-uniformity of the voltage applied to the power supply and to suppress the increase in power consumption and the heat generation of the target.

Another object of the present invention is to suppress the average luminance of the image display device to a certain reference value or less, thereby eliminating the uneven luminance more efficiently, and further reducing the power consumption of the image forming apparatus and the fluorescent screen. The purpose is to suppress the generation of heat.

Another object of the present invention is to suppress the luminance distribution due to the voltage drop in the wiring by changing the conversion ratio in the modulation driving for converting the image signal into a signal having a length corresponding to the amplitude of the image signal. An object of the present invention is to make it possible to form a high-quality image with good characteristics.

Another object of the present invention is to provide a method for detecting or predicting the light emission luminance of an apparatus, based on an evaluation value obtained.
An object of the present invention is to make it possible to control the average luminance of the entire light-emitting screen so as not to exceed a certain value, to suppress an increase in power consumption and to suppress heat generation of the fluorescent screen.

Another object of the present invention is to suppress the average brightness of the image display device to a certain reference value or less, and to suppress the power consumption of the image forming device and the heat generated by the fluorescent plate.

Another object of the present invention is to control the average luminance so that, for example, an image input signal in which the luminance of the main object at the center of the image is high and the periphery thereof is low,
An object of the present invention is to provide good display without lowering the luminance of a main object.

[0055]

An electron source driving apparatus according to an embodiment of the present invention that achieves the above object has, for example, the following configuration. That is, a driving device for an electron source having a plurality of electron-emitting devices, wherein the plurality of electron-emitting devices are connected to a common row wiring and separate column wiring, and the plurality of electron emitting elements are arranged in the plurality of column directions based on image information. Determining means for determining the time width of the modulation signal to be applied to each of the wirings, and forming a pulse train of the time width determined by the determining means by a combination of a plurality of predetermined pulse application periods of the time width. Column driving means for applying a drive signal based on the pulse train to each of the plurality of column direction wirings, wherein in the column driving means, an appearance order of the plurality of types of time width pulses is determined for each of the plurality of column direction wirings. To be different.

[0056]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration example of an image display device according to a first embodiment.
FIGS. 2 and 3 are timing charts for explaining timings of some signals in the first embodiment.

In FIG. 1, reference numeral 1 denotes an image display panel.
It is assumed that the surface-conduction emission devices corresponding to the respective phosphors are arranged in a vertical matrix of R, G, and B and are arranged in a simple matrix by row-direction wiring electrodes and column-direction wiring electrodes. Hereinafter, the present embodiment will be described by taking as an example the case where the image display panel 1 is driven line-sequentially.

The input TV signal s 1 is decoded into analog R, G, B signals by the decoder section 2 and input to the analog pre-processing section 3. Analog preprocessing unit 3
Consists of a sync separation circuit, a color adjustment circuit, a contrast control circuit, a DC reproduction circuit, a brightness control circuit, a matrix circuit, a low-pass filter, etc., and performs signal level control, DC reproduction, and band-limited R, G, B signals for each color. To the A / D converter 4. The analog pre-processing unit 3 sends a synchronization signal (sync) for PLL to the timing control unit 5, and also outputs a luminance signal s20 obtained by mixing the R, G, B signals in the matrix unit to the video detection unit 13.
Send to

The A / D converter 4 digitizes the analog R, G, B signals in a required number of gradations, in this embodiment, in eight gradations, by the sampling clock s2 from the timing control section 5. Upon receiving the digital image signal s9 from the A / D converter 4, the digital processing unit 6 performs gamma processing, digital filter processing for contour enhancement and noise suppression, and synchronizes with the clock signal s3 from the timing control unit 5. Then, a digital image signal is output to the data rearranging section 7 (see FIG. 3). Further, the digital process unit 6 also performs contour emphasis control and contrast control based on the coefficient data s15 from the system control unit 14 (see FIG. 3).

The data rearranging section 7 has one horizontal period R,
G and B data 160 (s9) are time-axis-compressed in synchronization with the clock s4, and a data sequence signal s10 in which the data is rearranged in an order corresponding to the color arrangement of the phosphor is generated. The data is transferred as 480 serial image data per line. Therefore, clock s4 is equal to clock s4.
It has three times the frequency of 3 (see FIG. 3).

The shift register 8 reads the serial image data s10 by the shift clock s6, converts 480 serial image data per line into parallel data, and sends the parallel data to the modulation signal generator 9 during the horizontal blanking period.

The modulation signal generator 9 forms a drive signal by a pulse width modulation method, and is composed of 480 pulse width modulators corresponding to the number of surface conduction type emission elements in one row. Then, a pulse signal having a time width proportional to the size of the image data read into each pulse width modulator is converted by the pulse width modulation signal s7 and possibly the pulse rearrangement signals s22 and s23 during one horizontal period. Is generated and sent to the horizontal drive driver 10.

The horizontal drive driver 10 includes a Vf controller 15
And outputs a drive signal to the image display panel 1 in which the voltage amplitude Ve of the pulse signal applied to the surface conduction electron-emitting device is controlled by the signal s17.

The shift register 11 receiving the timing signal s 8 (V_START, H_CLK) for row scanning from the timing control unit 5 sends a row selection signal for scanning to the vertical drive driver 12. The vertical drive driver 12 is composed of switch elements such as transistors for 240 rows, becomes conductive when selected, and applies the bias Vs sent from the Vf control unit 15 to the image display panel 1 (see FIG. 2).

As described above, since the vertical drive driver 12 sequentially selects the scanning of the image modulation data output from the horizontal drive driver 10 for each horizontal line, an image signal is displayed on the image display panel 1.

FIG. 4 shows the configuration of the system control unit 14.
The system control unit 14 includes a CPU 21, a ROM 22, an RA
M23, EEPROM 24, A / D converter 25, D
/ A converter 26, I / O port 27,
The device is controlled by the program stored in M22. Output signals s13 and s1 of the D / A converter 26
4 is a contrast control and brightness control signal,
The signal is transmitted to the analog pre-processing unit 3 and controls the levels of R, G, B signals and the amount of DC reproduction. s16 is
The control signal of the element applied voltage Vf at the time of selection is
5 is transmitted. s18 is transmitted to the high voltage generator 17 that outputs the high voltage Va (s19) for accelerating the electron beam, and controls the high voltage Va (s19).

The user interface unit 16 transmits a user request such as image quality adjustment to the system control unit 14,
The display of various information from the system control unit 14 is performed by a signal s1.
Perform by 2.

Next, a method of generating a modulation signal (the operation of the modulation signal generation unit 9) in the image display device according to the first embodiment having the above-described configuration will be described.

FIG. 5 is a time chart showing an example of the output timing of the modulation signal according to the first embodiment. The modulation signal generator 9 generates a pulse for each of the 480 column wirings X1 to X480 at the timing shown in FIG.

For example, the period 1H during which a certain row-direction wiring is selected is divided into eight equal parts (233 equal parts (where X ^ Y represents X to the power of Y. The powers are the same hereinafter). Is used as the basic pulse period t0. Then, each bi of the image data represented by 8 gradations, that is, 3 bits
A pulse period corresponding to t is set, and a drive signal is applied in a pulse period corresponding to a bit having a value of “1”. That is, a 2 期間 0 bit has a pulse period of 2、２0 × t0 in length, a 2 ^ 1 bit has a pulse period of 2 ^ 1 × t0 in length, and a 2 期間 2 bit has 2 ^ 2. A pulse period having a length of × t0 is assigned, and a pulse period corresponding to a bit having a value of 1 is turned on.

In the example shown in FIG. 5, in the column direction wiring of X1, T7 is assigned to 2 ^ 0 bits, and T5, T is assigned to 2 ^ 1 bits.
6 and 2 ^ 2 bits are assigned T1 to T4. Then, when the value "3" is applied to the row of X1, the bits of 2 ^ 0 and 2 ^ 1 become 1, so that the drive signal is applied in the corresponding periods (T5, T6 and T7). You.

Further, as shown in FIG. 5, the generation period of the pulse corresponding to each bit is dispersed for each column-direction wiring. For example, in the column wiring of X2, T3 is
T1 and T2 are in the bit of ^ 1, and T5 to T8 are in the bit of 2 ^ 2.
Is assigned. Then, when "5" is applied to the row of X2, the bits of 2 ^ 0 and 2 ^ 2 become 1, and the drive signal is applied in the corresponding periods (T3 and T5 to T8).

As a result, for example, the column direction wirings X1, X2, X
The image data is 3, 5, 7, 1, 0,
In the case of 2,2,2,2,2,2,2,..., A pulse is generated during the period painted black in FIG.

By dispersing the positions of the pulses during the period 1H in which a certain row direction wiring is selected,
Voltage drop due to wiring resistance can be reduced, and uneven brightness of an image can be reduced.

The dispersion of the pulse positions in the modulation signal generator 9 described above can be realized by a circuit as shown in FIG. 6, for example. FIG. 6 shows the configuration of the modulation signal generator 9.
FIG. 3 is a diagram illustrating a circuit configuration example of one pulse width modulator. In the figure, reference numeral 31 denotes a counter which counts a clock having a period obtained by equally dividing one horizontal period (1H in FIG. 5) into eight and outputs the counted value. In this example, the counter 31 outputs 0 to 7 (3 bits) as the count value. A decoder 32 turns on a bit corresponding to the count value input from the counter 31 and outputs the bit. For example, while the input value from the counter 31 is 6, the sixth output bit is turned on. Reference numeral 33 denotes eight AND gates, each having one input connected to the output bit of the decoder 32 and the other input connected to each bit of the image data value.

The eight AND gates 33 correspond to the periods T1 to T8 of FIG. 5 in order from the top in FIG. 6, and their outputs are turned on and off according to the value of each bit of the connected image data. Is done. FIG. 6 shows a circuit configuration corresponding to the column wiring of X1 in FIG. 5, but in order to support other column wiring, the connection between the AND gate 33 and each bit of the pixel data is changed. It's clear what we need to do.

In the above embodiment, a TV signal is used as an input signal. However, the present invention is not limited to this. For example, NTSC, PAL, SECAM and HDTV M
The same concept can be used in USE. It will be apparent that the present invention can be similarly applied to, for example, a computer signal other than the TV signal.

When the luminance of the image data in one row is high, the temporal overlap of the pulses applied to each column direction wiring increases, and the effect of the dispersion of the driving pulses as described above decreases. I will. Therefore, when the brightness of the image data in one row is higher than a predetermined value, the value of the image data in the row may be reduced to improve the dispersibility of the driving pulse. This will be described later in a third embodiment.

[Second Embodiment] Next, as a second embodiment, another form of the signal generated by the modulation signal generator 9 will be described. FIG. 7 is a time chart illustrating an example of the output timing of the modulation signal according to the second embodiment. Second
In the embodiment, 480 column-directional wirings X1 to X480
, A pulse is generated at the timing shown in FIG. That is, the period 1H during which a certain row direction wiring is selected is set to 7
A period having a length equally divided (2 ^ 3-1) is defined as a basic pulse period t0. Then, as in the first embodiment, 8
A pulse having a length corresponding to each bit of image data represented by a gradation, that is, 3 bits, that is, a pulse having a length of 2２0 × t0, 2 ^ 1 × t0, and 2 ^ 2 × t0 is applied. At this time, as shown in FIG. 7, the generation period of the pulse corresponding to each bit is dispersed for each column wiring. For example, column direction wirings X1, X2, X3, X
The image data is 3, 5, 4, 1, 0, 2,
In the case of 2, 2, 2, 2, 2,..., A pulse is generated during the period painted black in FIG.

By dispersing the positions of the pulses during the period 1H in which a certain row direction wiring is selected,
Voltage drop due to wiring resistance can be reduced. As in the first embodiment, when the luminance of the image data in one row is higher than a predetermined value, the value of the image data in the row is reduced to improve the dispersibility of the driving pulse. Is also good.

The second embodiment described above and the first embodiment described above
In comparison with the first embodiment, since the unit time t0 is longer in the second embodiment, the luminance is relatively higher than in the first embodiment even at the same high voltage Va with the same emission current Ie. On the other hand, in the first embodiment, since there are more types of pulse rising positions than in the second embodiment, it is possible to reduce the number of elements that are simultaneously lit on a screen having a low luminance value as a whole, The reduction of the voltage effect due to the wiring resistance can be better achieved.

[Third Embodiment] Next, as a third embodiment, still another form of the signal generated by the modulation signal generator 9 will be described. FIG. 8 is a time chart illustrating an example of the output timing of the modulation signal according to the third embodiment.
In the third embodiment, a pulse is generated at the timing shown in FIG. 8 for each of the 480 column wirings X1 to X480. That is, the period 1H during which a certain row direction wiring is selected.
Is a basic pulse period t0, and a basic pulse application having a time width of the basic time width t0 is a period P0. A period including 2 ^ 0 basic pulse application periods P0 includes a first group, a period including 2 ^ 1 basic pulse application periods P0 includes a second group, and 2 ^ 2 basic pulse application periods P0. The period is the third group, and the period during which no pulse having the basic time width t0 is applied is the fourth period.
Group as a group.

Here, the first group is 2 ^ 0 of the image data.
, The second group corresponds to 2 ^ 1 bits of the image data, and the third group corresponds to 2 ^ 2 bits of the image data. Then, pulse width modulation is performed by a combination of these four types of groups. At this time, there are 2 ^ 3 basic pulse application periods P belonging to any of the four types of groups.
Change the appearance order of 0 for each column. For example, if the basic pulse application period belonging to the first group is P0-1, the basic pulse application period belonging to the second group is P0-2, and the basic pulse application period belonging to the third group is P0-3, one P0 -1,
There are two P0-2 and four P0-3, and the order of appearance of these seven basic pulse application periods is changed for each column wiring as shown in FIG. Then, as in the first embodiment, 8
Each bit of image data represented by gradation, that is, 3 bits is 1
If so, a pulse is generated during the period assigned to the corresponding group.

Further, in the third embodiment, the video signal detecting section 13 shown in FIG. 1 converts the luminance signal s20 from the analog preprocessing section 3 from the timing control section 5 to the gate signal for each field to which horizontal blanking is added. Integration is performed by s5 (see FIG. 2), the average value of the luminance signal is detected for each field, and transmitted to the system control unit 14 as a luminance signal s11.

In the system controller 14, the detected average luminance signal s 11 is converted by the A / D converter 25 into a CPU
21 (FIG. 4), and is compared with a reference value stored in the system controller 14. Detection average luminance signal s1
When 1 is larger than the reference value, level 4 in the third embodiment, the output signal s13 of the D / A converter 26
By controlling the contrast, and by suppressing the output pulse width from the horizontal drive driver 10 as a result,
The light emission luminance of the panel 1 is controlled to a predetermined reference value or less. In the present embodiment, the entire luminance level is reduced to １ ／. The control of the luminance level will be described in detail in an eighth embodiment.

Further, as shown in FIG. 8, the basic pulse application period P0 of the pulse corresponding to each bit is substantially randomly distributed for each column direction wiring. Here, for example, the column direction wiring X
Image data corresponding to 1, X2, X3, X4,.
In the case of 5, 7, 2, 0, 7, 7, 7, 7, 7, 7, 7,..., The detected average luminance signal s11 is larger than the reference value level 4, so that the entire luminance signal is １ ／. As 3,3
4, 1, 4, 4, 4, 4, 4, 4, 4,..., And a pulse is generated during the period painted black in FIG.

By simply dispersing the pulse positions during the period 1H during which a certain row direction wiring is selected, the number of simultaneously energized elements increases when the overall luminance level is high, and the pulse positions are dispersed. Although the effect obtained is weakened, the effect of reducing the voltage drop due to the wiring resistance is maintained by lowering the overall luminance level in that case as in the third embodiment. Furthermore, the problem that the amount of emitted electron beams increases with an increase in luminance and the power consumption of the device increases is also solved.

In the above, an example has been described in which the emission luminance is controlled by the luminance evaluation value using the luminance signal s20 from the analog preprocessing unit 3 in the case of the R, G, B vertical stripe arrangement. In this case, in the luminance signal s20, the R, G, and B signals are mixed at the same ratio (eg, s20 = 1/3 (R + G +
B)) If the numbers of R, G, and B phosphors are different, such as in a checkered arrangement, the luminance signal s20 is generated at that ratio.

[Fourth Embodiment] Next, a fourth embodiment will be described. FIG. 9 is a block diagram illustrating a configuration of a drive circuit portion that is a part of the image forming apparatus according to the fourth embodiment. Referring to FIG. 1, reference numeral 101 denotes a display panel using a multi-electron beam source; 102, a scanning-side driving circuit for scanning and driving selected lines for line-sequential display;
Is a modulation-side drive circuit that outputs a pulse signal based on an image as a drive signal, 104 is a voltage-pulse conversion circuit that converts an image data signal into a predetermined drive pulse, and 105 is a high-voltage power supply for accelerating emitted electrons. .

As described above, a voltage drop in the matrix wiring on the multi-beam electron source substrate causes a distribution in the voltage applied to each electron-emitting device. This distribution can be suppressed by reducing the wiring resistance or the driving current.

The operation of the drive circuit shown in FIG. 9 according to the fourth embodiment will be described below. First, a selection voltage is output from the scanning-side drive circuit 102 to a predetermined selection line according to a scanning control signal. Next, the voltage-pulse conversion circuit 1
In step 04, the image data signal corresponding to the selected line is converted into a pulse train corresponding to a pulse width corresponding to the amplitude of the signal, and the pulse signal is applied to the panel as a drive signal by the modulation side drive circuit 103. Display is performed by performing the above operation on the lines sequentially selected by the scanning side driving circuit 102.

Next, the operation of the voltage-to-pulse conversion circuit 104 will be described with reference to FIGS. FIG. 10 is a block diagram showing a detailed configuration of the voltage-to-pulse conversion circuit according to the fourth embodiment. In FIG.
Is a voltage-pulse train conversion circuit for converting a pulse train corresponding to a width corresponding to the amplitude of the image data signal. Also, 1
Reference numerals 42 to 144 denote pulse train rearranging circuits for rearranging the pulse trains converted by the voltage-pulse train converter 141 in accordance with the following rules.

First, the number of divisions P in one line scanning period is set to 3
(The number of pulse train rearranging circuits is at least 3
The voltage-pulse conversion circuit 104
Will be described. FIG. 11 is a diagram illustrating an example of an image signal corresponding to any three adjacent modulation-side terminals m-1, m, and m + 1. According to the display image, image signals having different amplitudes are input to three adjacent elements.

FIG. 12 shows the element number m−
FIG. 4 is a diagram illustrating a signal obtained by converting an image signal of 1, m, and m + 1 into a pulse width corresponding to an amplitude. In FIG. 12, one line scanning period refers to a time (1H, one horizontal period) allocated to a specific line when line driving is performed line by line when scanning one screen.

FIGS. 13 (1), (2) and (3) are block diagrams of the pulse train rearranging circuits 142, 143 and 144. The pulse train rearranging circuit 142 delays the signal for each pulse signal line by one line scanning period 1H.
A delay line has been inserted. The pulse signals x1, x4,..., M-1.
1 ′, x4 ′... M−1 ′. That is, as shown in FIG. 14, the output signal of the voltage-pulse train conversion circuit 141 corresponding to the element number m-1 is converted into the signal m-1 '.

In the pulse rearranging circuit 143, each pulse signal line is branched into a line into which a (4/3) · H delay line is inserted and a line into which a (1/3) · H delay line is inserted. Synthesized. In Gate-1, the gate timing signal s2 generated by the timing control unit 5
According to 2, when the signal s22 is 1, the line in which the 4/3 delay line is inserted is selected, and when the signal s22 is 0, the line in which the H / 3 delay line is inserted is selected. Thus, the pulse signals x2, x5,... Are output as signals x2 ′, x5 ′,. That is, as shown in FIG. 14, the output signal of the voltage-to-pulse train conversion circuit 141 corresponding to the element number m has a signal m 'in which some pulses are rearranged when the pulse width is equal to or more than (2/3) .H. Is converted to

Similarly, in the pulse rearranging circuit 144, each pulse signal line is branched into a line into which a (5/3) · H delay line is inserted and a line into which a (2/3) · H delay line is inserted. Combined in 2. In Gate-2, when it is 1 according to the gate timing signal s23, (5
/ 3) Selects the line in which the H delay line is inserted, and if 0, selects the line in which the (2/3) H delay line is inserted. Thereby, the pulse signals x3, x
.. M + 1 are output as signals x3 ′, x6 ′,. That is, as shown in FIG. 14, when the pulse width is H / 3 or more, the output signal of the voltage-pulse train conversion circuit 141 corresponding to the element number m + 1 is a signal m in which some pulses are rearranged.
Converted to +1 '.

Here, the pulse train rearranging circuits 143, 1
In 44, the reason why the pulse having the pulse width b or d is arranged in the first H / 3 period is that the pulse arrangement is different in the 1H period when the initial position where the pulse is arranged is changed for each different pulse train rearranging circuit. Since no pulse appeared, it was shifted to the initial position. In actual driving of the display panel, the operation described above may be performed for all element numbers.

If the above-described operation of the voltage-to-pulse conversion circuit is performed for the modulation signals corresponding to all the element numbers, it is possible to apply a drive signal that rises at different times depending on the element numbers when displaying an image. It becomes possible. Therefore, the number of electron-emitting devices driven simultaneously decreases, and the instantaneous value of the driving current flowing through the scanning-side wiring decreases. Therefore, as shown by the solid line in FIG. 15, it is possible to suppress the voltage drop in the row direction wiring. Note that the broken line in FIG. 15 shows a voltage drop when the electron source is driven by the above-described conventional method that does not disperse the rising timing of the pulse.

Further, in this embodiment, the case where the number of divisions P is set to 3 has been described. However, the present invention is not limited to this case. The effect is suppressed, and high-quality image display with uniform luminance distribution can be performed.

[Fifth Embodiment] FIG. 16 is a block diagram showing a configuration of a drive circuit portion of an image forming apparatus according to a fifth embodiment. In the same figure, the same numbers are given to those performing the same operation as FIG. In FIG. 16, reference numeral 106 denotes a voltage-pulse conversion circuit for converting an image data signal into a predetermined drive pulse. Compared with the voltage-pulse conversion circuit 104 according to the fourth embodiment, a configuration for controlling the pulse width based on the evaluation value of the luminance evaluation circuit 108 is added. Reference numeral 107 denotes an ammeter for measuring an emission current in the display panel 101, and reference numeral 108 denotes a luminance evaluation circuit for predicting luminance from the emission current.

As described above, a voltage drop in the matrix wiring on the multi-beam electron source substrate causes a distribution in the voltage applied to each electron-emitting device. This distribution can be suppressed by reducing the wiring resistance or the driving current.

The operation of the drive circuit shown in FIG. 16 according to the fifth embodiment will be described below. First, a selection voltage is output from the scanning-side drive circuit 102 to a predetermined selection line according to a scanning control signal. On the other hand, the voltage-pulse conversion circuit 10
6, a pulse train is generated based on the amplitude of the image data signal corresponding to the selected line and the luminance predicted by the luminance evaluation circuit 108, and the pulse signal is generated by the modulation side driving circuit 10
3 is applied to the display panel 101 as a drive signal. Display is performed by performing the above operation on the selected line to be sequentially scanned.

Next, the operation of the luminance evaluation circuit 108 will be described with reference to FIGS. FIG. 17 shows the output of the ammeter 107 when displaying an image for a plurality of screens. The electron-emitting devices are driven line-sequentially within the display period shown in the figure to display one screen. The flyback period is a period during which an image between screens seen in a television signal is not displayed, for example. FIG. 18 shows an output signal of the ammeter 107 when the output of the LPF is input to a low-pass filter (LPF) (not shown) included in the luminance evaluation circuit 108. This output signal is a signal indicating a gradual change in the average electron emission amount for one screen between the screens. That is, assuming that the luminance is proportional to the electron emission amount, this signal is a signal whose luminance is predicted.

FIG. 19 is a block diagram showing a detailed configuration of the voltage-to-pulse conversion circuit according to the fifth embodiment. Hereinafter, the operation of the voltage-pulse conversion circuit 106 will be described with reference to FIG. Also in this case, a case where the number of divided regions is set to 3 will be described as an example.

In FIG. 19, reference numeral 161 denotes a voltage-to-pulse train conversion circuit which determines a conversion coefficient of voltage-to-pulse width conversion according to the amplitude of the image data signal and the output of the luminance evaluation circuit 108, and Is converted into a pulse train having a width corresponding to these. 162 to 164 correspond to FIG.
This is a pulse train rearranging circuit that performs the same operation as the pulse train rearranging circuits 142 to 144 described in. The voltage-to-pulse conversion circuit 161 performs an operation of converting the modulation signal into a pulse having a length obtained by multiplying the level of the modulation signal by a conversion coefficient corresponding to the luminance signal predicted by the luminance evaluation circuit 108.

FIG. 20 is a diagram showing a signal obtained by converting an image signal corresponding to any three adjacent modulation-side terminals s-1, s, and s + 1 shown in FIG. 11 into a pulse by the voltage-pulse train conversion circuit 161. It is. The luminance when the pulse length is within substantially the entire period of one line scanning period (one horizontal period) is defined as the maximum luminance Bm, and the luminance evaluation value obtained from the luminance evaluation circuit 108 is defined as B. A value obtained by dividing the Bm value by a value obtained by multiplying the B value by 3 which is the number of divisions is defined as r (r = Bm ÷ (B × 3)). A signal obtained by multiplying the pulse length in FIG. 12 by r, which is a signal corresponding to luminance, is the pulse signal in FIG. However, when r is 1 or more (that is, B value is 1 / Bm value).
R is not multiplied. As a result of the above processing, the widths of the pulses a, b, and c always become equal to or less than 1/3 (1 / q) of the one-line scanning period 1H.

Next, as shown in FIG. 21, the position of the converted pulse is changed by the pulse train rearranging circuits 162 to 164 in each of the three periods of 1H, which is one line scanning period. To relocate. It is assumed that a circuit for rearranging the pulse train corresponding to the element number s-1 is a pulse train rearranging circuit 162. Similarly, for the element number s, the pulse train rearranging circuit 163 adds the element number s + 1.
Corresponds to the pulse train rearranging circuit 164. That is, the pulse train rearranging circuit 162 outputs the first H
The pulse train rearranging circuit 163 does not arrange a pulse during the first H / 3 period, and outputs a pulse having the pulse width b during the second H / 3 period. The pulse train rearranging circuit 164 is arranged in the third H / 3
, A pulse having a pulse width c is arranged, and no pulse is arranged in the first and second H / 3 periods. In actual driving of the display panel, the operation described above may be performed for all element numbers.

If the above-described operation of the voltage-to-pulse conversion circuit is performed for the modulation signals corresponding to all the element numbers, the driving signal that rises in one of three types of periods depending on the element numbers when displaying an image is displayed. Can be applied. As a result, the number of simultaneously driven electron-emitting devices is reduced, and the instantaneous value of the drive current flowing through the scanning-side wiring is reduced, so that a voltage drop in the wiring can be suppressed as described with reference to FIG. In addition, since the luminance is limited even when the entire screen becomes a bright screen, the effective current of the high-voltage power supply decreases, and the effect of suppressing power consumption can be obtained.

Also, the example in which the luminance evaluation circuit 108 evaluates the luminance by measuring the electron emission current flowing through the high-voltage power supply has been described. However, the luminance of the actual display surface may be measured using a luminance meter, or the modulation signal may be evaluated. Even when the luminance is predicted, the voltage drop in the wiring can be similarly suppressed.

In the present embodiment, the case where the number of divisions q is set to 3 has been described. However, the present invention is not limited to this. In other cases, the voltage effect on the wiring can be similarly suppressed.

[Sixth Embodiment] Next, a sixth embodiment will be described. Also in this embodiment, the scanning method is line-sequential scanning, and the electron emission period within one horizontal scanning time (1H) is controlled by the time width of the modulation signal in order to give a gradation to a display image. Is based on controlling the total amount of light emission of each pixel and expressing the gradation. In the sixth embodiment, the distribution (variation) of the electron emission amount and the luminance generated by the resistance of the wiring is particularly improved by the method described below.

First, the outline of the sixth embodiment will be described.
FIG. 22 is a diagram for explaining a method for driving the multi-electron source and the image display device according to the sixth embodiment. Sixth
In this embodiment, an example in which the number of row-direction elements M = 1000 and the number of column-direction elements N = 3000 will be described.

In FIG. 22, the display panel 201 has M row-directional wirings 202, N column-directional wirings 203, and N × M cold cathode elements 204. Vx1 to VxM applied to the ends of the respective wirings are voltages applied to the ends of the row direction wirings 202 from the first row to the Mth row, respectively, Vy1 to Vy
N is the column direction wiring 203 from the first column to the Nth column, respectively.
Represents the voltage applied to the end of the.

FIG. 23 shows voltage application (Vx1 to VxM, Vy1) to the row direction wiring and the column direction wiring according to the sixth embodiment.
FIG. 7 is a time chart showing the timings of FIG.
In FIG. 23, the cold cathode elements in the first row in the period K, the second row in the period K + 1, the third row in the period K + 2, and the period K + 3
In this example, a voltage equal to or higher than the threshold voltage Vth is applied to the cold cathode elements in the fourth row, and electrons are emitted from the cold cathode elements in each row.

In the period K, the scan signal Vx1 is changed to -Vth (in this embodiment, V
The cold cathode element was designed so that th = 7 V).
A modulation signal (peak value + Vth) having a time width corresponding to the image signal is applied to each column direction wiring. In the sixth embodiment, as shown in the time chart of FIG. 23, a modulation signal applied to each column-directional wiring includes a group which rises in synchronization with the start of one horizontal scanning period and a group which rises in synchronization with the end. Created in descending groups. Various methods can be applied to this grouping method, and the method will be described later.

By driving the display panel by dispersing the rising positions of the modulation signals as shown in FIG. 23, the signals pass through the cold cathode elements of the selected row from the modulation signal side to the row direction wiring of the selected row. The current flowing out can be dispersed in time. As a result, a voltage drop on the row direction wiring of the selected row can be reduced. Therefore, the distribution of luminance due to the voltage drop on the row direction wiring was reduced, and the uniformity of luminance was able to be improved.

Hereinafter, the grouping of the application timing of the modulation signal will be described in detail.

In the sixth embodiment, as an example of a method of dispersing a modulation signal, a pulse whose rising edge is synchronized with the beginning of one horizontal scanning period is applied to an odd-numbered column-direction wiring, and an even-numbered column-direction wiring is applied. A pulse whose falling edge is synchronized with the end of one horizontal scanning period is applied.

FIG. 24 is a view for explaining an image display device according to the sixth embodiment. The signal flow will be described with reference to FIG.

First, a video signal such as an NTSC signal is input to the decoder 221. FIG. 25 is a block diagram showing a detailed configuration of the decoder 221. As shown in FIG. 25, the decoder 221 includes a decoder unit 250, an analog preprocessing unit 251, an A / D converter 252, a digital processing unit 253, and the like. The decoder unit 250 includes a video intermediate frequency circuit and a video detection circuit, and decodes an input video signal such as an NTSC signal into analog R, G, and B signals. The analog pre-processing unit 251 includes a sync separation circuit, a color adjustment circuit, a contrast control circuit, a DC reproduction circuit, a brightness control circuit, a low-pass filter, and the like, and performs signal level control, DC reproduction, and band-limited R, G, B signals. Is output to the A / D converter 252 of each color. Further, a synchronization signal (sync) for the PLL is transmitted to the timing control circuit 223.
(FIG. 24).

The A / D converter 252 uses the sampling clock from the timing control circuit to convert the analog R,
The G and B signals are digitized with a necessary number of gradations. A / D
The digital processing unit 253 receiving the digital image signal from the converter 252 performs gamma processing, contour enhancement, and digital filter processing for noise suppression, and outputs the digital image signal to the data array conversion circuit 222 (FIG. 24). . Note that the synchronization signal Sync includes a vertical synchronization signal and a horizontal synchronization signal. R, G, and B include luminance data for each of red, green, and blue.

Returning to FIG. 24, the timing control circuit 223
Generates a timing control signal for adjusting the operation timing of each unit based on the synchronization signal sync supplied from the decoder 221. The flow of the timing signal from the timing control circuit 223 to each section is indicated by a dotted arrow in FIG.

The data array conversion circuit 322 includes the decoder 22
The luminance data R, G, and B of the three primary colors supplied from 1 are arranged according to the pixel arrangement of the display panel, and are output as serial digital image signals Data. In the sixth embodiment, as one example, the digital image signal Data
Is 8-bit data.

The digital image signal Data output from the data array conversion circuit 222 is sequentially stored in the S / P conversion circuit 224 based on the timing signal supplied from the timing control circuit. When the digital video signal for one horizontal period is accumulated, the S / P conversion circuit 224 transfers the digital video signal to the one-line memory 225 according to the timing signal sent from the timing control circuit 223. The output of the one-line memory 225 is connected to the input of the pulse width modulation circuit 226.

The pulse width modulation circuit 226 is mainly composed of a counter and a latch, and performs counting in accordance with the timing supplied from the timing control circuit, and performs 1 count.
This is a circuit for converting a pulse width modulation signal having a time width corresponding to a digital video signal supplied from a line memory.

FIG. 26 is a block diagram showing a configuration of a pulse width modulation circuit 226 according to the sixth embodiment. In the pulse width modulation circuit 226 of the sixth embodiment, as shown in FIG. 26, an up counter 240 is arranged in an odd-numbered column, and a down counter 241 is arranged in an even-numbered column. Each counter operates based on timing signals Load and CLK sent from the timing control circuit 223.

The up counter 240 corresponding to the odd-numbered column of the pulse width modulation circuit 226 changes its output to High in synchronization with the Load signal,
5, the data is loaded, the up-count is performed by the timing signal CLK, and the signal becomes Carry and its output becomes Low. As a result, the up counter 240 outputs a pulse that rises in synchronization with the start of one horizontal period and falls after a set period (pulse width) has elapsed.

On the other hand, the down counter 241 corresponding to the even-numbered column of the pulse width modulation circuit 226 sets the output to Low in synchronization with the Load signal, loads data from the one-line memory 225, and down-converts the data according to the timing signal CLK. The counting is performed, the output becomes high at the time of Borrow, and the output is low at the end of one horizontal period. As a result, the down counter 241 outputs a pulse that falls in synchronization with the end of one horizontal period.

FIG. 27 shows the above operation timing in a timing chart. FIG. 27 is a timing chart for explaining the operation of the pulse width modulation circuit 226 according to the sixth embodiment. Up counter 2 for odd columns
Since 40 is arranged, the pulse signal rises in synchronization with the start (data load) of one horizontal period, and after counting the CLK signal for the loaded data, the signal falls. On the other hand, a down counter 241 is arranged in an even-numbered column, and counts down from 255 in response to the CLK signal. Then, the pulse signal rises when the count value becomes smaller than the loaded data, and falls when the down counter becomes 0.

Returning to FIG. 24, the modulation signal voltage conversion circuit 227 converts the pulse width modulation signals Dy1 to DyN supplied from the pulse width modulation circuit 226 to the optimum voltage level for driving the display panel. is there. The display panel 201 has an Hv terminal as shown in the figure, and a high-voltage power supply Va is applied.

The scanning signal generating circuit 228 is a circuit composed of an M-bit shift register, a latch, and a transistor. The scanning signal generating circuit 228 applies a selection voltage to an end of the currently selected row direction wiring every horizontal scanning period. The ends of the unselected row wirings are grounded. Further, when one horizontal scanning period is completed, the selected row is switched and a voltage is similarly applied. Although the M outputs of the scanning signal generating circuit are not shown in FIG. 24, they are connected to both ends of each row-direction wiring so that the same voltage is applied to both ends.

FIG. 2 shows a time chart of the voltage applied to each row direction wiring and column direction wiring of the display panel.
It looks like 3. The selection signal is a rectangular wave having a peak value of −Vth having a time width of substantially one horizontal scanning period, and the modulation signal applied to each column direction wiring has a pulse width corresponding to the image of the row to be displayed. A pulse whose peak position is + Vth and whose rising position is synchronized with the beginning of one horizontal scanning period in odd-numbered column-direction wirings and whose falling position is at the end of one horizontal scanning period in even-numbered column-direction wirings A synchronized pulse is applied.

As described above, by dispersing the timing of applying the voltage of the modulation signal, the element current flowing from the column wiring to the selected row wiring can be dispersed. The voltage drop due to the wiring resistance on the row direction wiring can be reduced. As a result, the distribution of luminance due to the voltage drop due to the resistance of the wiring resistance, which was described in the subject, can be reduced, and a more uniform luminance than before can be obtained. Specifically, when the moving image was displayed by the general driving method, the distribution was clearly observed by the human eyes. However, when the moving image was driven by the driving circuit of the sixth embodiment, the distribution was almost invisible to the naked eye. Then I could not confirm.

As described above, according to the sixth embodiment, by controlling the rising position and the falling position of the modulation signal as described above, it is possible to reduce the influence of the wiring resistance and increase the uniformity of the luminance. did it.

[Seventh Embodiment] In the seventh embodiment,
A modification of the method of dispersing the modulated signal described in the sixth embodiment will be described. In the seventh embodiment, as a method of dispersing a modulation signal, a method of dispersing according to a video signal is employed. That is, the digital image signal corresponding to the time width of the pulse width modulation signal applied to each column direction wiring is 25
If it is assumed that there are 6 steps (8 bits), 0 to 127
A pulse having a time width corresponding to the signal value whose rising period is synchronized with the beginning of one horizontal scanning period is applied to the column wiring of signal values up to and a falling edge is applied to the column wiring of signal values 128 to 255. A pulse having a time width corresponding to the signal value whose period is synchronized with the end of one horizontal scanning period is applied.

A schematic diagram for explaining the image display device of the present embodiment is substantially the same as that of FIG. 24 (sixth embodiment), so that the illustration is omitted. The difference from the sixth embodiment is the configuration of the pulse width modulation circuit 226.

FIG. 28 is a block diagram illustrating the configuration of a pulse width modulation circuit 226 according to the seventh embodiment. The pulse width modulation circuit 226 mainly includes a counter and a latch, counts in accordance with the timing supplied from the timing control circuit 223, and has a time width corresponding to the digital video signal supplied from the one-line memory 225. Convert to a pulse width modulated signal. More specifically, as shown in FIG. 28, an up-down counter 242 is arranged corresponding to each column. Each of the up / down counters 242 receives the Lo sent from the timing control circuit.
It switches to either an up-counter or a down-counter according to the value of the ad signal, so that the CLK signal is counted up or down.

If the digital image signal sent from the one-line memory 225 is in the range of 0 to 127 (8 bits), the up / down counter 242 operates as an up counter, and
If it is in the range of 8 to 255, the up / down counter 242 operates as a down counter. For example, 1
When the value of the digital image signal loaded from the line memory 225 is “100”, the up / down counter 242 counts down according to the CLK signal.

FIG. 29 is a timing chart for explaining the operation of the pulse width modulation circuit 226 according to the seventh embodiment. With the configuration of the pulse width modulation circuit 226 described above, 1
The rise of a rectangular signal having a pulse width less than half of the horizontal period is synchronized with the start of the horizontal period. Further, the falling of the rectangular signal having a pulse width of half or more of one horizontal period is synchronized with the end of the horizontal period.

With the above-described configuration, the digital image signal supplied from the one-line memory has a signal value of 0 to 127 in the column direction wiring, and its rising period is synchronized with the beginning of one horizontal scanning period. A pulse having a time width corresponding to the signal value, and a pulse having a time width corresponding to the signal value whose falling period is synchronized with the end of one horizontal scanning period is applied to the column direction wiring of signal values from 128 to 255. Apply. FIG. 30 shows a time chart of the voltage applied to each wiring of the display panel by the driving device of the seventh embodiment.

When the display panel is driven by dispersing the rising position of the modulation signal in this manner, the luminance at the center of the display panel increases as compared with the conventional case, and the luminance of the entire display panel increases. Distribution improved. Specifically, there was a clear distribution even when viewed with human eyes, but when the moving image was displayed on the image display device of the present embodiment, it could hardly be confirmed with the naked eye.

As described above, according to the present embodiment, by controlling the rising position and the falling position of the modulation signal as described above, the influence of the wiring resistance can be reduced and the uniformity of the luminance can be improved.

[Eighth Embodiment] The sixth and seventh embodiments described above.
In the pulse signal dispersion method described in the embodiment, the effect of dispersing the modulation signal tends to decrease particularly when the time width of the modulation signal is long or when the luminance signal is high. The present inventors have confirmed that this is because the longer the time width of the modulation signal is, the more columns are turned on at the same time, and the effect of dispersing the element current is reduced.

By the way, when the light emission luminance of the entire display panel is high, the relative relationship of the luminance in the display panel is left.
There is a phenomenon that even if the luminance is reduced as a whole, the reduction in the luminance is hardly recognized by human eyes. Therefore, the eighth
In the embodiment, in the image display device described in the sixth embodiment, a circuit for suppressing the luminance of the entire display screen when the luminance of the display screen is high on average is provided inside the decoder 221 described above. Further, the uniformity of luminance is improved.

That is, in the eighth embodiment, when the light emission luminance of the display panel is high as a whole, the time width of the modulation signal applied to each column direction wiring is suppressed, and the luminance of the entire display panel is suppressed. Is added to the drive circuit of the above-described sixth embodiment. The effect of this circuit is to reduce the period in which the modulation signal pulses applied to the respective column direction wirings overlap with each other in time, while the reduction in luminance is not recognized by the human eye. As a result, there is an effect of dispersing the element current, thereby reducing a voltage drop on the row direction wiring due to the resistance of the wiring, and achieving an effect of realizing uniform brightness on the entire display panel. Further, since the emission luminance is suppressed, power consumption can be reduced.

The outline of the drive circuit of the eighth embodiment is shown in FIG.
Is almost the same as the drive circuit of the sixth embodiment shown in FIG. The feature of the eighth embodiment, that is, the difference from the sixth embodiment is the decoder 221. FIG. 31 is a block diagram illustrating a configuration of a decoder 221 according to the eighth embodiment.

Video signals such as NTSC signals are supplied to the decoder 2.
21. The decoder 221 includes, as shown in FIG.
1, A / D converter 252, digital process unit 2
53, a video detector 262, and a controller 263. Here, the analog pre-processing unit 261
Has a function of suppressing the brightness value in accordance with the brightness suppression signal input from the controller 263, in addition to the function of the analog preprocessing unit 251 described in the sixth embodiment.

The decoder section 221 is composed of a video intermediate frequency circuit and a video detection circuit as described above.
An input video signal such as an NTSC signal is converted to an analog signal R,
Decode into G and B signals. Analog preprocessing unit 2
Reference numeral 61 denotes a sync separation circuit, a color adjustment circuit, a contrast control circuit, a DC reproduction circuit, a brightness control circuit, a low-pass filter and a matrix circuit, and the like. The signal level control, DC reproduction, and band-limited R, G, B signals are performed. Output to the A / D converter 252 of each color. Also, a synchronization signal (sync) for the PLL is transmitted to the timing control unit 223.
And a luminance signal obtained by mixing the R, G, and B signals in a matrix circuit to the video detector 262. A
The / D converter 252 digitizes the re-analog R, G, and B signals with a necessary number of gradations according to the sampling clock from the timing control circuit 223. The digital processing unit 253 receiving the digital image signal from the A / D converter 252 performs gamma processing, contour enhancement, and digital filter processing for noise suppression, and outputs a digital image signal to the data array conversion circuit 222.

The video detecting section 262 integrates the luminance signal from the analog pre-processing section every one horizontal scanning period.
The average value of the luminance signal detected every one horizontal scanning period is transmitted to the controller 263. In the controller 263,
When the average luminance signal is larger than a certain reference value, a luminance suppression signal is output to the analog pre-processing unit 261 to perform contrast control. In the eighth embodiment, the controller 263 converts analog R, G,
A luminance suppression signal is output so as to suppress the B signal at a magnification as shown in FIG.

As a result, the pulse width of the modulation signal output to each column direction wiring is suppressed, and the light emission luminance of the display panel is controlled to a certain reference value or less.

When the display panel is arranged in the R, G, B vertical stripe arrangement, the mixed luminance signals calculated by the matrix circuit are mixed at the same ratio of the R, G, B signals (eg, S0). = 1/3 (R + G + B)), and when the numbers of R, G, and B phosphors are different, such as in a checkered arrangement, a mixed luminance signal is generated at that ratio.

Further, in the above embodiment, the contrast control of the analog pre-processing section 261 is used to suppress the luminance, but the present invention is not limited to this. For example, the luminance may be controlled by suppressing the digital data R, G, and B in the digital processing unit 253.

In order to further obtain a luminance evaluation value, a high-voltage power supply V
a may be provided with a circuit for detecting the average high-voltage anode current or a circuit for detecting the average supply current of the line for supplying power to the high-voltage power supply Va, and the detection signal may be sent to the controller 263.

By limiting the luminance signal as described above and consequently limiting the time width of the modulation signal, there is an effect that the modulation signal applied to each column direction wiring is more dispersed.
As a result, the element current flowing from each column direction wiring to the selected row direction wiring via the cold cathode element of the selected row can be dispersed, and the voltage drop on the wiring resistance can be further reduced. . As a result, it is possible to further improve the uniformity of the luminance of the display panel caused by the wiring resistance.

When the display panel is driven by dispersing the rising position of the modulation signal in this manner, the luminance at the center of the display panel increases as compared with the conventional case, and the luminance of the entire display panel increases. Distribution improved. Specifically, there was a clear distribution even when viewed with human eyes, but when the moving image was displayed on the image display device of the present embodiment, it could not be confirmed with the naked eye at all.

As described above, according to the sixth to eighth embodiments,
By controlling the rise position and the fall position of the modulation signal, the influence of the wiring resistance was reduced, and the uniformity of luminance was able to be increased.

[Ninth Embodiment] FIG. 33 is a block diagram showing the structure of an image display device according to the ninth embodiment.
In the figure, the same components as those of the first embodiment (FIG. 1) are denoted by the same reference numerals. In FIG. 33, reference numeral 1 denotes an image display panel in which horizontal 480 and vertical 240 phosphors are arranged in the form of R, G, and B vertical stripes, and the electron-emitting devices corresponding to each phosphor are arranged in a row direction. It is assumed that wiring is performed in a simple matrix by electrodes and column wiring electrodes, and an example will be described in which this panel is driven line-sequentially.

The input TV signal s1 is decoded by the decoder unit 2 into analog R, G, B signals and is input to the analog preprocessing unit 3. Analog preprocessing unit 3
Consists of a sync separation circuit, a color adjustment circuit, a contrast control circuit, a DC reproduction circuit, a brightness control circuit, a matrix circuit, a low-pass filter, etc., and performs signal level control, DC reproduction, and band-limited R, G, B signals for each color. To the A / D converter 4. In addition to sending a synchronization signal (sync) for the PLL to the timing control unit 5, it also sends to the video detection unit 3 a luminance signal obtained by mixing the R, G, and B signals in the matrix unit.

The A / D converter 4 digitizes analog R, G, and B signals in a required number of gradations according to a sampling clock from the timing control unit 305. A /
Upon receiving the digital image signal s9 from the D converter 4, the digital processing unit 6 performs gamma processing, digital filter processing for edge enhancement and noise suppression, and outputs a digital image signal to the data rearranging unit 7. In addition, control of logical emphasis and contrast control are also performed by the coefficient data s15 from the system control unit 14.

The data rearranging section 7 compresses the 160 data (s9) for each one horizontal period R, G, B in the time axis as s10 as shown in the outline of the horizontal timing in FIG. The data is rearranged in the order corresponding to the color arrangement and transferred to the shift register 8 as 480 serial image data per line.

The shift register 8 reads the serial image data s10 by the shift clock s7, converts 480 serial image data per line into parallel data, and sends the parallel data to the modulation signal generator 309 during the horizontal blanking period.

In the ninth embodiment, the modulation signal generator 309 uses the voltage modulation method, and is composed of 480 voltage modulators corresponding to one row of electron-emitting devices. Then, a pulse signal having a voltage amplitude corresponding to the size of the image data read into each voltage modulator is generated by the modulation signal s7 during one horizontal period, and is sent to the horizontal drive driver 10.

The horizontal drive driver 310 controls the pulse width of the pulse signal (pulse signal output to the image display panel 1) to be applied to the electron-emitting device by the signal s317 from the pulse width control unit 315.

As shown in the vertical timing diagram of FIG.
The shift register 11 receiving the row scanning timing signal s8 (V_START, H_CLK) from the timing control unit 5 sends a row selection signal for scanning to the vertical drive driver 12.

The vertical drive driver 12 is composed of switch elements such as transistors for 240 rows, becomes conductive at the time of selection, and supplies a bias V supplied from the Vs voltage generation section 318.
s is applied to the image display panel 1. As described above, the vertical drive driver 12 sequentially scans and selects the image modulation data output from the horizontal drive driver 310 for each horizontal line, whereby an image signal is displayed on the image display panel 1.

The configuration of the system control unit 14 is as described above with reference to FIG.
AM23, EEPROM24, A / D converter 2
5, a D / A converter 26 and an I / O port 27. The apparatus is controlled by a program stored in the ROM 22. Output signals s13 and s14 of the D / A converter 26 are contrast control and brightness control signals, which are transmitted to the analog pre-processing unit 3 and control the levels of the R, G and B signals and the amount of DC reproduction. s16 is a control signal of the pulse width of the element applied pulse at the time of selection and is transmitted to the pulse width control unit 15. s18
Is transmitted to the high voltage generator 17 which outputs a high voltage Va (s19) for accelerating the electron beam, and is transmitted to the high voltage Va (s1).
9) is controlled.

The user interface unit 16 transmits a user request such as image quality adjustment to the system control unit 14 and displays various information from the system control unit 14 by a signal s12.

The video detection unit 13 integrates the luminance signal s20 from the analog pre-processing unit 3 with the gate signal s5 (see FIG. 2) for each field to which horizontal blanking is added from the timing control unit 5, and The signal s11 obtained by detecting the average value of the signal for each field is transmitted to the system control unit 14.

The detected average luminance signal s11 is represented by A / D in FIG.
The signal is taken into the CPU 21 by the converter 25 and is compared with a reference value held in the system control unit 14. When the detected average luminance signal s11 is larger than the reference value, D / D
The contrast is controlled by the output signal s13 of the A converter 26, and as a result, the output pulse width from the horizontal drive driver 310 is suppressed, so that the light emission luminance of the panel 1 is controlled to a certain reference value or less. As the reference value, an average luminance value for several fields or several screens calculated by the system control unit 14 is used.

FIG. 34 is a diagram for explaining luminance suppression according to the ninth embodiment. (A) of FIG.
9 shows a modulation signal (voltage modulation) from 09. When the luminance value of this signal is higher than the above-described reference value, the pulse width is limited by the pulse width control unit 315 according to the instruction (s316) from the system control unit 14. As a result, a drive signal as shown in FIG. 34B is output from the horizontal driver 310. That is, the time width of each drive pulse is shortened by h, and as a result, the luminance value is suppressed. Needless to say, the time width of h is controlled according to the magnitude of the luminance value. h is, for example, in the present embodiment, the maximum luminance value obtained when the maximum voltage pulse is applied is Bm, and the detected average luminance s11 is the luminance evaluation value B: h = ｛1−Bm / (3 × B) ｝ H (when B> Bm / 3) h = 0 (when B ≦ Bm / 3) Further, in FIG. 34B, the falling of the pulse is advanced, but it is apparent that the rising timing of the pulse may be delayed.

In the above, an example has been described in which the emission luminance is controlled by the luminance evaluation value using the luminance signal s20 from the analog preprocessing unit 3 in the case of the R, G, B vertical stripe arrangement. In the case of the above embodiment, the luminance signal s20 is R, G, B
Although the signals are mixed at the same ratio, (eg, s20 =
When the numbers of R, G, and B phosphors are different, such as in a 1/3 (R + G + B) checkerboard arrangement, the luminance signal s2 is calculated at that ratio.
Generate 0.

Further, a circuit for detecting an average high-voltage anode current or a circuit for detecting an average supply current of a line for supplying power to the high-voltage generation unit 17 is provided in the high-voltage generation unit 17 to obtain a luminance evaluation value. Control unit 1
4 may be sent.

Although the TV signal is described as an input signal, the present invention is not limited to this, and NTSC, PAL, S
ECAM and MUSE of HDTV can be realized by the same concept. Further, the same applies to, for example, a computer signal other than the TV signal.

[Tenth Embodiment] In the ninth embodiment, the luminance is suppressed by either delaying the rise of the pulse or accelerating the fall of the pulse. In the tenth embodiment, by mixing a column-direction wiring that delays the rise of a pulse and a column-direction wiring that delays the fall of a pulse, pulse dispersion is achieved, and luminance unevenness is reduced more effectively. FIG. 35 is a timing chart for explaining the timing of the drive signal according to the tenth embodiment. In the output pulse signal from the horizontal drive driver 310 in the ninth embodiment, the detected average luminance signal s11 is compared with a reference value inside the system control unit 14, and when the detected average luminance signal s11 is larger than the reference value. , Odd columns (2n-1; n = 1 to 24)
In the output pulse signal 0), the time of the falling portion of the basic pulse is controlled (advanced), and the even-numbered row (2n; n = 1 to 2)
The output pulse signal of 40) controls the average luminance of the entire light emitting screen so as not to exceed a certain value by controlling (delaying) the rise time of the basic pulse.

As shown in FIG. 4, the detected average luminance signal s
11 is taken into the CPU 21 by the A / D converter 25 and compared with a reference value stored in the system control unit 14. When the detected average luminance signal s11 is larger than the reference value, the odd-numbered (2n-1; n = 1 to 24) signal is output by the output signal s13 of the D / A converter 26.
Contrast control so that the output pulse signal of 0) controls the time of the falling portion of the basic pulse, and the even-numbered (2n; n = 1 to 240) output pulse signal controls the time of the rising portion of the basic pulse. I do. As a result, the output pulse width from the horizontal drive driver 310 is suppressed as shown in FIG. 5, and the light emission luminance of the image display panel 1 is controlled to be below a certain reference value.

As in the ninth embodiment, an average luminance value for several fields or several screens calculated by the system control unit 14 is used as the reference value.

In the above, the example of controlling the contrast of the analog pre-processing unit 3 to suppress the luminance by the output pulse width has been described. The contrast control by the coefficient data s15 in the digital processing unit 6 and the pulse width control unit by s16 are described. Fifteen controls may be used.

As described above, according to the tenth embodiment,
By shifting the pulses of the odd-numbered (2n-1; n = 1 to 240) output pulse signals and the even-numbered (2n; n = 1 to 240) output pulse signals, the voltage is applied to all the elements on one field. By reducing the time, the effect of the voltage drop due to the wiring resistance can be reduced.

The preferred embodiments of the present invention have been described with reference to the first to tenth embodiments. Hereinafter, an image display panel suitable for applying the electron source drive according to the above embodiment will be described in detail.

(Structure and Manufacturing Method of Display Panel) First, the structure and manufacturing method of a display panel of an image display device to which the present invention is applied will be described with reference to specific examples.

FIG. 36 is a perspective view of a display panel used in the embodiment, in which a part of the panel is cut away to show the internal structure.

In the figure, 1005 is a rear plate, 1006
Is a side wall, 1007 is a face plate, 1005
1007 form an airtight container for maintaining the inside of the display panel at a vacuum. When assembling an airtight container, it is necessary to seal the joints of each member to maintain sufficient strength and airtightness.For example, apply frit glass to the joints, and in air or nitrogen atmosphere, Sealing was achieved by baking at 400 to 500 degrees for 10 minutes or more. A method of evacuating the inside of the airtight container to a vacuum will be described later.

The rear plate 1005 has a substrate 1001
Is fixed, but the cold cathode device 1002 is provided on the substrate.
N × M are formed. (N and M are positive integers of 2 or more and are appropriately set according to the target number of display pixels. For example, in a display device for displaying high-definition television, N = 3000, M It is desirable to set a number equal to or greater than 1000. In the present embodiment, N = 3072 and M = 1024.)
The cold cathode elements are arranged in a simple matrix by M row-directional wirings 1003 and N column-directional wirings 1004. The portion constituted by 1001 to 1004 is called a multi-electron beam source. The manufacturing method and structure of the multi-electron beam source will be described later in detail.

In this embodiment, the substrate 1001 of the multi-electron beam source is fixed to the rear plate 1005 of the airtight container.
01 has sufficient strength, the substrate 10 of the multi-electron beam source is used as a rear plate of the hermetic container.
01 itself may be used.

A fluorescent film 1008 is formed on the lower surface of the face plate 1007. Since the present embodiment is a color display device, the fluorescent film 1008 has C
Phosphors of three primary colors of red, green and blue used in the field of RT are separately applied. The phosphor of each color is, for example, as shown in FIG.
As shown in (A) of FIG.
A black conductor 1010 is provided between the phosphor stripes. The purpose of providing the black conductor 1010 is to prevent the display color from shifting even if the electron beam irradiation position is slightly shifted, and to prevent the reflection of external light to prevent the display contrast from lowering. And preventing charge-up of the fluorescent film by the electron beam. Although graphite is used as a main component for the black conductor 1010, any other material may be used as long as it is suitable for the above purpose.

The method of applying the three primary color phosphors is not limited to the stripe arrangement shown in FIG. 37A, but may be, for example, a delta arrangement as shown in FIG. Other arrangements may be used.

When a monochrome display panel is manufactured, a monochromatic phosphor material may be used for the phosphor film 1008, and a black conductive material is not necessarily used.

A metal back 1009 known in the CRT field is provided on the surface of the fluorescent film 1008 on the rear plate side.
Is provided. The purpose of providing the metal back 1009 is
A part of the light emitted from the fluorescent film 1008 is specularly reflected to improve the light utilization rate, or the fluorescent film 1008
8 to protect it, to act as an electrode for applying an electron beam acceleration voltage, and to act as a conductive path for excited electrons of the fluorescent film 1008. The metal back 1009 was formed by forming a fluorescent film 1008 on the face plate substrate 1007, smoothing the surface of the fluorescent film, and vacuum-depositing Al thereon.
Note that when a fluorescent material for low voltage is used for the fluorescent film 1008, the metal back 1009 is not used.

Although not used in this embodiment, for the purpose of applying an acceleration voltage and improving the conductivity of the fluorescent film, a transparent material made of, for example, ITO is used between the face plate substrate 1007 and the fluorescent film 1008. Electrodes may be provided.

Dx1 to Dxm, Dy1 to Dyn, and Hv are electric connection terminals having an airtight structure provided for electrically connecting the display panel to an electric circuit (not shown). Dx1 to Dxm are the row wirings 10 of the multi-electron beam source.
03, Dy1 to Dyn are the column direction wirings 1004 of the multi-electron beam source, and Hv is the metal back 1 of the face plate.
009 electrically.

In order to evacuate the inside of the hermetic container, after the hermetic container is assembled, an exhaust pipe (not shown) and a vacuum pump are connected, and the inside of the hermetic container is raised to the power of 10 −7 [T
orr]. Thereafter, the exhaust pipe is sealed, but a getter film (not shown) is formed at a predetermined position in the airtight container immediately before or after the sealing in order to maintain the degree of vacuum in the airtight container. The getter film is, for example, a film formed by heating and depositing a getter material containing Ba as a main component by a heater or high-frequency heating,
Due to the adsorbing action of the getter film, the inside of the airtight container is 1 × 10 −5 or 1 × 10 −7 [Torr].
Is maintained at a vacuum degree.

The basic configuration and manufacturing method of the display panel according to the embodiment of the present invention have been described above.

Next, a method of manufacturing the multi-electron beam source used for the display panel of the above embodiment will be described. The material, shape, and manufacturing method of the cold cathode device are not limited as long as the multi-electron beam source used for the image display device of the present invention is an electron source in which cold cathode devices are arranged in a simple matrix. Therefore, for example, a cold cathode device such as a surface conduction type emission device, an FE type, or an MIM type can be used.

However, in a situation where a display device having a large display screen and an inexpensive display device is required, among these cold cathode devices, a surface conduction type emission device is particularly preferable. That is, in the FE type, since the relative position and shape of the emitter cone and the gate electrode greatly affect the electron emission characteristics, extremely high-precision manufacturing technology is required, but this achieves a large area and a reduction in manufacturing cost. Is a disadvantageous factor. In the case of the MIM type, it is necessary to make the thicknesses of the insulating layer and the upper electrode thin and uniform, which is also a disadvantageous factor in achieving a large area and a reduction in manufacturing cost. On the other hand, since the surface conduction electron-emitting device has a relatively simple manufacturing method, it is easy to increase the area and reduce the manufacturing cost. In addition, the inventors have found that among the surface conduction electron-emitting devices, those in which the electron-emitting portion or its peripheral portion is formed of a fine particle film have particularly excellent electron-emitting characteristics and can be easily manufactured. Therefore, it can be said that it is most suitable for use in a multi-electron beam source of a high-luminance, large-screen image display device. Therefore, in the display panel of the above embodiment, a surface conduction electron-emitting device in which the electron-emitting portion or its peripheral portion is formed of a fine particle film is used.

The basic structure, manufacturing method and characteristics of a suitable surface conduction electron-emitting device will be described first, and then the structure of a multi-electron beam source in which many devices are arranged in a simple matrix will be described.

(Preferable Device Configuration and Manufacturing Method of Surface Conduction Emission Device) A typical configuration of a surface conduction electron-emitting device in which an electron-emitting portion or its peripheral portion is formed from a fine particle film is a flat type or a vertical type. Kinds are given.

(Planar surface conduction electron-emitting device) First, the structure and manufacturing method of a plane surface conduction electron-emitting device will be described. FIG. 38 is a plan view (a) and a cross-sectional view (b) for describing the configuration of the planar surface conduction electron-emitting device. In the figure, 1101 is a substrate, 1102 and 1103 are device electrodes, 1104 is a conductive thin film, 1105
Are electron-emitting portions formed by an energization forming process;
Reference numeral 113 denotes a thin film formed by the activation process.

As the substrate 1101, for example, various glass substrates such as quartz glass and blue plate glass, various ceramics substrates such as alumina, or an insulating layer made of, for example, SiO 2 is laminated on the various substrates described above. Substrate or the like can be used.

The element electrodes 1102 and 1103 provided on the substrate 1101 so as to be parallel to the substrate surface are formed of a conductive material. For example, N
i, Cr, Au, Mo, W, Pt, Ti, Cu, Pd,
The material may be appropriately selected from metals such as Ag and the like, alloys of these metals, metal oxides such as In 2 O 3 —SnO 2, and semiconductors such as polysilicon. An electrode can be easily formed by using a combination of a film forming technique such as vacuum evaporation and a patterning technique such as photolithography and etching. However, the electrode can be formed by other methods (for example, printing technique). I can't wait.

The shapes of the device electrodes 1102 and 1103 are appropriately designed according to the application purpose of the electron-emitting device.
Generally, the electrode spacing L is usually designed by selecting an appropriate value from the range of several hundreds of angstroms to several hundreds of micrometers. It is in the range of ten micrometers. Further, regarding the thickness d of the device electrode,
Usually, an appropriate numerical value is selected from the range of several hundred angstroms to several micrometers.

A fine particle film is used for the conductive thin film 1104. The fine particle film mentioned here is a film containing many fine particles as a constituent element (including an island-shaped aggregate).
I mean If you examine the microparticle film microscopically, usually
A structure in which the individual fine particles are spaced apart, a structure in which the fine particles are adjacent to each other, or a structure in which the fine particles overlap each other is observed.

The particle size of the fine particles used in the fine particle film is in the range of several Angstroms to several thousand Angstroms, but is preferably in the range of 10 Angstroms to 200 Angstroms. Further, the thickness of the fine particle film is appropriately set in consideration of various conditions described below. That is, the device electrode 11
02, or 1103, conditions necessary for satisfactorily performing energization forming described later, conditions necessary for setting the electric resistance of the fine particle film itself to an appropriate value described later. , And so on.

More specifically, the distance is set within a range of several Angstroms to several thousand Angstroms, and a preferable range is between 10 Angstroms and 500 Angstroms.

Materials that can be used to form the fine particle film include, for example, Pd, Pt, Ru, Ag,
Au, Ti, In, Cu, Cr, Fe, Zn, Sn, T
a, W, Pb, and other metals, PdO, S
Oxides such as nO2, In2 O3, PbO, Sb2 O3, etc .; HfB2, ZrB2, LaB6, C
Borides such as eB6, YB4, GdB4, etc., TiC, ZrC, HfC, TaC, SiC, WC,
And other carbides, TiN, ZrN, Hf
Nitrides such as N, etc., semiconductors such as Si, Ge, etc., carbon, and the like are listed, and are appropriately selected from these.

As described above, the conductive thin film 1104 is formed of a fine particle film.
It was set to be included in the range of 10 3 to 10 7 [Ohm / sq].

The conductive thin film 1104 and the device electrode 11
Since it is desirable that the wires 02 and 1103 be electrically connected well, they have a structure in which a part of each overlaps with the other. In the example of FIG. 38,
Although the substrate, the device electrode, and the conductive thin film are stacked in this order from the bottom, in some cases, the substrate, the conductive thin film, and the device electrode may be stacked in this order from the bottom.

The electron-emitting portion 1105 is a crack-like portion formed in a part of the conductive thin film 1104, and has a higher electrical property than the surrounding conductive thin film. The crack is formed by performing a later-described energization forming process on the conductive thin film 1104. Fine particles having a particle size of several Angstroms to several hundred Angstroms may be arranged in the crack. Since it is difficult to accurately and accurately show the actual position and shape of the electron-emitting portion, it is schematically shown in FIG.

The thin film 1113 is a thin film made of carbon or a carbon compound, and covers the electron emitting portion 1105 and its vicinity. The thin film 1113 is formed by performing an energization activation process described later after the energization forming process.

The thin film 1113 is made of any one of single crystal graphite, polycrystal graphite, and amorphous carbon, or a mixture thereof, and has a thickness of 500 [Å] or less, but 300 [Å] or less. Is more preferred.

Since it is difficult to accurately show the actual position and shape of the thin film 1113, it is schematically shown in FIG. Also, in the plan view (a), the thin film 11
13 shows a device in which a part of the device 13 is removed.

The basic structure of the preferred element has been described above. In the embodiment, the following element is used.

That is, blue glass was used for the substrate 1101, and Ni thin films were used for the device electrodes 1102 and 1103. The thickness d of the device electrode was 1000 [angstrom], and the electrode interval L was 2 [micrometer].

Pd or P as the main material of the fine particle film
Using dO, the thickness of the fine particle film was set to about 100 [angstrom], and the width W was set to 100 [micrometer].

Next, a description will be given of a preferred method of manufacturing a planar type surface conduction electron-emitting device. (A) to (d) of FIG.
Is a cross-sectional view for explaining a manufacturing process of the surface conduction electron-emitting device, and the notation of each member is the same as that in FIG.

1) First, as shown in FIG. 39A, device electrodes 1102 and 1103 are formed on a substrate 1101.

Before forming, the substrate 1
After sufficiently washing 101 with a detergent, pure water and an organic solvent,
The material of the device electrode is deposited. (As a deposition method, for example, a vacuum film forming technique such as a vapor deposition method or a sputtering method may be used.) Thereafter, the deposited electrode material is patterned by using a photolithography / etching technique, and as shown in FIG. The illustrated pair of device electrodes (1102 and 110)
Form 3).

2) Next, a conductive thin film 1104 is formed as shown in FIG.

In the formation, first, an organic metal solution is applied to the substrate (a), dried, heated and baked to form a fine particle film, and then patterned into a predetermined shape by photolithography and etching. . here,
The organic metal solution is a solution of an organic metal compound containing a material of fine particles used for the conductive thin film as a main element. (Specifically, in the present embodiment, Pd is used as a main element. In the embodiment, a dipping method is used as a coating method, but other methods such as a spinner method and a spray method may be used).

As a method of forming a conductive thin film made of a fine particle film, other than the method of applying an organic metal solution used in the present embodiment, for example, a vacuum evaporation method, a sputtering method, or a chemical vapor deposition method Method may be used.

3) Next, as shown in FIG. 14C, a forming power supply 1110 switches the device electrodes 1102 and 1102 from each other.
3, an appropriate voltage is applied, and an energization forming process is performed to form the electron-emitting portion 1105.

[0223] The energization forming treatment is to energize the conductive thin film 1104 made of a fine particle film, to appropriately break, deform, or alter a part of the conductive thin film 1104 to change the structure to a structure suitable for emitting electrons. This is the process that causes A portion of the conductive thin film made of a fine particle film that has been changed to a structure suitable for emitting electrons (that is, the electron emitting portion 110
In 5), an appropriate crack is formed in the thin film.
Note that the electrical resistance measured between the device electrodes 1102 and 1103 is significantly increased after the formation of the electron emission portions 1105 as compared to before the formation.

FIG. 40 shows an example of an appropriate voltage waveform applied from the forming power supply 1110 in order to explain the energization method in more detail. When forming a conductive thin film made of a fine particle film, a pulse-like voltage is preferable. In the case of this embodiment, a triangular wave pulse having a pulse width T1 is continuously generated at a pulse interval T2 as shown in FIG. Was applied. At that time, the peak value Vpf of the triangular wave pulse was sequentially increased. In addition, monitor pulses Pm for monitoring the state of formation of the electron-emitting portion 1105 were inserted at appropriate intervals between the triangular-wave pulses, and the current flowing at that time was measured by the ammeter 1111.

In the embodiment, for example, in a vacuum atmosphere of about 10 −5 [torr], for example, the pulse width T1 is 1 [millisecond], the pulse interval T2 is 10 [millisecond], and the peak value Vpf is The voltage was increased by 0.1 [V] for each pulse. Then, the monitor pulse Pm was inserted at a rate of one every time five triangular waves were applied. The monitor pulse voltage Vpm was set to 0.1 [V] so as not to adversely affect the forming process. Then, when the electric resistance between the element electrodes 1102 and 1103 becomes 1 × 10 6 [ohm], that is, the current measured by the ammeter 1111 when the monitor pulse is applied becomes 1 × 10 −7 [A] or less. At this stage, the energization related to the forming process was terminated.

The above method is a preferable method for the surface conduction electron-emitting device of the present embodiment. For example, the design of the surface conduction electron-emitting device such as the material and film thickness of the fine particle film or the element electrode interval L is changed. In such a case, it is desirable to appropriately change the energization conditions accordingly.

4) Next, as shown in FIG.
The device electrodes 1102 and 1103 are supplied from the activation power source 1112.
During the energization activation process, apply an appropriate voltage during
Improve electron emission characteristics.

The energization activation process is a process of energizing the electron emitting portion 1105 formed by the energization forming process under appropriate conditions and depositing carbon or a carbon compound in the vicinity thereof. (In the figure, a deposit made of carbon or a carbon compound is schematically shown as a member 1113.) By performing the activation process, the emission current at the same applied voltage is typically smaller than that before the activation. Specifically, it can be increased by 100 times or more.

Specifically, 10 minus the fourth power to 1
By applying a voltage pulse periodically in a vacuum atmosphere within the range of 0 to the fifth power [torr], carbon or a carbon compound originating from an organic compound existing in the vacuum atmosphere is deposited. The deposit 1113 is any of single crystal graphite, polycrystalline graphite, and amorphous carbon, or a mixture thereof, and has a thickness of 500.
[Angstrom] or less, more preferably 300 [angstrom] or less.

In order to explain the energization method in more detail, FIG. 41A shows an example of an appropriate voltage waveform applied from the activation power supply 1112. In the present embodiment, the energization activation process is performed by periodically applying a rectangular wave having a constant voltage, but specifically, the rectangular wave voltage Vac is 14
[V], pulse width T3 is 1 [millisecond], pulse interval T4
Was set to 10 [milliseconds]. The above-described energization conditions are preferable conditions for the surface conduction electron-emitting device of the present embodiment, and when the design of the surface conduction electron-emitting device is changed,
It is desirable to change the conditions accordingly.

An anode electrode 1114 shown in FIG. 38D for capturing the emission current Ie emitted from the surface conduction electron-emitting device is connected to a DC high voltage power supply 1115 and an ammeter 1116. (Note that the substrate 1101
When the activation process is performed after the display panel is incorporated into the display panel, the phosphor screen of the display panel is connected to the anode electrode 1114.
Used as While the voltage is applied from the activation power supply 1112, the emission current Ie is measured by the ammeter 1116 to monitor the progress of the energization activation process.
12 is controlled. An example of the emission current Ie measured by the ammeter 1116 is shown in FIG. 41B. When the pulse voltage is started to be applied from the activation power supply 1112, the emission current Ie increases with the passage of time, but eventually saturates. And hardly increase. As described above, when the emission current Ie is substantially saturated, the application of the voltage from the activation power supply 1112 is stopped, and the energization activation process ends.

The above-mentioned energization conditions are preferable conditions for the surface conduction electron-emitting device of the present embodiment, and when the design of the surface conduction electron-emitting device is changed, the conditions should be changed accordingly. desirable.

As described above, the plane type surface conduction electron-emitting device shown in FIG. 39E was manufactured.

(Vertical Surface Conduction Emission Device) Next, another typical structure of a surface conduction electron-emitting device in which the electron-emitting portion or its periphery is formed of a fine particle film, that is, a vertical surface-conduction emission device. The configuration of the element will be described.

FIG. 42 is a schematic cross-sectional view for explaining the basic structure of the vertical type. In FIG.
202 and 1203 are device electrodes, 1206 is a step forming member, 1204 is a conductive thin film using a fine particle film, 1205
Are electron-emitting portions formed by an energization forming process;
213 is a thin film formed by the activation process.

The difference between the vertical type and the flat type described above is that one of the device electrodes (1202) is provided on the step forming member 1206, and the conductive thin film 1204 is provided on the side surface of the step forming member 1206. It is in the point of coating. Therefore, the element electrode interval L in the planar type shown in FIG.
Is the step height L of the step forming member 1206 in the vertical type.
s. In addition, the substrate 1201, the element electrode 1
202 and 1203, conductive thin film 1 using fine particle film
204, the materials listed in the description of the planar type can be used in the same manner. For the step forming member 1206, an electrically insulating material such as SiO2 is used.

Next, a method of manufacturing a vertical surface conduction electron-emitting device will be described. FIGS. 43A to 43F are cross-sectional views for explaining the manufacturing process.
Same as 2.

1) First, as shown in FIG. 43A, an element electrode 1203 is formed on a substrate 1201.

2) Next, as shown in FIG. 23B, an insulating layer for forming a step forming member is laminated. The insulating layer may be formed by laminating SiO2 by sputtering, for example, but other film forming methods such as vacuum deposition or printing may be used.

3) Next, as shown in FIG. 23C, an element electrode 1202 is formed on the insulating layer.

4) Next, as shown in FIG. 14D, a part of the insulating layer is removed by, for example, an etching method to expose the element electrode 1203.

5) Next, as shown in FIG. 17E, a conductive thin film 1204 using a fine particle film is formed. For the formation, as in the case of the flat type, a film forming technique such as a coating method may be used.

6) Next, in the same manner as in the case of the planar type, the energization forming process is performed to form an electron emission portion (the same process as the planar type energization forming process described with reference to FIG. 39C). Just do it.)

7) Next, as in the case of the flat type, a current activation process is performed to deposit carbon or a carbon compound near the electron emitting portion. (The same process as the planar energization activation process described with reference to FIG. 39D may be performed.)

As described above, the vertical surface conduction electron-emitting device shown in FIG. 43 (f) was manufactured.

(Characteristics of Surface Conduction Emission Device Used in Display Device) The element configuration and manufacturing method of the planar and vertical surface conduction electron-emitting devices have been described above. Next, the characteristics of the device used in the display device will be described. Is described.

FIG. 44 shows typical examples of (emission current Ie) versus (device applied voltage Vf) characteristics and (device current If) versus (device applied voltage Vf) characteristics of the device used in the display device. . Note that the emission current Ie is significantly smaller than the element current If, and it is difficult to show the same current on the same scale.
Since these characteristics are changed by changing design parameters such as the size and shape of the element, the two graphs are shown in arbitrary units.

The element used in the display device has the following three characteristics regarding the emission current Ie.

First, a certain voltage (this is referred to as a threshold voltage Vth
When a voltage of the above magnitude is applied to the element, the emission current Ie sharply increases. On the other hand, at a voltage lower than the threshold voltage Vth, the emission current Ie is hardly detected.

That is, the non-linear element has a clear threshold voltage Vth with respect to the emission current Ie.

Second, since the emission current Ie changes depending on the voltage Vf applied to the element, the emission current Ie varies with the voltage Vf.
The magnitude of e can be controlled.

Third, since the response speed of the current Ie emitted from the element is fast with respect to the voltage Vf applied to the element, the amount of charge of the electrons emitted from the element depends on the length of time during which the voltage Vf is applied. Can control.

Because of the above characteristics, the surface conduction electron-emitting device could be suitably used for a display device. For example, in a display device in which a large number of elements are provided corresponding to pixels of a display screen, if the first characteristic is used, display can be performed by sequentially scanning the display screen. That is,
The driving element has a threshold voltage Vt according to a desired light emission luminance.
h or higher, and a voltage lower than the threshold voltage Vth is applied to the non-selected elements. By sequentially switching the elements to be driven, the display screen can be sequentially scanned and displayed.

Further, by utilizing the second characteristic or the third characteristic, the light emission luminance can be controlled, so that gradation display can be performed.

(Structure of a multi-electron beam source in which a large number of elements are arranged in a simple matrix) Next, a structure of a multi-electron beam source in which the above-described surface conduction electron-emitting elements are arranged on a substrate and arranged in a simple matrix will be described.

FIG. 45 is a plan view of the multi-electron beam source used for the display panel of FIG. On the substrate, surface conduction type emission devices similar to those shown in FIG. 38 are arranged.
3 and the column-direction wiring electrodes 1004 are wired in a simple matrix. An insulating layer (not shown) is formed between the row-directional wiring electrodes 1003 and the column-directional wiring electrodes 1004 where they intersect, so that electrical insulation is maintained.

FIG. 46 is a sectional view taken along the line AA ′ of FIG.
Shown in

A multi-electron source having such a structure is as follows.
After previously forming a row direction wiring electrode 1003, a column direction wiring electrode 1004, an interelectrode insulating layer (not shown), and a device electrode and a conductive thin film of a surface conduction electron-emitting device on a substrate,
Row direction wiring electrode 1003 and column direction wiring electrode 1004
The device was manufactured by supplying power to each element through the device and performing an energization forming process and an energization activation process.

(Example of Application to Display Panel) FIG.
Is a multifunctional display configured to be able to display image information provided from various image information sources such as a television broadcast on a display panel using the surface conduction electron-emitting device described above as an electron beam source. It is a figure for showing an example of an apparatus. In the figure, 2100 is a display panel, 2101 is a drive circuit of the display panel,
2102 is a display controller, 2103 is a multiplexer, 2104 is a decoder, 2105 is an input / output interface circuit, 2106 is a CPU, 2107 is an image generation circuit, 2108, 2109 and 2110 are image memory interface circuits, 2111 is an image input interface circuit, 2112 and 2113 is TV
The signal receiving circuit 2114 is an input unit. (Note that when the present display device receives a signal including both video information and audio information, such as a television signal, it naturally outputs audio simultaneously with video display. Reception, separation, reproduction, and playback of audio information that is to be reproduced but not directly related to the features of the present invention
Descriptions of circuits, speakers, and the like relating to processing and storage are omitted. Hereinafter, the function of each unit will be described along the flow of the image signal.

First, the TV signal receiving circuit 2113 is a circuit for receiving a TV image signal transmitted using a wireless transmission system such as radio waves or spatial optical communication.
The type of TV signal to be received is not particularly limited,
For example, various systems such as the NTSC system, the PAL system, and the SECAM system may be used. A TV signal (for example, a so-called high-definition TV such as the MUSE system) composed of a larger number of scanning lines is suitable for taking advantage of the display panel suitable for a large area and a large number of pixels. Signal source. The TV signal received by the TV signal receiving circuit 2113 is output to the decoder 2104.

The TV signal receiving circuit 2112 is a circuit for receiving a TV image signal transmitted using a wired transmission system such as a coaxial cable or an optical fiber. As with the TV signal receiving circuit 2113, the type of the TV signal to be received is not particularly limited, and the TV signal received by this circuit is also output to the decoder 2104.

In addition, the image input interface circuit 21
Reference numeral 11 denotes a circuit for receiving an image signal supplied from an image input device such as a TV camera or an image reading scanner.
Is output to

The image memory interface circuit 2
110 is a video tape recorder (hereinafter abbreviated as VTR)
Is a circuit for capturing the image signal stored in the decoder 2104. The captured image signal is output to the decoder 2104.

The image memory interface circuit 2
Reference numeral 109 denotes a circuit for capturing an image signal stored in the video disk, and the captured image signal is output to the decoder 2104.

The image memory interface circuit 2
Reference numeral 108 denotes a circuit for taking in an image signal from a device that stores still image data, such as a so-called still image disk.
04 is output.

The input / output interface circuit 210
Reference numeral 5 denotes a circuit for connecting the present display device to an external computer, a computer network, or an output device such as a printer. In addition to inputting and outputting image data, character data, and graphic information, control signals and numerical data can be input and output between the CPU 2106 included in the display device and the outside in some cases. .

The image generating circuit 2107 is provided with image data, character / graphic information input from the outside via the input / output interface circuit 2105, or a CPU.
A circuit for generating display image data based on the image data and character / graphic information output from 2106.
The circuit includes a rewritable memory for storing, for example, image data and character / graphic information, a read-only memory for storing image patterns corresponding to character codes, and a processor for performing image processing. Circuits necessary for generating an image, such as those described above, are incorporated.
The display image data generated by this circuit is output to the decoder 2104, but may be input / output to an external computer network or a printer via the input / output interface circuit 2105 in some cases.

The CPU 2106 mainly performs operations related to operation control of the display device and generation, selection and editing of a display image. For example, a control signal is output to the multiplexer 2103, and image signals to be displayed on the display panel are appropriately selected or combined. In this case, a control signal is generated for the display panel controller 2102 in accordance with the image signal to be displayed, and the display frequency, the scanning method (for example, interlaced or non-interlaced), the number of scanning lines on one screen, and the like are displayed. The operation of the device is appropriately controlled.

Also, image data and character / graphic information are directly output to the image generation circuit 2107, or an external computer or memory is accessed via the input / output interface circuit 2105 to access the image data or character / graphic information. Enter graphic information. Note that the CPU 2106
Of course, it may be related to work for other purposes. For example, it may directly relate to a function of generating and processing information, such as a personal computer or a word processor. Alternatively, it may be connected to an external computer network via the input / output interface circuit 2105 as described above, and work such as numerical calculation may be performed in cooperation with external equipment.

The input unit 2114 is connected to the CPU 21.
06 is for the user to input commands, programs, data, and the like. For example, in addition to a keyboard and a mouse, a joystick, a barcode reader,
Various input devices such as a voice recognition device can be used.

Also, the decoder 2104 has the
And 2113 are circuits for inversely converting various image signals inputted from 2113 into three primary color signals or luminance signals and I and Q signals. It is to be noted that the decoder 2104 desirably includes an image memory therein, as indicated by a dotted line in FIG. This is for handling a television signal that requires an image memory when performing inverse conversion, such as the MUSE method. Further, the provision of the image memory facilitates the display of a still image, or enables image processing and editing including image thinning, interpolation, enlargement, reduction, and synthesis in cooperation with the image generation circuit 2107 and the CPU 2106. This is because there is an advantage that it can be easily performed.

The multiplexer 2103 is provided by the C
A display image is appropriately selected based on a control signal input from the PU 2106. That is, the multiplexer 2103 selects a desired image signal from the inversely converted image signals input from the decoder 2104 and outputs the selected image signal to the drive circuit 2101. In that case, by switching and selecting an image signal within one screen display time, it is possible to divide one screen into a plurality of areas and display different images depending on the areas, as in a so-called multi-screen TV. .

The display panel controller 2
Reference numeral 102 denotes a circuit for controlling the operation of the drive circuit 2101 based on a control signal input from the CPU 2106.

First, as a signal related to the basic operation of the display panel, for example, a signal for controlling an operation sequence of a driving power source (not shown) for the display panel is output to the driving circuit 2101. Also,
A signal for controlling, for example, a screen display frequency and a scanning method (for example, interlaced or non-interlaced) related to the display panel driving method is output to the driving circuit 2101.

In some cases, a control signal related to image quality adjustment such as brightness, contrast, color tone, and sharpness of a display image may be output to the drive circuit 2101.

The drive circuit 2101 is a circuit for generating a drive signal to be applied to the display panel 2100, and includes an image signal input from the multiplexer 2103 and the display panel controller 21.
02 operates based on a control signal input from the control unit 02.

The function of each part has been described above. With the configuration illustrated in FIG. 58, in this display device, image information input from various image information sources is displayed on the display panel 2.
100 can be displayed. That is, various image signals including television broadcasting are transmitted to the decoder 21.
After the inverse conversion at 04, the multiplexer 2103
And is input to the driving circuit 2101 as appropriate. On the other hand, the display controller 2102 generates a control signal for controlling the operation of the drive circuit 2101 according to the image signal to be displayed. The drive circuit 2101 controls the display panel 2 based on the image signal and the control signal.
100 is applied with a drive signal. Accordingly, an image is displayed on display panel 2100. These series of operations are totally controlled by the CPU 2106.

In the present display device, the image memory incorporated in the decoder 2104, the image generation circuit 21
07 and the CPU 2106 involve not only displaying a selected one of a plurality of pieces of image information but also enlarging, reducing, rotating, moving, edge emphasizing, thinning out, and interpolating the displayed image information. , Color conversion,
It is also possible to perform image processing such as image aspect ratio conversion and the like, and image editing such as combining, erasing, connecting, exchanging, and fitting. Although not specifically mentioned in the description of the present embodiment, a dedicated circuit for processing and editing audio information may be provided as in the above-described image processing and image editing.

Therefore, the present display device can be used as a display device for a television broadcast, a terminal device for a video conference, an image editing device for handling still images and moving images, a computer terminal device, an office terminal device such as a word processor,
It can be equipped with the functions of a game machine etc. by one unit, and has a very wide application range for industrial or consumer use.

FIG. 58 shows only an example of a configuration of a display device using a display panel using a surface conduction electron-emitting device as an electron beam source, and the present invention is not limited to this. Needless to say. For example, FIG.
Circuits related to functions that are not necessary for the purpose of use among the eight components may be omitted. Conversely, additional components may be added depending on the purpose of use. For example, when the present display device is applied as a video phone, it is preferable to add a transmission / reception circuit including a television camera, an audio microphone, an illuminator, and a modem to the components.

In the present display device, in particular, since the display panel using the surface conduction electron-emitting device as the electron beam source can be easily made thin, the depth of the entire display device can be reduced. In addition, the display panel using surface conduction electron-emitting devices as the electron beam source can easily enlarge the screen, and has high brightness and excellent viewing angle characteristics. It is possible to display well.

The application of the present invention can be applied to almost all image forming apparatuses having an electron source section in which a large number of electron-emitting devices are connected in parallel, in addition to the flat plate type image forming apparatus described in the embodiment. For example, it is extremely effective in the field of an electron beam drawing apparatus and an image recording apparatus.

[0283]

As described above, according to the present invention, it is possible to reduce the number of elements that are simultaneously energized during a period in which a certain row-direction wiring is selected, and to reduce the amount of current flowing through the selected row-direction wiring. And the effect of voltage drop due to wiring resistance is reduced. As a result, the distribution of the light emission luminance of the display panel due to the resistance of the row direction wiring is improved, and the luminance is made uniform and the luminance non-uniformity of the entire image display device is reduced.

Further, according to the present invention, the problem of uneven brightness in an image is eliminated, and the practical performance of a thin, large-area, large-capacity image forming apparatus is greatly improved.

Further, according to the present invention, the magnitude of the input signal is suppressed so that the total amount of electron emission does not exceed a certain value, and even if the average input signal level becomes large, the voltage to each element is reduced by the voltage drop. Non-uniformity of the applied voltage is reduced, and increase in power consumption and heat generation of the target are suppressed.

Further, according to the present invention, since the average luminance of the image display device is suppressed to a certain reference value or less, the luminance unevenness can be more efficiently eliminated, and in addition, the power consumption of the image display device and the use of the fluorescent plate are reduced. Fever is also suppressed.

Further, according to the present invention, it is possible to control based on the evaluation value obtained based on the light emission luminance of the device so that the average luminance of the entire light emission screen does not exceed a certain value. The increase and the heat generation of the fluorescent plate are suppressed.

[0288]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an image display device according to a first embodiment.

FIG. 2 is a timing chart illustrating timings of some signals according to the first embodiment.

FIG. 3 is a timing chart illustrating timings of some signals according to the first embodiment.

FIG. 4 is a diagram showing a configuration of a system control unit 14.

FIG. 5 is a time chart illustrating an example of an output timing of a modulation signal according to the first embodiment.

FIG. 6 is a diagram illustrating an example of a circuit configuration of one pulse width modulator in the modulation signal generation unit 9;

FIG. 7 is a time chart illustrating an example of an output timing of a modulation signal according to the second embodiment.

FIG. 8 is a time chart illustrating an example of an output timing of a modulation signal according to the third embodiment.

FIG. 9 is a block diagram illustrating a configuration of a drive circuit portion that is a part of an image forming apparatus according to a fourth embodiment.

FIG. 10 is a block diagram illustrating a detailed configuration of a voltage-to-pulse conversion circuit according to a fourth embodiment.

FIG. 11 shows arbitrary adjacent three modulation-side terminals m-1, m,
FIG. 9 is a diagram illustrating an example of an image signal corresponding to m + 1.

FIG. 12 shows element numbers m-1, m, and m + 1 shown in FIG.
3 is a diagram showing a signal obtained by converting the image signal of FIG. 1 into a pulse width corresponding to the amplitude.

13 is a block diagram illustrating details of pulse train rearranging circuits 142, 143, and 144 in the voltage-to-pulse converter shown in FIG.

FIG. 14 is a diagram illustrating an example of pulse train rearrangement by a pulse train rearrangement circuit according to a fifth embodiment.

FIG. 15 is a diagram illustrating suppression of a voltage drop in a row wiring.

FIG. 16 is a block diagram illustrating a configuration of a drive circuit portion of an image forming apparatus according to a fifth embodiment.

FIG. 17 shows an output of the ammeter 107 when an image is displayed for a plurality of screens.

FIG. 18 shows an output signal of the ammeter 107 when the output of the LPF is input to a low-pass filter (LPF) (not shown) included in the luminance evaluation circuit 108.

FIG. 19 is a block diagram illustrating a detailed configuration of a voltage-to-pulse conversion circuit according to a fifth embodiment.

20 is a diagram showing a signal obtained by converting an image signal corresponding to any three adjacent modulation-side terminals s-1, s, and s + 1 shown in FIG. 11 into a pulse by a voltage-pulse train conversion circuit 161. FIG.

FIG. 21 is a diagram illustrating an example of pulse train rearrangement by a pulse train rearrangement circuit according to the fifth embodiment.

FIG. 22 is a diagram illustrating a method for driving a multi-electron source and an image display device according to a sixth embodiment.

FIG. 23 shows voltage application (Vx1 to VxM, Vy1 to VyN) to row and column wirings according to the sixth embodiment.
6 is a time chart showing the timing of FIG.

FIG. 24 is a diagram illustrating an image display device according to a sixth embodiment.

FIG. 25 is a block diagram showing a detailed configuration of a decoder 221.

FIG. 26 is a pulse width modulation circuit 22 according to a sixth embodiment.
6 is a block diagram showing a configuration of FIG.

FIG. 27 is a pulse width modulation circuit 22 according to a sixth embodiment.
6 is a timing chart for explaining the operation of FIG.

FIG. 28 is a pulse width modulation circuit 22 according to a seventh embodiment.
6 is a block diagram illustrating the configuration of FIG.

FIG. 29 is a pulse width modulation circuit 22 according to a seventh embodiment.
6 is a timing chart for explaining the operation of FIG.

FIG. 30 is a diagram showing a time chart of the voltage applied to each wiring of the display panel by the driving device of the seventh embodiment.

FIG. 31 is a block diagram illustrating a configuration of a decoder 221 according to an eighth embodiment.

FIG. 32 is a diagram showing a luminance signal magnification value for luminance suppression according to the eighth embodiment.

FIG. 33 is a block diagram illustrating a configuration of an image display device according to a ninth embodiment.

FIG. 34 is a diagram illustrating luminance suppression according to the ninth embodiment.

FIG. 35 is a timing chart illustrating timings of drive signals according to the tenth embodiment.

FIG. 36 is a perspective view of the image display device according to the embodiment of the present invention, in which a part of a display panel is cut away.

FIG. 37 is a plan view illustrating a phosphor array of a face plate of the display panel.

FIG. 38 is a plan view (a) and a cross-sectional view (b) of a planar surface conduction electron-emitting device used in the embodiment.

FIG. 39 is a cross-sectional view showing a step of manufacturing the planar type surface conduction electron-emitting device.

FIG. 40 is a diagram showing an applied voltage waveform during the energization forming process.

FIG. 41 shows an applied voltage waveform (a) in the energization activation process;
It is a figure showing change (b) of discharge current Ie.

FIG. 42 is a sectional view of a vertical surface conduction electron-emitting device used in the embodiment.

FIG. 43 is a cross-sectional view showing a step of manufacturing a vertical surface conduction electron-emitting device.

FIG. 44 is a graph showing typical characteristics of the surface conduction electron-emitting device used in the embodiment.

FIG. 45 is a plan view of a substrate of the multi-electron beam source used in the embodiment.

FIG. 46 is a partial cross-sectional view of the substrate of the multi-electron beam source used in the embodiment.

FIG. 47 is a view showing an example of a conventionally known surface conduction electron-emitting device.

FIG. 48 is a diagram showing an example of a conventionally known FE.

FIG. 49 is a diagram showing an example of a conventionally known MIM type.

FIG. 50 is a diagram illustrating matrix wiring of a cold cathode device.

FIG. 51 is a diagram illustrating an example of a multi-electron beam source using matrix wiring.

FIG. 52 is a time chart for explaining a scanning signal and a modulation signal in a general pulse width modulation driving method.

FIG. 53 is a diagram showing a simplified equivalent circuit of a multi-electron beam source when one line is selectively driven.

FIG. 54 is a diagram showing a potential on a scanning signal line side of each surface conduction electron-emitting device in a certain row.

FIG. 55 is a diagram showing voltages applied to the respective surface conduction electron-emitting devices in the row shown in FIG. 54;

FIG. 56 is a diagram illustrating a method of applying a scanning signal to both sides of a row direction wiring and driving the row wiring.

FIG. 57 is a diagram showing a potential distribution on a certain row-direction wiring when a scanning signal is applied to both ends of the row-direction wiring and driven.

FIG. 58 is a block diagram of a multi-function image display device using the image display device according to the embodiment of the present invention.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Hidetoshi Suzuki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Aoji Isono 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Eiji Yamaguchi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (77)

[Claims] 1. An electron source driving device having a plurality of electron-emitting devices, wherein the plurality of electron-emitting devices are connected to a common row wiring and separate column wiring, wherein the plurality of electron-emitting devices are connected based on image information. Determining means for determining the time width of the modulation signal to be applied to each of the column-directional wirings; and forming a pulse train for the time width determined by the determining means by a combination of pulse application periods of a plurality of predetermined time widths. And a column drive unit for applying a drive signal based on the pulse train to each of the plurality of column direction wirings. An electron source driving device characterized in that it is different for each wiring. 2. The method according to claim 1, wherein the determining unit determines, for each column-directional wiring, a modulation signal having a time width of 2 n powers based on the image information. Assuming that y represents X to the power of y,
A pulse train corresponding to the time width of the modulated signal determined by the determination means is formed by a combination of n-time pulse application periods represented by powers of 2 from 2 ^ 0 to 2 ^ (n-1). The electron source driving device according to claim 1, wherein: 3. The column driving means, when a basic time width is t0, 2 ^ 0 × t0, 2 ^ 1 × t0,..., 2 ^ (n-1) × t
3. The electron source driving device according to claim 2, wherein a pulse train corresponding to a time width of the modulation signal determined by the determination unit is formed by a combination of pulse application periods having n types of time widths of 0. 4. The electron source driving device according to claim 2, wherein in the column driving means, the order of appearance of the pulses having the n time widths is a factorial of n. 5. The electron source according to claim 2, wherein the basic time width t0 is substantially equal to a value obtained by dividing one horizontal scanning period in image display by 2 ^ n-1. Drive. 6. The column driving means includes a pulse having n time widths represented by powers of 2 from 2 ^ 0 to 2 ^ (n-1),
3. The electron source driving device according to claim 2, wherein a pulse train corresponding to a time width of the modulation signal determined by the determination unit is formed by a combination with a predetermined time width in which no pulse exists. 7. The column driving means, when a basic time width is t0, 2 ^ 0 × t0, 2 ^ 1 × t0,..., 2 ^ (n-1) × t
A pulse application period having n types of time widths of 0 and a time width t0
7. The electron source driving device according to claim 6, wherein a pulse train corresponding to a time width of the modulation signal determined by the determination unit is formed by a combination with a period in which the pulse is not applied. 8. The type of appearance order of a pulse application period having n types of time widths changed for each column and one non-pulse application period is a factorial type of (n + 1). 8. The electron source driving device according to 7. 9. The electron source driving device according to claim 7, wherein the basic time width t0 is substantially equal to a value obtained by dividing one horizontal scanning period in image display by 2 ^ n. 10. The method according to claim 1, wherein the determining unit determines, for each column-directional wiring, one of modulation signals having a time width of 2 n powers based on the image information. The pulse application period P having a width is determined by the determination means by a combination of pulse application periods of n types of groups from a first group having 2 ^ 0 to an nth group having 2 ^ (n-1). 3. The electronic device according to claim 2, wherein a pulse train corresponding to a time width of the modulation signal is formed, and in the column driving unit, an appearance order of the pulse application periods P belonging to each group is made different for each column wiring. Source drive. 11. The type of appearance order of 2 ^ n-1 basic pulse application periods P changed for each column is ((2 ^ n-1)!) / (1! × 2! ×... × (2 ^ (n-1))
! 11. The electron source driving device according to claim 10, wherein the device is of a type. 12. The column drive means includes n types of groups from a first group having 2 ^ 0 pulse application periods P having a basic time width to an nth group having 2 ^ (n-1) pulse application periods. A pulse train corresponding to the time width of the modulation signal determined by the determination unit is formed by a combination of the pulse application period and the non-pulse application period having the basic time width. 11. The electron source driving device according to claim 10, wherein the order of appearance of P and the non-pulse application period is different for each column wiring. 13. In the column driving means, the appearance order of 2 ^ n-1 basic pulse application periods P and one non-pulse application period changed for each column is ((2 ^ n)!) / (1 ! × 1! × 2! × ... × (2 ^ (n-
1))! 13. The electron source driving device according to claim 12, wherein the device is of a type. 14. An evaluation unit for outputting an evaluation value based on the amount of electron emission of the electron source; and the determining unit for controlling the amount of electron emission of the electron source based on the evaluation value obtained by the evaluation unit. 14. The electron source driving device according to claim 1, further comprising an adjusting unit that adjusts a time width of the modulation signal determined by: 15. The adjusting unit compares an evaluation value obtained by the evaluating unit with a predetermined reference value, and when the evaluation value exceeds the reference value, suppresses the amount of electron emission from the electron source. 15. The electron source driving device according to claim 14, wherein the image information is adjusted as much as possible. 16. The apparatus according to claim 14, wherein the evaluation unit detects an average value of a signal level indicated by the image information, and uses the average value of the detected signal levels as an evaluation value. Electron source drive. 17. The electronic device according to claim 14, wherein the evaluation unit detects an average value of a current caused by electrons emitted from the electron source, and uses the average value of the current as an evaluation value. Source drive. 18. The apparatus according to claim 17, wherein said evaluation means detects an average current value of a line for supplying power to a high voltage generator for applying a high voltage to a target of said electron source. Electron source drive. 19. The method according to claim 19, wherein the adjusting unit adjusts a signal level of an image input signal input to the apparatus based on the evaluation value, thereby adjusting an amount of electrons reaching a target based on the evaluation value. Claims 14 to 18
An electron source driving device according to any one of the above. 20. The electron source driving device according to claim 1, wherein said electron-emitting device is a surface conduction electron-emitting device. 21. The electron source driving device according to claim 1, wherein the electron-emitting device is an FE-type electron-emitting device. 22. The electron source driving device according to claim 1, wherein the electron-emitting device is a MIM-type electron-emitting device. 23. A semiconductor device according to claim 23, further comprising: a row selection unit configured to apply a selection signal to the plurality of row-directional wirings to drive the electron-emitting device connected to the one row-directional wiring. 20. The electron source driving device according to claim 1, wherein: 24. The electron source has a simple matrix structure in which a plurality of electron-emitting devices arranged in a matrix on a plane are connected by a plurality of row wirings and column wirings. 24. The electron source driving device according to any one of 1 to 23. 25. An electron source having a simple matrix structure in which surface conduction electron-emitting devices arranged in a matrix on a plane are connected by a plurality of row-direction wirings and column-direction wirings. An image forming apparatus comprising: the electron source driving device described above; and a target that is arranged to face the electron source and that irradiates electrons emitted from the electron source to form a visible image. 26. The image forming apparatus according to claim 25, wherein a phosphor is used for the target. 27. A method of driving an electron source, comprising: a plurality of electron-emitting devices, wherein the plurality of electron-emitting devices are connected to a common row wiring and separate column wiring, and A determining step of determining the time width of the modulation signal to be applied to each of the column-directional wirings, and forming a pulse train of the time width determined in the determining step by a combination of a predetermined plurality of types of pulse widths of a time width. A column drive step of applying a drive signal based on the pulse train to each of the plurality of column direction wirings. In the column drive step, the order of appearance of the pulses of the plurality of types of time widths is changed to the plurality of column directions. A method for driving an electron source, wherein the method is different for each wiring. 28. An electron source driving device having a plurality of electron-emitting devices, wherein the plurality of electron-emitting devices are connected to a common row wiring and separate column wiring, wherein the plurality of electron-emitting elements are connected based on image information. Determining means for determining an application period of the modulation signal to be applied to each of the column wirings, and a pulse having an application period determined by the determining means,
Column drive means for dividing one scan period in image formation into P regions obtained by dividing the scan period into P regions, rearranging the order, and applying a drive signal to each of the plurality of column wirings. Characteristic electron source driving device. 29. The electron source driving device according to claim 28, wherein the P regions have substantially equal periods. 30. An image processing apparatus further comprising: an evaluation unit that outputs a luminance evaluation value based on an electron emission amount of the electron source, wherein the determination unit is configured to perform the operation based on the image information and the luminance evaluation value obtained by the evaluation unit. 30. The electron source driving device according to claim 28, wherein an application period of a modulation signal applied to each of the plurality of column direction wirings is determined. 31. A luminance evaluation value obtained by said evaluation means, wherein a luminance value obtained when a pulse having an application period extending over substantially one horizontal period is applied is set as a maximum luminance value. 31. The electron source driving device according to claim 30, wherein an application period of the modulation signal is adjusted based on a magnitude relationship with the maximum luminance value. 32. In a case where the luminance evaluation value is B and the maximum luminance value is Bm, when B> Bm / P, the determining unit determines an application period of the modulation signal determined based on the image information. 32. The electron source driving device according to claim 31, wherein the modulation signal is multiplied by Bm / (P × B) to adjust the application period of the modulation signal. 33. The evaluation method according to claim 30, wherein the evaluation unit detects an average value of the signal levels indicated by the image information, and uses the average value of the detected signal levels as an evaluation value. An electron source driving device according to any one of the above. 34. The apparatus according to claim 30, wherein said evaluation means detects an average value of a current caused by electrons emitted from said electron source, and uses the average value of the current as an evaluation value. An electron source driving device according to claim 1. 35. The apparatus according to claim 34, wherein the evaluation means detects an average current value of a line for supplying power to a high voltage generator for applying a high voltage to a target of the electron source. Electron source drive. 36. The apparatus according to claim 36, wherein the determining unit adjusts an application period of the modulation signal by adjusting a signal level of an image input signal input to the apparatus based on the evaluation value. An electron source driving device according to any one of claims 30 to 35. 37. The electron source driving device according to claim 28, wherein said electron-emitting device is a surface conduction electron-emitting device. 38. The electron source driving device according to claim 28, wherein the electron-emitting device is an FE-type electron-emitting device. 39. The electron source driving device according to claim 28, wherein the electron-emitting device is a MIM-type electron-emitting device. 40. The apparatus according to claim 40, further comprising: a row selection unit configured to apply a selection signal to the plurality of row-directional wirings in order to drive an electron-emitting device connected to one of the row-directional wirings. The electron source driving device according to any one of claims 28 to 36. 41. The electron source has a simple matrix structure in which a plurality of electron-emitting devices arranged in a matrix on a plane are connected by a plurality of row wirings and column wirings. 41. The electron source driving device according to any one of 28 to 40. 42. An electron source having a simple matrix structure in which surface conduction electron-emitting devices arranged in a matrix on a plane are connected by a plurality of row wirings and column wirings, and An image forming apparatus comprising: the electron source driving device described above; and a target that is arranged to face the electron source and that irradiates electrons emitted from the electron source to form a visible image. 43. The image forming apparatus according to claim 42, wherein a fluorescent material is used for said target. 44. A method for driving an electron source, comprising a plurality of electron-emitting devices, wherein the plurality of electron-emitting devices are connected to a common row wiring and separate column wiring, wherein the plurality of electron-emitting elements are connected based on image information. A determining step of determining an application period of the modulation signal to be applied to each of the column wirings, and a pulse having the application period determined in the determining step,
A column driving step of dividing one scanning period in the image formation by P regions obtained by dividing the scanning period into P regions, rearranging the order, and applying a driving signal to each of the plurality of column direction wirings. Characteristic electron source driving method. 45. An electron source driving device having a plurality of electron-emitting devices, wherein said plurality of electron-emitting devices are connected to a common row wiring and separate column wiring, and wherein said plurality of electron-emitting elements are connected based on image information. Determining means for determining a time width of a pulse signal to be applied to each of the column wirings; and a pulse of a first mode having a time width determined by the determining means rising in synchronization with the start of one horizontal scanning period in image formation. A column to be applied to each of the plurality of column-directional wirings by mixing a signal and a pulse signal of the second mode having a time width determined by the determining unit and falling in synchronization with the end of the one horizontal scanning period An electron source driving device, comprising: driving means. 46. When applying the pulse of the first mode or the pulse of the second mode to each of the plurality of column-directional wirings, the column driving means performs the control based on a column number of the column-directional wiring. 46. The electron source driving device according to claim 45, wherein it is determined which of the first and second forms of pulse is to be applied. 47. The column driving means, when applying the first mode pulse or the second mode pulse to each of the plurality of column direction wirings, based on image information corresponding to the column direction wiring. 46. The electron source driving device according to claim 45, wherein it is determined which of the first and second forms of pulse is to be applied. 48. When applying the pulse of the first mode or the pulse of the second mode to each of the plurality of column-directional wirings, the column driving means generates a pulse signal corresponding to the column-directional wiring. 46. The electron source driving device according to claim 45, wherein it is determined which of the first or second form of pulse is to be applied based on the time width determined by the determination unit. 49. Evaluation means for outputting an evaluation value based on the amount of electron emission of the electron source; and the determining means for controlling the amount of electron emission of the electron source based on the evaluation value obtained by the evaluation means. 49. The electron source driving device according to claim 45, further comprising adjusting means for adjusting a time width of the pulse signal determined by the following. 50. The adjustment means compares the evaluation value obtained by the evaluation means with a predetermined reference value, and when the evaluation value exceeds the reference value, suppresses the amount of electron emission by the electron source. 50. The electron source driving device according to claim 49, wherein the image information is adjusted to adjust the image information. 51. The apparatus according to claim 49, wherein the evaluation means detects an average value of a signal level indicated by the image information, and sets the average value of the detected signal levels as an evaluation value. Electron source drive. 52. The electron device according to claim 49, wherein the evaluation means detects an average value of a current caused by electrons emitted from the electron source, and uses the average value of the current as an evaluation value. Source drive. 53. The apparatus according to claim 52, wherein said evaluation means detects an average current value of a line for supplying power to a high voltage generator for applying a high voltage to a target of said electron source. Electron source drive. 54. The adjustment means adjusts a signal level of an image input signal input to the apparatus based on the evaluation value, thereby adjusting an amount of electrons reaching a target based on the evaluation value. 50. The electron source driving device according to claim 49, wherein 55. The electron source driving device according to claim 45, wherein the electron-emitting device is a surface conduction electron-emitting device. 56. The electron source driving device according to claim 45, wherein the electron-emitting device is an FE-type electron-emitting device. 57. An electron source driving device according to claim 45, wherein said electron-emitting device is a MIM-type electron-emitting device. 58. A semiconductor device further comprising row selection means for applying a selection signal to the plurality of row-directional wirings in order to drive an electron-emitting device connected to one of the row-directional wirings. The electron source driving device according to any one of claims 45 to 54. 59. The electron source has a simple matrix structure in which a plurality of electron-emitting devices arranged in a matrix on a plane are connected by a plurality of row wirings and column wirings. 59. The electron source driving device according to any one of 45 to 58. 60. An electron source having a simple matrix structure in which surface conduction electron-emitting devices arranged in a matrix on a plane are connected by a plurality of row-direction wirings and column-direction wirings, and the electron source according to claim 45. An image forming apparatus, comprising: the electron source driving device described above; and a target that is arranged to face the electron source and that irradiates electrons emitted from the electron source to form a visible image. 61. The image forming apparatus according to claim 60, wherein a phosphor is used for the target. 62. A method of driving an electron source, comprising a plurality of electron-emitting devices, wherein the plurality of electron-emitting devices are connected to a common row wiring and separate column wiring, wherein the plurality of electron-emitting elements are connected based on image information. A determining step of determining a time width of a pulse signal to be applied to each of the column wirings; and a pulse of the first mode having the time width determined in the determining step rising in synchronization with the start of one horizontal scanning period in image formation. A column to be applied to each of the plurality of column-directional wirings by mixing a signal and a pulse signal of the second mode having a time width determined in the determination step falling in synchronization with the end of the one horizontal scanning period And a driving step. 63. An electron source driving device, comprising: a plurality of electron-emitting devices, wherein the plurality of electron-emitting devices are connected to a common row wiring and separate column wiring. Row selection means for applying a selection signal to the row direction wiring to drive the surface conduction electron-emitting device connected to one row direction wiring; and applying the selection signal to each of the plurality of column direction wirings based on image information. Determining means for determining the amplitude of the pulse signal; evaluating means for outputting an evaluation value based on the electron emission amount of the electron source; and estimating the electron emission amount of the electron source based on the evaluation value obtained by the evaluation means. Adjusting means for adjusting the time width of the pulse signal for controlling; applying a pulse signal having an amplitude determined by the determining means and a time width adjusted by the adjusting means to each of the plurality of column-directional wirings Row drive Electron source driving apparatus characterized by comprising: means. 64. The electron source drive according to claim 63, wherein the column driving unit changes the rising timing of the pulse signal to form a pulse signal having a time width adjusted by the adjusting unit. apparatus. 65. The electron source according to claim 63, wherein the column drive unit forms a pulse signal having a time width adjusted by the adjustment unit by changing a fall timing of the pulse signal. Drive. 66. The column driving unit divides the plurality of column-directional wires into a first group and a second group, and changes the rising timing of a pulse signal to the column-directional wires belonging to the first group. Applying a pulse signal whose width has been adjusted by applying a pulse signal whose width has been adjusted and changing a fall timing of the pulse signal to a column-directional wiring belonging to the second group. Item 64. The electron source driving device according to Item 63. 67. The apparatus according to claim 63, wherein said evaluation means detects an average value of a signal level indicated by said image information, and sets the average value of the detected signal levels as an evaluation value. An electron source driving device according to any one of the above. 68. The apparatus according to claim 63, wherein the evaluation means detects an average value of a current caused by electrons emitted from the electron source, and sets the average value of the current as an evaluation value. An electron source driving device according to claim 1. 69. The evaluation method according to claim 68, wherein the evaluation unit detects an average current value of a line that supplies power to a high voltage generation unit for applying a high voltage to a target of the electron source. Electron source drive. 70. The electron source driving device according to claim 63, wherein said electron-emitting device is a surface conduction electron-emitting device. 71. The electron source driving device according to claim 63, wherein said electron-emitting device is an FE-type electron-emitting device. 72. The electron source driving device according to claim 63, wherein said electron-emitting device is a MIM-type electron-emitting device. 73. A semiconductor device according to claim 73, further comprising: a row selection unit configured to apply a selection signal to the plurality of row-directional wirings to drive an electron-emitting device connected to the one row-directional wiring. 70. The electron source driving device according to claim 63. 74. The electron source has a simple matrix structure in which a plurality of electron-emitting devices arranged in a matrix on a plane are connected by a plurality of row wirings and column wirings. 73. The electron source driving device according to any one of 63 to 73. 75. An electron source having a simple matrix structure in which surface conduction electron-emitting devices arranged in a matrix on a plane are connected by a plurality of row wirings and column wirings. An image forming apparatus comprising: the electron source driving device described above; and a target that is arranged to face the electron source and that irradiates electrons emitted from the electron source to form a visible image. 76. The image forming apparatus according to claim 75, wherein a phosphor is used for the target. 77. A method for driving an electron source, comprising a plurality of electron-emitting devices, wherein the plurality of electron-emitting devices are connected to a common row wiring and separate column wiring, wherein the plurality of electron-emitting elements are connected based on image information. A determining step of determining an amplitude of a pulse signal applied to each of the column-directional wirings, an evaluating step of outputting an evaluation value based on an electron emission amount of the electron source, and an evaluation value obtained in the evaluating step. An adjusting step of adjusting a time width of the pulse signal to control an electron emission amount of the electron source; and a plurality of pulse signals having the amplitude determined in the determining step and the time width adjusted in the adjusting step. A column driving step of applying a voltage to each of the column-directional wirings.