JPH11282512A - Sequence controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sequence controller for surely and quickly performing a sequence arithmetic operation by asynchronously reading the state of a bit arithmetic CPU. SOLUTION: Relating to a sequence controller, an instruction read from a program memory 31 is stored in a flip flop 32, and temporarily preserved in a flip flop 33. A flip flop 36 maintains a content indicating the state of a bit arithmetic CPU. A multiplexer 34 selects the content of the flip flop 32 in a normal operation, and selects the content of the flip flop 33 at the time of the read end of a word arithmetic CPU. While the word arithmetic CPU is reading the content of the flip flop 36, the multiplexer 35 feedbacks and preserves the content of the flip flop 36 instead of a content from the multiplexer 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bit operation CP.
The present invention relates to a sequence controller that performs a sequence operation using U and a word operation CPU.

[0002]

2. Description of the Related Art In many cases, a sequence controller executes a bit operation for processing a coil instruction or a contact instruction. Therefore, a CPU dedicated to a bit operation is employed to increase the speed. Therefore, the two CPs of the bit operation CPU and the word operation CPU for executing the numerical instructions and managing the system.
U.

As shown in FIG. 3, a circuit for performing a sequence operation includes a bit operation CPU 11 and a word operation CPU 1.
2. Program memory (PM) 13 and data memory (D
M) 14.

In order to execute a sequence, each CPU reads a sequence instruction from the program memory 13 and
The bit instruction is executed by the bit operation CPU 11, and the numerical instruction is executed by the word operation CPU 12. Depending on the type of instruction, each CPU processes in order.

[0005] The word operation CPU 12 has a role of controlling the system management in addition to the execution of numerical instructions.
It is necessary to grasp the state of the PU 11. Bit operation CP
U11 has a status register 11A indicating whether a bit operation instruction is being executed or stopped, and a word operation CPU 1
2 reads the state of the bit operation CPU 11 by reading the register 11A at the time of a request from the bit operation CPU 11 or during the idle time of the word operation CPU itself.

[0006]

In the sequence operation circuit shown in FIG. 3, the word operation CPU 12 has a role of managing the system, and it is necessary to grasp the state of the bit operation CPU 11. The status of the bit operation CPU 11 is determined by reading the status register 11A of the bit operation CPU 11 by the word operation CPU 12.

Since the contents of the status register are changed by the execution of the instruction by the bit operation CPU 11 as shown in FIG.
If the data is read asynchronously with the execution of the data, the data may change during the read.

As a conventional countermeasure, a bit operation CPU is used.
11 outputs a read request signal to the word operation CPU 12, and the bit operation CPU 11 outputs the status register 11A.
Are fixed to prevent data from changing during reading of the word operation CPU 12.

According to this method, the bit operation CPU 11 terminates the operation and outputs a request signal, and upon receiving the request signal, the word operation CPU 12 interrupts the operation being processed and reads the status register 11A, and then reads the sequence instruction. Will run.

For this reason, software processing of the word operation CPU 12 becomes complicated, and it takes a long time to move the processing from the bit operation CPU 11 to the word operation CPU 12.

It is an object of the present invention to provide a sequence controller for reliably and quickly performing a sequence operation while asynchronously reading the state of a bit operation CPU.

[0012]

SUMMARY OF THE INVENTION The present invention provides a bit operation C
The content of the status register of the PU is the word operation C
By preventing data from changing during PU reading,
It enables reading from the word operation CPU asynchronously, simplifies the software processing of the word operation CPU, and speeds up the transfer time of the process from the bit operation CPU to the word operation CPU. .

A bit operation CPU for processing coil instructions and contact instructions and a word operation CPU for processing numerical instructions and system management, the word operation CPU indicating the state of the bit operation CPU. By reading the contents of the status register, the bit operation CP
In the sequence controller that grasps the state of U,
The status register circuit of the bit operation CPU includes a first flip-flop for storing an instruction read from a program memory, a second flip-flop for temporarily storing the contents of the first flip-flop, and a state of the bit operation CPU. Is stored, and the third word is read by the word operation CPU in a read operation.
And the contents of the first flip-flop are normally selected and passed to the third flip-flop, and the second operation is performed at the read end of the word operation CPU.
A first multiplexer for selecting the contents of the flip-flop and passing the selected flip-flop to the third flip-flop; and Instead, a second multiplexer for feeding back the content of the third flip-flop is provided.

[0014]

FIG. 1 is a circuit diagram of a status register section of a bit operation CPU according to an embodiment of the present invention, and FIG. 2 shows the operation timing thereof.

The program memory 31 stores a sequence command and is external to the bit operation CPU 11. The flip-flop 32 stores the program memory 31
Stores the instruction read from. Flip-flop 33
Temporarily stores the contents of the flip-flop 32 for the flip-flop 36 described later.

The multiplexer MUX 34 switches between data stored in the flip-flop 32 and data stored in the flip-flop 33 according to the state of the read end signal.

When the word operation CPU 12 reads the status register 11A while the bit operation CPU 11 is reading an instruction from the program memory 31, the flip-flops 32 and 33 change to the contents of the next instruction.

The contents of the flip-flop 33 are
Since the content of F32 is stored, the word operation CPU 1
By sending the contents of the flip-flop 33 to the flip-flop 36 at the end of the read operation of No. 2, it is possible to prevent one of the contents of the flip-flop 36 from missing.

The multiplexer 35 is a word operation CPU.
During the reading, the contents of the flip-flop 36 are selected and fed back so that the contents of the flip-flop 36 do not change while the status register 11A is reading the status register 11A.

The flip-flop 36 is the contents of the status register itself, and the word operation CPU 12 reads the flip-flop 36 to execute the bit operation C
The state of the PU 11 is grasped.

[0021]

As described above, according to the present invention, the contents of the status register of the bit operation CPU can be read asynchronously from the word operation CPU by preventing data from changing during reading of the word operation CPU. Therefore, the software processing of the word operation CPU can be simplified, and the moving time of the processing from the bit operation CPU to the word operation CPU can be increased.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram showing an embodiment of the present invention.

FIG. 2 is an operation time chart in the embodiment.

FIG. 3 is a sequence operation circuit diagram.

FIG. 4 is a time chart for an asynchronous read.

[Explanation of symbols]

 11 bit operation CPU 12 word operation CPU 13, 31 program memory 14 data memory 32, 33, 36 flip-flop 34, 35 multiplexer

Claims (1)

[Claims] The present invention comprises two CPUs, a bit operation CPU for processing a coil instruction and a contact instruction, and a word operation CPU for processing a numerical instruction and system management, wherein the word operation CPU is in a state of the bit operation CPU. By reading the contents of the status register indicating
In the sequence controller for grasping the state of the PU, the status register circuit of the bit operation CPU comprises: a first flip-flop for storing an instruction read from a program memory; and a second flip-flop for temporarily storing the contents of the first flip-flop.
And a third flip-flop for reading the content by the read operation by the word operation CPU, and normally storing the content indicating the state of the bit operation CPU. The content is selected and passed to the third flip-flop, and the word operation CPU
A first multiplexer that selects the content of the second flip-flop at the read end of the third flip-flop and transfers the selected flip-flop to the third flip-flop; A sequence controller, comprising: a second multiplexer that feeds back the content of the third flip-flop instead of the content from one multiplexer.