JPH11275601A - Chroma signal processor - Google Patents

Abstract

(57) [Summary] ACC amplifier and ACC for chroma signal processing device
Digitalization of the detector is realized. An ACC amplifier is provided in a stage preceding a decoder, and an ACC detection input signal is extracted from an input stage of an encoder and supplied to an ACC detection unit. Furthermore, ACC
A limiter 18 is provided immediately after the amplifier, and an overflow pulse output from the
Decrease the gain of the C amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chroma signal processing apparatus suitable for use in a recording / reproducing apparatus which converts a modulated chroma signal represented by a home video tape recorder (hereinafter abbreviated as "VTR") into a frequency and records it. The present invention relates to a device, and is particularly suitable for application to a chroma signal processing device that realizes this by digital processing.

[0002]

2. Description of the Related Art An example in which a signal processing device of a home VTR is realized by digital processing is disclosed in November 29, 1994.
Television Society report of the announcement "Development of SVHS 2nd generation digital signal processing system" (ITE Techni
cal Report Vol. 18, No. 72, P
P125 to 130, CE94-44 (Nov. 199
An example is described in 4)). In a form similar to this case,
FIG. 6 shows the system.

FIG. 6 is a block diagram of a conventional chroma signal processing device. In FIG. 6, during recording, the chroma subcarrier frequency fsc (about 3.58 MHz in the NTCS system)
The fsc-modulated chroma signal modulated at is input to the terminal 1 and, at the time of reproduction, the low-frequency conversion carrier flsc (VHS, N
Flsc modulated at about 629 kHz in the TSC system)
The modulated chroma signal is input to terminal 1. Analog ACC
The analog ACC circuit composed of the amplifier 2 and the analog ACC detector 3 controls the feedback loop of the analog ACC circuit.
Control is performed so that the amplitude of the output signal of the amplifier 2 becomes substantially constant. However, when the reproduced signal includes an adjacent crosstalk component which is an interference signal from an adjacent track,
Unless this is removed, a correct signal amplitude cannot be detected. Therefore, in this case, the output signal of the analog ACC amplifier 2 has a small amplitude fluctuation, but the accuracy is not good. That is, a decoder 5 described later
Although the effect of stabilizing the amplitude to the extent that the signal bit width of the comb filter 6 does not overflow can be expected, the stabilization of the amplitude with the accuracy expected of the chroma signal output from the terminal 16 cannot be realized.

The output of the analog ACC amplifier 2 is A
The signal is converted into a digital signal by the / D converter 4 and decoded by the decoder 5 in the digital signal processing unit 17 to become a baseband chroma signal. When recording, switch 13
Is connected to the contact 13 a, and the converted carrier is input to the decoder 5 from the output of the fsc carrier generator 12. At the time of reproduction, the switch 13 is connected to the contact 13b and fls
The converted carrier is input from the c carrier generating unit 13 to the decoder 5. Since the switch 7 is connected to the contact 7b during reproduction of the signal output from the decoder 5, a signal from which adjacent crosstalk components have been removed through the comb filter 6 is input to the ACC amplifier 8. Since the switch 7 is connected to the contact 7a during recording, a signal bypassing the comb filter 6 is supplied to the ACC amplifier 8.

[0005] The ACC amplifier 8 and the ACC detector 9 constitute a digital ACC circuit, and are controlled so that the output signal amplitude of the ACC amplifier 8 becomes constant. In this digital ACC circuit, since the amplitude of the signal from which the adjacent crosstalk component has been removed is detected, the output signal of the ACC amplifier 8 is controlled to have a constant amplitude with high accuracy.
Input to the encoder 10. This digital ACC circuit compensates for the lack of accuracy of the analog ACC circuit described above. As a conversion carrier of the encoder 10, since the switch 15 is connected to the contact 15a during recording, fl
The output of the sc carrier generator 14 is selected and input to the output of the sc carrier generator 14 because the switch 15 is connected to the contact 15b during reproduction. Encoder 1
At 0, the chroma signal modulated to the low-frequency flsc modulated chroma signal at the time of recording, and the chroma signal modulated to the fsc modulated chroma signal at the time of reproduction is converted to an analog signal by the D / A converter 11 and output from the terminal 16.

[0006]

In FIG. 6, an analog ACC amplifier 2 and an analog ACC detector 3 are a digital integrated circuit (hereinafter abbreviated as IC) realized by a process such as a C-MOS while maintaining an analog circuit. ), It is difficult to incorporate the analog IC into the circuit, and an independent analog IC is provided at the front stage, which is an obstacle to further cost reduction.

An object of the present invention is to provide a chroma processing apparatus which eliminates an analog ACC amplifier and an analog ACC detector and reduces the cost.

[0008]

According to the present invention, A /
An ACC gain control unit composed of an ACC amplifier and an ACC detection unit is provided only in a digital signal processing unit that converts the frequency of the output of the D converter and outputs it as a second digital signal. Further, the ACC amplifier is arranged before a decoder that decodes the digitized modulated chroma signal into a baseband chroma signal, and amplifies the digitized modulated chroma signal. The baseband chroma signal extracted from the latter stage of the decoder is supplied to the ACC detector. Also, a limiter is connected to the output of the ACC amplifier so that the baseband limiter does not work. This limiter controls the ACC detector with an overflow pulse generated when the limiter function operates, and
The gain of the C amplifier is reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a case where the present invention is applied to a chroma signal processing device of a home VTR will be described as an example. FIG. 1 is a block diagram showing one embodiment of a chroma signal processing device according to the present invention. In the figure, the analog ACC circuit section comprising the analog ACC amplifier 2 and the analog ACC detector 3 in FIG.
7 is provided with a digital ACC circuit unit including an ACC amplifier 40 and an ACC detection unit 41. ACC amplifier 40
Is provided before the decoder 5, and the ACC amplifier 40 is controlled by the output from the ACC detector 41.

In this embodiment, the ACC detector 41
Since the ACC detection input signal is received after the switch 7, interference of adjacent crosstalk is avoided. The insertion position of the ACC amplifier 40 is determined by the A / D converter 4
Immediately after, that is, before the decoder 5, the amplitude of all signals processed by the subsequent circuits such as the decoder 5 and the comb filter 6 is stabilized, so that problems such as overflow hardly occur. Note that the trigger pulse input to the ACC detector 41 is used to extract a burst signal from the ACC detection input signal extracted from the switch 7. In this embodiment, since the analog ACC amplifier and the analog ACC detector are not used, the cost of the chroma signal processing device can be reduced. In addition, since the ACC detection input signal is extracted from the preceding stage of the encoder 10, there is an advantage that the amplitude of a signal processed by a decoder, a comb filter, or the like can be stabilized.

However, in the embodiment of FIG. 1, it is necessary to improve the following points. That is, the ACC amplifier 40
The ACC circuit composed of the ACC detector 41 and the ACC detector 41 cannot respond instantaneously to a change in the input signal amplitude.
One of the reasons is that if the time constant of the ACC circuit is made small so that it can respond to a high frequency of a color signal, the response is too fast, and the influence of disturbance due to noise or the like becomes liable. Therefore, a loop filter or the like is usually inserted, or an appropriate time constant is intentionally provided. In the case of the feedback connection as in the present embodiment, there is a delay due to the feedback system.
As described above, if the time constant of the ACC circuit is increased in order to prevent disturbance due to noise, there will be a response delay. In particular, in the process of a transient response in which the input signal amplitude suddenly changes, the output amplitude of the ACC amplifier 40 may greatly deviate from the desired amplitude. This phenomenon is likely to occur at the time of searching for a home VTR or performing special reproduction such as a still.

On the other hand, if the circuit after the ACC amplifier 40 has an extremely large dynamic range with respect to the desired amplitude, the circuit scale is increased and the cost is disadvantageous.
For example, it is customary to set a dynamic range such as 1.5 times or 2 times the desired amplitude. However, in the process of the above-described transient response, the output amplitude of the ACC amplifier 40 may exceed this dynamic range.
Problems occurring at this time will be described below with reference to FIG.

FIG. 2 is a vector diagram showing a hue change occurring in the baseband limiter. In the embodiment of the present invention shown in FIG. 1, signal processing is performed as a baseband chroma signal in a circuit section sandwiched between a decoder 5 and an encoder 10. That is, the modulated chroma signal C shown in FIG.
Is processed in the form of a signal decoded into an RY component Cr and a BY component Cb. The amplitudes of the RY component Cr and the BY component Cb by the baseband limiter (not shown in FIG. 1 but usually inserted between the decoder 5 and the encoder 10) due to the limitation of the dynamic range. FIG. 2B shows an example when the restriction acts.
As shown in FIG. 2A, the BY component Cb is more RY than the RY component.
Since the signal amplitude is larger than the component Cr, the limiter is B-
It acts more strongly on the Y component Cb. RY components Cr and B-
Since the compression ratios of the Y components Cb are not the same, the phase angles θ1 and θ2 of the modulated chroma signal C obtained by re-encoding the Y components Cb are shifted, and a problem of a change in hue occurs. In addition, if the above-described deviation between the phase angles θ1 and θ2 occurs in the burst signal portion, the detection processing of the chroma signal processing will be significantly disturbed, and further remarkable image disturbance will occur. Therefore, it is necessary to improve this point. is there.

FIG. 3 is a block diagram of another embodiment of the chroma signal processing device according to the present invention. Differences from the configuration of FIG. 1 described above will be described below. In this embodiment, the limiter 18 is inserted immediately after the ACC amplifier 40 of the digital signal processing unit 48, and the output is sent to the decoder 5. When the limiter function of the limiter 18 is activated,
The limiter 18 outputs an overflow pulse.
The overflow pulse is supplied to A through the ACC detector 41.
It acts to lower the gain of the CC amplifier 40. The other parts are the same as in FIG. 1 and will not be described.

FIG. 4 is a block diagram showing one embodiment of the ACC amplifier and limiter of FIG. A / D converter 4 in FIG.
Is input from the terminal 19 and processed by the code removing unit 20. The sign removal unit 20 removes the sign indicating the sign of the 9-bit signal, and outputs the signal as an 8-bit absolute value representation. That is, the negative portion of the positive / negative signal is turned back to the positive side. Further, the signal is multiplied by the 8-bit ACC control signal input from the terminal 28 by the multiplier 21 to output a 16-bit multiplication result. This 16
The number of effective bits of the bit signal is 8 bits. Therefore,
The bit distributor 22 distributes the input 16-bit signal into upper 10 bits and lower 6 bits, and sends only the upper 10 bits to the comparator 23 and the switch 24. Here, the lower 6 bits are an error range, and no problem occurs without using the 6-bit signal. Further, in this embodiment, since the standard value of the 8-bit ACC control signal is assumed to be 64, the lower 6 bits are discarded to 1/6.
ACC amplifier 4 which is multiplied by four and configured by a multiplier 21 and the like
A standard gain of 0 is set to 0 dB. If the operation of the upper 10-bit width is continued to be maintained in the subsequent circuit, the overflow in the base band, which is a problem, does not occur, but the circuit scale is significantly increased, which is not preferable. If the standard gain of the ACC amplifier 40 (mainly composed of the code removing unit 20, the multiplier 21, and the code restoring unit 25) is 0 dB, the post-stage circuit also has a bit width before the ACC amplifier, that is, 8 bits in absolute value representation. It is a preferable setting of the bit width that the processing is performed with 9 bits after code restoration.

The limiter 18 is composed of the comparator 23 and the switch 24.
Is configured. When the input is a digital value greater than 255, the comparator 23 outputs an overflow pulse from the terminal 27, and connects the switch 24 to the contact 24b to connect the input of the code restoration unit 25 to the fixed value 255.
Switch to. As a result, the output of switch 24 is limited to a maximum value of 255 and the bit width is reduced to eight. Thereafter, the code restoration unit 25 performs a process reverse to that of the code removal unit 20, that is, a plus / minus sign is added to the 8-bit signal and restored as a 9-bit signal having a plus / minus polarity.
6 is output. This bit width is the same as the bit width of the input terminal 19, and the above-described preferable bit width setting is realized. If this bit width is maintained in a circuit after the decoder receiving the output of the terminal 26, the hue change by the baseband limiter as described with reference to FIG. 2 does not occur.

The overflow pulse output from the comparator 23 is, for example, a high-level pulse in an overflow state, and a low-level pulse in a non-overflow state.
Level pulse which is output from terminal 27 and
The C detection unit 41 is controlled.

FIG. 5 is a block diagram showing an embodiment of the ACC detector of FIG. The signal extracted from the output of the switch 7 in FIG. 3 is input from the terminal 29 as an input signal of the ACC detector 41, and the signal amplitude is detected by the digital amplitude detector 30. Further, the difference from the reference value output from the reference value generating unit 32 is calculated by the subtracter 31 as an ACC error value, and the write enable (write enable) is written.
le) is input to a register 33 (hereinafter abbreviated as a register). A feedback loop composed of the register 33, the adder 34, and the register 38 constitutes an integrator, and a terminal 4
The ACC error value is fetched only during the period when the trigger pulse is input from 4 to the write enable terminal of the register. By setting the trigger pulse near the burst position of the chroma signal, an intermittent detection operation with only the burst signal amplitude is realized.

The overflow pulse input from the terminal 45 is ANDed with the trigger pulse input from the terminal 44 by the AND circuit 36, and then the switch 35
Control. The switch 35 includes a register 33 and an adder 34.
The switch 35 is connected to the contact 35b and selectively selects the output value -k (where k> 0) of the fixed value generation unit 37 only when both the trigger pulse and the overflow pulse rise. Let through. In other periods, the switch 35 is connected to the contact 35a,
3 output.

If the burst signal is subjected to the limiter operation in the limiter 18, the waveform does not have the original waveform of the burst, so that various detection operations of the chroma signal inside the VTR and on the TV side may become abnormal. Therefore, it is desirable to avoid this situation promptly. If the burst signal overflows due to the control with the overflow pulse, -k becomes the input of the adder 34 and the terminal 39 until the overflow is avoided.
, The ACC control signal is lowered, and by appropriately setting the -k value, an operation of quickly avoiding the overflow can be realized. Further, as described above, by performing control of adding the −k value to the input of the adder 34, the correction amount of the ACC control signal output from the terminal 39 is n times the −k value (where n is (The number of overflow pulses), so that even when a large correction amount is required, it is possible to cope with the problem by increasing the number n of overflow pulses.

The register 38 adds the error correction value to the current value, so that the error value becomes smaller.
In the convergence state in which the gain of the C amplifier 40 is changed and the error value becomes sufficiently small, the output of the amplitude detector 30 substantially matches the set value set by the reference value generator 32.

In this embodiment, since a limiter is provided at the output of the ACC amplifier, an overflow of a circuit after the decoder can be avoided by the amplitude limiting function of the limiter. By performing control to lower the gain, an ACC circuit having a function of quickly avoiding overflow of a burst signal can be realized.

[0023]

Since the ACC circuit can be entirely realized as a digital signal processing circuit, the rationalization of the chroma signal processing IC can be realized and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a chroma signal processing device according to the present invention.

FIG. 2 is a vector diagram showing a hue change generated by a baseband limiter in the block diagram of FIG. 2;

FIG. 3 is a block diagram showing another embodiment of the chroma signal processing device according to the present invention.

FIG. 4 is a block diagram showing one embodiment of an ACC amplifier and a limiter of FIG. 3;

FIG. 5 is a block diagram showing one embodiment of an ACC detector of FIG. 3;

FIG. 6 is a block diagram of a conventional chroma signal processing device.

[Explanation of symbols]

4 A / D converter, 5 decoder, 6 comb filter, 7, 13, 15, 24, 35 switch, 10 encoder, 11 D / A converter, 12 fsc carrier generator, 14 ... flsc carrier generator, 18 ... limiter, 20 ... code remover, 21 ... multiplier, 22 ... bit distributor, 23 ... comparator, 25 ... code recovery unit, 30 ... amplitude detector, 31 ... subtractor, 32 ... Reference value generators 33, 38
... Register with write enable, 34 ... Adder, 36
... AND circuit, 37 ... fixed value-k generator, 40 ... ACC
Amplifier, 41: ACC detector, 47, 48: Digital signal processor.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Katsuyuki Watanabe, Inventor Katsuyuki Watanabe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Multimedia Systems Development Division of Hitachi, Ltd. 292 Hitachi Image Information System Co., Ltd.

Claims (14)

[Claims] 1. A decoder for decoding a digitized modulated chroma signal into a baseband chroma signal, an ACC amplifier disposed before the decoder for amplifying the digitized modulated chroma signal, and an ACC control signal. A chroma signal processing apparatus comprising: an ACC detector that generates and supplies the ACC amplifier with a baseband chroma signal extracted from a subsequent stage of the decoder to the ACC detector. . 2. The chroma signal processing device according to claim 1, further comprising an A / D converter, wherein the analog modulation chroma signal not subjected to the automatic gain control is converted into a digital modulation chroma signal through the A / D converter. A chroma signal processing device for converting. 3. The chroma signal processing device according to claim 1, further comprising an encoder, wherein the baseband chroma signal gain-controlled by the ACC amplifier is converted into a modulated chroma signal by the encoder. Processing equipment. 4. An ACC amplifier for amplifying a digitized modulated chroma signal, a limiter connected to an output stage of the ACC amplifier, and an AC control signal for generating an ACC control signal.
An ACC detector for supplying the C amplifier; a decoder connected downstream of the limiter for decoding the modulated chroma signal into a baseband chroma signal; and supplying the baseband chroma signal to the ACC detector as an ACC detection input signal. And a means for controlling the gain of the ACC amplifier by the ACC control signal so that the amplitude of the baseband chroma signal is substantially constant. 5. The method according to claim 1, wherein the limiter outputs an overflow pulse when the limiter level exceeds a maximum limiter level, controls the ACC control signal output from the ACC detector, and lowers the gain of the ACC amplifier. Chroma signal processor. 6. The chroma signal processing device according to claim 4, wherein said limiter has a comparator, and said comparator outputs a signal of a predetermined amplitude when the amplitude of an input signal exceeds a limiter level. A chroma signal processing device for outputting an overflow pulse. 7. The chroma signal processing device according to claim 6, wherein the ACC detector generates a predetermined ACC control signal when the overflow pulse is input, and changes the gain of the ACC amplifier from a normal state. A chroma signal processing device characterized by lowering. 8. The chroma signal processing apparatus according to claim 7, wherein a trigger pulse is supplied to said ACC detector to generate said ACC signal.
While extracting the burst signal of the CC detector input signal,
The chroma signal processing device according to claim 1, wherein the predetermined ACC control signal is generated when the trigger pulse and the overflow pulse are input simultaneously. 9. An A / D converter for converting an analog modulated chroma signal to a first digital signal, and a digital signal processing for converting the frequency of the output of the A / D converter and outputting the converted signal as a second digital signal. Unit, an ACC gain control unit provided in the digital signal processing unit for controlling the gain of the first digital signal, and a D / A connected to the digital signal processing unit and converting the second digital signal to analog. A chroma signal processing apparatus, comprising: a converter for avoiding an overflow state caused by a transient response of the amplitude of the first digital signal. 10. An A / D converter for converting a modulated chroma signal of a video signal into a first digital signal as an analog input signal.
A D converter, a digital signal processing unit that converts the frequency of the first digital signal and outputs it as a second digital signal, and a D / A converter that converts the second digital signal into an analog output signal. In the chroma signal processing device provided, the digital signal processing unit has an ACC amplifier whose gain is controlled by an ACC control signal, and has a limiter level. When the input signal amplitude exceeds the limiter level, the digital signal processing unit maximizes the limiter level. A limiter that outputs a signal whose amplitude is limited as a value, and an AC that generates the ACC control signal.
A C detector, a decoder for decoding a modulated chroma signal into a baseband chroma signal, wherein the limiter is disposed between the ACC amplifier and the decoder, and the ACC amplifier is disposed at a stage prior to the decoder. A chroma signal processing device, wherein a gain is controlled by an ACC signal output from an ACC detector so that the amplitude of the baseband chroma signal is substantially constant. 11. The chroma signal processing device according to claim 10, wherein said limiter level is set to a value such that said baseband chroma signal does not overflow in a normal state. 12. The chroma signal processing device according to claim 10, wherein when the input signal amplitude exceeds the limiter level, the limiter outputs the signal whose amplitude is limited with the limiter level being the maximum value and overflows. A chroma signal processing device for outputting a pulse and reducing a gain of the ACC amplifier by the overflow pulse. 13. The chroma signal processing device according to claim 10, wherein when the input signal amplitude exceeds the limiter level, the limiter outputs a signal whose amplitude is limited by setting the limiter level to a maximum value and overflows. If the overflow pulse is output near the chroma signal burst period, the ACC signal is output.
A chroma signal processing device wherein the gain of an amplifier is reduced. 14. The chroma signal processing device according to claim 12, wherein said ACC detector has an integrator for integrating an ACC error value which is a difference between a result of amplitude detection and a reference value. A chroma signal processing device, wherein an input value of the integrator is replaced with a fixed value during a period of an overflow pulse.