JPH11273358A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device in which low power consumption and a high-speed operation of a multivalued memory can be realized. SOLUTION: A semiconductor memory device is provided with a plurality of memory cells in which pieces of information on a value of (n) [where (n) represents an integer of 4 or higher] are stored, with (n-1) pieces of latch circuits 16 which hold the pieces of information to be read out from the memory cells and with an encoder 18 which encodes outputs of the (n-1) pieces of latch circuits 16. Operation switch points of the (n-1) pieces of latch circuits 16 are set respectively to a potential between two adjacent potentials out of potentials corresponding to the information on the value of (n).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a multi-valued memory that stores four or more values of information in a 1-bit memory cell.

[0002]

2. Description of the Related Art FIG. 6 is a conceptual diagram showing an example of a memory cell of a multilevel memory. In FIG. 1, a 1-bit memory cell 30 and a bias circuit 32 are shown. The memory cell 30 is a floating gate type N-type MO.
S transistor whose gate, source and drain are connected to a word line WL, a ground and a bit line B, respectively.
L. The bias circuit 32 is connected to the bit line BL.

Here, it is assumed that the memory cell 30 stores quaternary information '00', '01', '10', and '11', and that the information stored in the memory cell 30 of the multilevel memory is The read operation will be described.

When reading information from the memory cell 30,
First, on / off of the transistor of the memory cell 30 is controlled by the word line WL. At this time, as shown in FIG. 7, the potential of the bit line BL is
Information “00”, “0” stored in the memory cell 30
1 ',' 10 'and' 11 ', corresponding to predetermined constant potentials VB0, VB1, VB2, VB3 (VB0
>VB1>VB2> VB3).

Subsequently, as disclosed in, for example, JP-A-7-37393 and JP-A-9-69293, the potential of the bit line BL is switched while the reference potential is switched using a differential amplification sense amplifier. And the reference potential are sequentially compared to read out the information of the memory cell 30. Hereinafter, the operation of reading information in a conventional multi-valued memory and its problems will be described with reference to the multi-valued sense amplifier disclosed in Japanese Patent Application Laid-Open No. 9-69293 as an example.

FIG. 8 is a conceptual diagram of an example of a multi-level sense amplifier disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 9-69293. As shown in FIG.
A differential amplification sense amplifier 36 for comparing the potential of the bit line BL with a reference potential, an output buffer 38 having two latch circuits 42a and 42b for holding the comparison result of the differential amplification sense amplifier 36, and a predetermined reference potential Is provided.

Here, the reference potential output from the reference circuit 40 is set to a potential between two adjacent potentials among the potentials VB0, VB1, VB2, VB3 of the bit line BL as shown in FIG. Have been. That is, the reference potential VR0 is equal to the potential VB0 and the potential VB.
1 and a reference potential VR1
Is set to a potential between the potential VB1 and the potential VB2,
The reference potential VR2 is set to a potential between the potential VB2 and the potential VB3.

In the multi-level sense amplifier 34, first, the reference circuit 40 outputs the central reference potential VR1, and the differential amplifier sense amplifier 36 compares the potential of the bit line BL with the reference potential VR1. As a result, it is detected whether the upper bit of the information of the memory cell 30 is “0” or “1”. The comparison result of the differential amplifier sense amplifier 36 is held in the latch circuit 42a and output as the upper bit B1 of the information of the memory cell 30.

Subsequently, the upper bits of the information held in the latch circuit 42a are fed back to the reference circuit 40. At this time, if the upper bit of the information of the memory cell 30 fed back from the latch circuit 42a is “0”, the control of the switching signal causes the reference circuit 4
The reference potential output from 0 is switched from the reference potential VR1 to the reference potential VR0,
If it is “1”, it is switched to the reference potential VR2.

That is, from the reference circuit 40,
The reference potential VR0 or VR2 is output according to the upper bits of the information of the memory cell, and the potential of the bit line BL is compared with the reference potential VR0 or VR2 by the differential amplifier sense amplifier. This allows
Whether the lower bit of the information is '0' or '1' is detected, held in the latch circuit 42b, and output as the lower bit B0 of the information of the memory cell 30.

As described above, in the conventional multi-valued memory, since the differential amplification sense amplifier 36 is used to read information from the memory cell 30, the number of bits of one word of the memory cell 30 to be read at a time is read. However, there is a problem that the power consumption increases as the number increases.
In addition, the comparison is performed by sequentially switching the reference potential,
Since the potential of the bit line BL is detected, the memory cell 3
There is also a problem that the reading speed of information from 0 becomes slow.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of reducing the power consumption and operating speed of a multi-valued memory in view of the problems based on the above-mentioned prior art. .

[0013]

In order to achieve the above object, the present invention provides a plurality of memory cells for storing n-value (n is an integer of 4 or more) information, and outputs from these memory cells. And (n-1) latch circuits for holding information, and an encoder for encoding the outputs of these latch circuits. The operation switching point of the (n-1) latch circuits is determined by the n value The semiconductor memory device is set to a potential between two adjacent potentials among the potentials corresponding to the above information.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings. FIG. 1 is a conceptual diagram showing a configuration of one embodiment of a memory cell of a semiconductor memory device according to the present invention. In FIG. 1, a 1-bit memory cell 10 and a precharge circuit 12 are shown for ease of explanation. Of course, a plurality of words may be provided, or one word may include a plurality of memory cells 10.

Here, the memory cell 10 has an n value (n is 4).
In the case of the present embodiment, '00', '0' are stored so as to be easily compared with the conventional example.
It is assumed that quaternary information of 1 ',' 10 'and' 11 'is stored. In the example shown, a floating gate type N-type MOS transistor is used for the memory cell 10, and its gate, source, and drain are connected to a word line WL, a ground, and a bit line BL, respectively.

In the illustrated example, the memory cell 10 is simply a floating gate type N-type MOS transistor.
² A memory cell such as a PROM or a flash memory may be used. Further, the method and means for storing information in the memory cell 10 are not limited at all. The precharge circuit 12
The bit line BL is precharged to a predetermined potential, and is connected to the bit line BL as shown in FIG.

When reading information from the memory cell 10,
First, the bit line BL is precharged to a predetermined potential by the precharge circuit 12. Then, the word line W
On / off of the transistor of the memory cell 10 is controlled by L. At this time, the bit line BL is discharged through the memory cell 10 at a speed corresponding to the information "00", "01", "10" and "11" of the memory cell 10, as shown in FIG. Gradually decreases.

In this embodiment, when the information of the memory cell 10 is "01", "10", "11", the bit line B
L is discharged at a rate of '01'<'10'<'11', and the potential of the bit line BL finally becomes the ground potential. When the information of the memory cell 10 is “00”, in this embodiment, the bit line BL is not discharged, and the potential 0 of the bit line BL maintains a state of being precharged by the precharge circuit 12. .

Here, after the operation of reading information from the memory cell 10 is started, that is, after the word line WL has changed from the low level to the high level, the potential of the bit line BL after a lapse of a predetermined time T _sw has elapsed. Of the bit line BL, that is, the potential between the potentials VB0 and VB1 of the bit line BL, the potential VSW0, the potential between the potentials VB1 and VB2 as the potential VSW1, and the potential between the potentials VB2 and VB3. Is the potential VSW2.

As described above, the information of the memory cell 10 is output to the bit line BL. Next, a reading circuit which is a feature of the present invention will be described. FIG. 3 is a configuration circuit diagram of one embodiment of the read circuit of the semiconductor memory device of the present invention. The read circuit 14 detects the potential of the bit line BL to which the information of the memory cell 10 is output, and
It reads information of 0, and has a latch circuit group 16 and an encoder 18 as shown in FIG.

Here, the latch circuit group 16 holds information output from the memory cell 10 for storing n-value information to the bit line BL, and has (n-1) latch circuits. . In the case of the present embodiment, three latch circuits 20a, 20 corresponding to the four-valued information stored in the memory cell 10
0b and 20c. For example, the latch circuit 20a
Is an N-type MOS transistor (hereinafter referred to as NMOS)
22, inverter IV0 and clocked inverter 2
4

In the latch circuit 20a, the NMOS 22
Is connected between the bit line BL and the inverter IV0, and its gate is connected to the control signal φ. Inverters IV0 and the clocked inverter 24, one output to each other is input to the other input, the output X ₀ of the inverters IV0 is inputted to the encoder 18.
The control input of clocked inverter 24 is connected to control signal φ, and its inverted control input is connected to control signal φ.

Note that the latch circuits 20b and 20c
Instead of inverter IV0, each inverter IV
1 and IV2 have been used, except that the output is X ₁ and X _2, respectively, is exactly the same structure as the latch circuit 20a.

In the latch circuit group 16, as shown in FIG. 4, the control signal φ is made high at the same time as the word line WL is made high, the NMOS 22 is turned on, and the clocked inverter 24 is turned on. Turned off. Thereafter, after a predetermined time T _sw , the control signal φ is set to the low level, the NMOS 22 is turned off, and the clocked inverter 24 is turned on. Thereby, the information of the memory cell 10 output to the bit line BL is held in the latch circuit group 16.

Here, the latch circuits 20a, 20b, 20
The operation switching points of the inverters IV0, IV1 and IV2 that constitute c are the above-mentioned potentials VSW0 and VSW0, respectively.
SW1 and VSW2. FIG. 5A is a conceptual diagram of the inverter, and FIG. 5B is a graph of the operation switching point. As shown in FIG. 5A, the input potential of the inverters IV0, IV1, and IV2 is A, and the output potential is Y.

As shown in FIG. 5B, the inverter IV
0 Operation Switching point, in FIG. 2, since the read operation of the data of the memory cell 10 is started, the potential VSW0 between potential VB0 and VB1 of the bit line BL after a predetermined fixed time T _sw. Similarly, the operation switching point of the inverter IV1 is the potential VSW1 between the potentials VB1 and VB2,
The operation switching points of the potentials VB2 and VB
3 is the potential VSW1.

In the read circuit 14, when the potential of the bit line BL is VB0 after a predetermined time T _sw from the start of the information read operation of the memory cell 10,
That is, when the information of the memory cell 10 is “00”, the operation switching points of the inverters IV0, IV1, IV2 are set to the potentials VSW0, VSW, respectively.
1, VSW2, the latch circuits 20a, 20b,
The outputs X ₀ , X ₁ , and X ₂ of 20c are all “0”.

Similarly, when the potential of the bit line BL is VB1
In this case, "1" is output from the latch circuit 20a, and "0" is output from the latch circuits 20b and 20c. When the potential of the bit line BL is VB2, "1" is output from the latch circuits 20a and 20b, and "0" is output from the latch circuit 20c. When the potential of the bit line BL is VB3, the latch circuit 20a,
'1' is output from both 20b and 20c.

Subsequently, the encoder 18 encodes the output of the latch circuit group 16, and in the case of this embodiment,
An EOR gate 26 for encoding the outputs X ₀ , X ₁ , and X ₂ of the latch circuit group 16 and a buffer 28 are provided. Here, the outputs X ₀ , X ₁ , and X ₂ are input to the EOR gate 26, the output X ₁ is input to the buffer 28, and the outputs of the EOR gate 26 and the buffer 28 are respectively stored in the memory cell 10. , The lower bit B0 and the upper bit B1.

Here, the outputs X ₀ , X ₀ ,... Of the latch circuit group 16 corresponding to the information stored in the memory cell 10 are shown.
X ₁ and X ₂ and the respective outputs B 1 and B 0 of the encoder 18 are shown in the following table.

[0031]

As described above, the semiconductor memory device of the present invention is different from a conventional multi-valued memory in that it does not use a differential amplifier sense amplifier or a reference circuit to read information stored in a memory cell. Even if the number of bits of a memory cell of one word read at a time increases, the power consumption can be reduced, and the potential of the bit line BL can be detected at a time by the latch circuit group. The reading speed can be increased.

The semiconductor memory device of the present invention is basically as described above. As described above, the semiconductor memory device of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and changes may be made without departing from the gist of the present invention. is there. That is, the circuit configurations of the memory cell, the precharge circuit, the latch circuit, and the encoder are not limited to those in the illustrated example, and various conventionally known configurations can be used.

[0034]

As described above in detail, in the semiconductor memory device of the present invention, the information output from the memory cell is used to determine whether the operation switching point is a potential corresponding to the n-value information stored in the memory cell. Are held by (n-1) latch circuits each set to a potential between two adjacent potentials, and the output of this latch circuit is encoded by an encoder. According to the semiconductor memory device of the present invention, the differential amplifier sense amplifier and the reference circuit are unnecessary, so that the power consumption of the multilevel memory can be reduced and the operation speed can be increased.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating a configuration of a memory cell of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a timing chart of an embodiment showing an operation of a memory cell.

FIG. 3 is a configuration circuit diagram of an embodiment of a read circuit of the semiconductor memory device of the present invention.

FIG. 4 is a timing chart illustrating an operation of a read circuit according to an embodiment.

5A is a conceptual diagram of an inverter, and FIG. 5B is a graph showing an operation switching point thereof.

FIG. 6 is a conceptual diagram illustrating an example of a memory cell of a multilevel memory.

FIG. 7 is a graph showing an example of potentials of quaternary information;

FIG. 8 is a conceptual diagram illustrating a configuration of an example of a multi-level sense amplifier.

FIG. 9 is a graph illustrating an example of a reference potential.

[Explanation of symbols]

 10, 30 memory cell 12 precharge circuit 14 read circuit 16 latch circuit group 18 encoder 20a, 20b, 20c, 42a, 42b latch circuit 22 N-type MOS transistor (NMOS) IV0, IV1, IV2 inverter 24 clocked inverter 26 EOR gate 28 buffer 32 bias circuit 34 multi-level sense amplifier 36 differential amplification sense amplifier 38 output buffer 40 reference circuit BL bit line WL word line φ, φ￣ control signal

Claims (1)

[Claims] 1. A plurality of memory cells for storing n-value (n is an integer of 4 or more) information, (n-1) latch circuits for holding information output from these memory cells, And an encoder that encodes an output of the latch circuit of (a), wherein an operation switching point of the (n-1) latch circuits is between two adjacent potentials among potentials corresponding to the n-value information. Semiconductor memory devices, each set to a potential of