JPH1126712A - Semiconductor integrated circuit device, its manufacturing method and its manufacturing device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce leakage current of an information storage capacitor. SOLUTION: A lower electrode 60 constituting an information storage capacitive element C is constituted by a polycrystalline silicon film obtained by solid-phase crystallization of a deposited amorphous silicon film.
The CMP method is used for the processing of No. 0. Further, the capacitance insulating film 61 constituting the information storage capacitance element C is composed of a silicon nitride film and a polycrystalline tantalum oxide film. The silicon nitride film is formed by a CVD method, and the tantalum oxide film is formed by depositing an amorphous tantalum oxide film by a CVD method and then performing heat treatment in an oxidizing atmosphere. Further, the upper electrode 62 of the information storage capacitor C is formed of a titanium nitride film formed by a CVD method. The intrinsic stress of the titanium nitride film is 1
GPa or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
(c) Random Access Memory).

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memory)
The ry) memory cells are arranged at intersections of a plurality of word lines and a plurality of bit lines arranged in a matrix on the main surface of the semiconductor substrate, and one memory cell selecting MISFET (M
etal Insulator SemiconductorField Effect Transisto
r) and one information storage capacitance element (capacitor) connected in series to this. The memory cell selection MISFET is formed in an active region surrounded by an element isolation region, and mainly includes a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions forming a source and a drain. Have been. The bit line is arranged above the memory cell selecting MISFET,
Two memory cell selecting MISs adjacent in the extending direction
It is electrically connected to one of the source and drain shared by the FET. The information storage capacitance element is similarly disposed above the memory cell selection MISFET, and is electrically connected to the other of the source and the drain.

[0003] Japanese Patent Application Laid-Open No. 7-7084 discloses a capacitor over bit line (Capacitor Over Bitline) structure in which an information storage capacitor is arranged above a bit line.
A RAM is disclosed. DRAM described in this publication
The lower electrode (storage electrode) of the information storage capacitor disposed above the bit line is formed in a cylindrical shape in order to compensate for the decrease in the storage charge (Cs) of the information storage capacitor accompanying the miniaturization of the memory cell. The capacitance insulating film and the upper electrode (plate electrode) are formed thereon.

[0004]

SUMMARY OF THE INVENTION The above prior art DRA
M uses the inner wall and outer wall of the lower electrode processed into a cylindrical shape as an effective area for securing the amount of accumulated charges. Therefore, the height of the cylinder increases as the memory cell becomes finer.

However, when the height of the cylinder is increased, the step between the region where the memory cell is formed and the peripheral circuit region is increased, and the process margin of photolithography when processing the wiring or connection hole formed thereover is increased. Decrease. For this reason, even if an insulating film of the same layer as the information storage capacitor is formed in the peripheral circuit region to eliminate the step, the aspect ratio of the insulating film opened in the insulating film on the peripheral circuit becomes large, and the processing step becomes large. The burden increases.

Even when the height of the cylinder is increased, when a silicon nitride film is used as the capacitance insulating film of the information storage capacitance element, the amount of accumulated charge cannot be reduced due to the low dielectric constant and the limit of the required film thickness. It is becoming difficult to secure.

The silicon nitride film requires a heat treatment at 850 ° C. or higher to reduce the leakage current. However, the memory cell selecting MI already formed before the heat treatment step is performed.
It adversely affects SFETs and the like, and is one of the causes of malfunctions and the like.

An object of the present invention is to provide a semiconductor integrated circuit device having an information storage capacitance element capable of securing a required amount of stored charge even when miniaturized, and a manufacturing technique therefor.

Another object of the present invention is to provide a structure of a semiconductor integrated circuit device capable of facilitating opening of a connection hole formed in a peripheral circuit region when a step between a memory cell array region and a peripheral circuit region is eliminated. And manufacturing technology.

It is another object of the present invention to provide a technique for reducing a leak current of an information storage capacitor and facilitating securing an amount of stored charge.

It is another object of the present invention to provide a structure and a manufacturing technique of a lower electrode constituting an information storage capacitor which contributes to reducing a leak current of the information storage capacitor.

It is another object of the present invention to provide a structure and a manufacturing technique of a capacitor insulating film constituting an information storage capacitor which contributes to reducing a leak current of the information storage capacitor.

Another object of the present invention is to provide a structure and a manufacturing technique of an upper electrode constituting an information storage capacitor which contributes to reducing a leak current of the information storage capacitor.

Another object of the present invention is to provide a technique capable of obtaining a highly reliable semiconductor integrated circuit device by securing a required amount of accumulated charge and lowering the temperature of the whole manufacturing process. is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a method of manufacturing a semiconductor integrated circuit device according to the present invention, a memory cell is constituted by a memory cell selecting MISFET and an information storage capacitor connected in series to the MISFET, and an opening is formed upward. A lower electrode made of a cylindrical polycrystalline silicon film, a capacitor insulating film formed on the surface of the lower electrode, and an information storage capacitor having an upper electrode formed opposite the lower electrode with the capacitor insulating film interposed therebetween. A method of manufacturing a semiconductor integrated circuit device having a DRAM arranged above a memory cell selecting MISFET, wherein (a) a first insulating film is deposited on the memory cell selecting MISFET formed on a main surface of a semiconductor substrate. Forming a groove by opening the first insulating film, and (b) forming a film on the first insulating film including the inside of the groove so that the amorphous silicon film containing impurities is not filled with the groove. Deposit on Extent, (c) depositing a second insulating film having a thickness such as grooves in the upper part of the amorphous silicon film is filled, a second insulating film and the first region is formed (d) the groove
Removing the amorphous silicon film on the insulating film to leave an amorphous silicon film only inside the trench;
(E) performing a first heat treatment to grow the amorphous silicon film in a solid phase and convert it to a polycrystalline silicon film; (f) a first insulating film and a groove in a gap between the groove and a groove adjacent thereto Forming a cylindrical lower electrode having an opening above, and (g) forming a capacitive insulating film on the surface of the lower electrode and performing a second heat treatment. Modifying the capacitance insulating film.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention is a method of manufacturing a semiconductor integrated circuit device having the same configuration as described above, wherein (a) a memory cell formed on a main surface of a semiconductor substrate. Depositing a first insulating film on the upper part of the selection MISFET and then forming a groove by opening the first insulating film; (b) an impurity is contained in the upper part of the first insulating film including the inside of the groove; (C) depositing a second insulating film having a thickness such that the trench is buried above the amorphous silicon film, and (d) trench. Removing the amorphous silicon film above the second insulating film and the first insulating film in the region where the is formed to leave an amorphous silicon film only inside the groove, and (e) forming the groove and the The first insulating film in the gap with the adjacent groove and the second insulating film inside the groove are removed. Exposing a cylindrical amorphous silicon film having an opening to the lower electrode, (f) performing a first heat treatment to solid-phase grow the amorphous silicon film, convert the amorphous silicon film into a polycrystalline silicon film, And (g) forming a capacitive insulating film on the surface of the lower electrode and performing a second heat treatment to modify the capacitive insulating film.

According to the method of manufacturing a semiconductor integrated circuit device described in (1) and (2), since the lower electrode is a polycrystalline silicon film formed by solid phase growth of an amorphous silicon film, The surface can be flattened, which is effective in preventing occurrence of a defective capacitor.

(3) In the case of the method of manufacturing a semiconductor integrated circuit device according to (2), after exposing a cylindrical amorphous silicon film having an opening above, The method may include a step of forming irregularities on the surface of the silicon film.

According to such a method of manufacturing a semiconductor integrated circuit device, in order to form irregularities on the surface, the surface area of the lower electrode is increased to easily secure the required amount of accumulated charge, and the height of the cylinder is reduced. It is possible.

(4) In the method of manufacturing a semiconductor integrated circuit device according to the above (3), before forming the irregularities on the surface of the cylindrical amorphous silicon film having the opening above, The method may include a step of cleaning the surface of the crystalline silicon film.

According to such a method of manufacturing a semiconductor integrated circuit device, since the surface of the amorphous silicon film is cleaned before forming the irregularities, nucleation of hemispherical silicon constituting the irregularities is inhibited. Therefore, it is possible to form uniform unevenness.

(5) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the amorphous silicon film is formed by a low-pressure CVD method using a gas containing at least monosilane (SiH ₄ ) as a source gas. is there.

According to such a method of manufacturing a semiconductor integrated circuit device, an amorphous silicon film can be formed in the trench with good step coverage, the surface area can be secured, and the structurally stable lower electrode can be formed. Can be formed.

(6) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the second insulating film and the amorphous silicon film may be removed by a CMP method or by etching the second insulating film. After exposing the first conductive film on the film,
This is performed by etching the conductive film.

According to such a method of manufacturing a semiconductor integrated circuit device, the tip of the cylindrical lower electrode can be flattened, and the tip does not become sharp as in the conventional dry etching method. In addition, there is no reduction in dielectric strength or increase in leakage current due to electric field concentration.

(7) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the first heat treatment is performed at a temperature equal to or higher than the second heat treatment.

According to such a method of manufacturing a semiconductor integrated circuit device, the lower electrode is not subjected to deformation or the like by the second heat treatment after depositing, for example, a tantalum oxide film serving as a lower electrode and a capacitor insulating film. The occurrence of thermal stress does not reduce the insulating property of the capacitive insulating film and increase the leakage current.

(8) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a memory cell is constituted by a memory cell selecting MISFET and an information storage capacitance element connected in series with the MISFET, and an opening is formed upward. A lower electrode made of a cylindrical polycrystalline silicon film, a capacitor insulating film formed on the surface of the lower electrode, and an information storage capacitor having an upper electrode formed opposite the lower electrode with the capacitor insulating film interposed therebetween. A method of manufacturing a semiconductor integrated circuit device having a DRAM disposed above a memory cell selecting MISFET, comprising: (a) forming an opening above a memory cell selecting MISFET formed on a main surface of a semiconductor substrate; (B) forming a silicon nitride film on the surface of the lower electrode, and (c) forming a tantalum oxide film on the silicon nitride film by CV.
The method includes a step of depositing by a method D, and a step of (d) forming a capacitive insulating film by performing a heat treatment on the tantalum oxide film to modify the tantalum oxide film.

According to such a method of manufacturing a semiconductor integrated circuit device, since the silicon nitride film is formed before the tantalum oxide film is deposited, a heat treatment is performed, for example, in an oxygen atmosphere when the tantalum oxide film is modified. However, it is necessary to prevent oxygen from entering the lower electrode, prevent the formation of a silicon oxide film at the interface between the lower electrode and the silicon nitride film, and prevent a substantial increase in the thickness of the capacitive insulating film. Can be.

(9) The silicon nitride film is at 600 ° C.
It can be formed by heat treatment in an ammonia (NH ₃ ) atmosphere at ８850 ° C. or by a low-pressure CVD method. When formed by the low-pressure CVD method, a uniform silicon nitride film is deposited without being affected by impurities of the lower electrode serving as a base, and abnormal silicon oxide is formed at the interface between the silicon nitride film and the lower electrode. Can be prevented.

(10) In the low-pressure CVD method, a gas containing at least dichlorosilane (SiH ₂ Cl ₂ ) and ammonia can be used as a source gas.

(11) The method of manufacturing a semiconductor integrated circuit device according to (8) may include a step of forming a silicon oxynitride film before depositing the tantalum oxide film.

According to such a method of manufacturing a semiconductor integrated circuit device, the silicon oxynitride film is formed instead of or in addition to the silicon nitride film. It is possible to more effectively prevent oxygen from entering the electrode. That is, since the silicon oxynitride film contains oxygen in advance, it is possible to prevent a reaction in which oxygen constituting the tantalum oxide film itself is extracted to the silicon oxynitride film.

(12) A method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to any one of the above (8) to (11), wherein the silicon nitride film or the silicon oxynitride film is used. Before the formation of the first electrode, a step of cleaning the surface of the lower electrode is included.

According to such a method of manufacturing a semiconductor integrated circuit device, since the surface of the lower electrode is cleaned, abnormal growth of the silicon nitride film or silicon oxynitride film is prevented, and the uniform thickness of the silicon nitride film or silicon oxynitride film is prevented. A silicon nitride film or a silicon oxynitride film can be formed. As a result, it is possible to more effectively prevent oxygen from entering the lower electrode during the modification of the tantalum oxide film.

(13) In the method of manufacturing a semiconductor integrated circuit device according to (12), the surface of the lower electrode is cleaned in the same manner as in a reaction chamber for forming a silicon nitride film or a silicon oxynitride film. Performing heat treatment in a hydrogen atmosphere in a reaction chamber or another reaction chamber connected to a reaction chamber in which a silicon nitride film or a silicon oxynitride film is formed in a transfer chamber in which a reduced pressure or an inert atmosphere can be formed; Can be performed.

According to such a method of manufacturing a semiconductor integrated circuit device, recontamination or oxidation of the surface of the cleaned lower electrode can be prevented.

(14) A method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a semiconductor integrated circuit device according to any one of (8) to (13), wherein the tantalum oxide film is deposited. , 450 ° C. or higher.

In the deposition of the tantalum oxide film, the film can be formed uniformly regardless of the size of the substrate on which the film is formed, the step coverage is good, and the deposition rate can be deposited with good reproducibility without depending on the substrate material. However, these conditions can be satisfied in an isothermal atmosphere of 450 ° C. or higher.

(15) The method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a semiconductor integrated circuit device according to any one of the above (8) to (14), wherein the heat treatment of the tantalum oxide film is performed. The tantalum oxide is applied so as to have a uniform crystal grain size.

Such uniformity of the crystal grain size can be realized by performing the heat treatment in an oxidizing atmosphere in a temperature range of 730 ° C. to 850 ° C.

The heat treatment converts the silicon nitride film into a film containing a silicon oxynitride film.

(16) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to any one of the above (8) to (15), wherein after the heat treatment of the tantalum oxide film, Further, the method includes a step of depositing a second tantalum oxide film by a CVD method and performing a heat treatment on the second tantalum oxide film.

According to such a method of manufacturing a semiconductor integrated circuit device, a plurality of tantalum oxide films can be formed. The effect of having a plurality of tantalum oxide films will be described later.

(17) The semiconductor integrated circuit device according to the present invention
A memory cell is composed of a memory cell selection MISFET and an information storage capacitor element connected in series with the memory cell selector, a cylindrical lower electrode having an opening above, and a capacitor insulating film formed on the surface of the lower electrode And an information storage capacitance element having an upper electrode formed opposite to the lower electrode with the capacitance insulating film interposed therebetween, wherein the information storage capacitance element is disposed above the memory cell selection MISFET.
A method for manufacturing a semiconductor integrated circuit device having an AM,
(A) M for memory cell selection formed on main surface of semiconductor substrate
Forming a lower electrode over the ISFET and forming a capacitive insulating film on at least the surface of the lower electrode; (b) depositing a titanium nitride film to be an upper electrode on the entire surface of the semiconductor substrate on which the capacitive insulating film has been formed; And a step of burying a recess formed by the cylindrical shape of the lower electrode to flatten the surface of the titanium nitride film on the lower electrode.

According to such a method of manufacturing a semiconductor integrated circuit device, since the recess formed by the cylindrical shape of the lower electrode is buried by the deposition of the titanium nitride film, when the recess is formed on the upper surface of the upper electrode, In comparison, voids and the like do not occur in the insulating film or the like embedded in the recess, and the reliability of the semiconductor integrated circuit device can be improved.

(18) A method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to (17), wherein the memory cell is formed before the deposition of the titanium nitride film. A connection hole is opened in a peripheral circuit region around the memory cell array region, a titanium nitride film is deposited on the entire surface of the semiconductor substrate including the connection hole, and the titanium nitride film is patterned to form an upper electrode so as to cover the memory cell array region. A plug or a wiring for filling the connection hole is formed at the same time as the formation.

According to such a method of manufacturing a semiconductor integrated circuit device, a plug or a wiring is formed in a peripheral circuit region to eliminate a step between a memory cell array region and a peripheral circuit region. It is possible to easily open the connection hole to the like.

(19) The semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to the above (17) or (18), wherein the titanium nitride film is deposited only by the CVD method. The first titanium nitride film can be deposited by any one of the first method and the second method of depositing a second titanium nitride film by sputtering after the deposition of the first titanium nitride film by CVD.

Since the titanium nitride film formed by the CVD method can be formed with good step coverage, the trench can be filled well, and the first titanium nitride film formed by the CVD method and the second titanium nitride film formed by the sputtering method can be formed. When combined, the intrinsic stress of the titanium nitride film can be reduced.

(20) The titanium nitride film formed by the CVD method can be deposited in a temperature range of 430 ° C. to 500 ° C. using a gas containing at least titanium tetrachloride and ammonia as a source gas.

(21) A method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a semiconductor integrated circuit device according to any one of the above (17) to (20), wherein the method comprises the steps of: No heat treatment exceeding 550 ° C.

According to such a method of manufacturing a semiconductor integrated circuit device, when heat treatment at 550 ° C. or more is performed, the intrinsic stress of the deposited titanium nitride film increases, and the leakage current of the information storage capacitor element decreases. Although there is a possibility of increase, it is possible to suppress such deterioration of the information storage capacitor.

(22) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a memory cell is constituted by a memory cell selecting MISFET and an information storage capacitor connected in series with the MISFET, and an opening is formed upward. A method of manufacturing a semiconductor integrated circuit device having a DRAM in which an information storage capacitor having a cylindrical lower electrode is disposed above a MISFET for selecting a memory cell, comprising: (a) forming on a main surface of a semiconductor substrate; A first insulating film is deposited on the memory cell selecting MISFET, a second insulating film having an etching rate different from that of the first insulating film is deposited, and then the first insulating film and the second insulating film are opened to form a groove. (B) depositing a first conductive film constituting a lower electrode of the information storage capacitor on the second insulating film including the inside of the groove so as to fill the groove, and (c) ) Groove on top of first conductive film Depositing a third insulating film having a thickness so as to fill the trench, and (d) removing the third conductive film in a region where the groove is formed and the first conductive film above the second insulating film, thereby forming the inside of the groove. (E) etching the second insulating film in the gap between the groove and the groove adjacent thereto and the third insulating film inside the groove using the first insulating film as an etching stopper; And forming a cylindrical lower electrode having an opening.

According to such a method of manufacturing a semiconductor integrated circuit device, the second insulating film has a different etching rate from that of the first insulating film.
Since the insulating film is deposited, the first insulating film can be used as a stopper film for etching the second insulating film and the third insulating film.

(23) The semiconductor integrated circuit device according to the present invention
A memory cell is composed of a memory cell selecting MISFET and an information storage capacitor connected in series with the MISFET, and a lower electrode made of a cylindrical polycrystalline silicon film having an opening above, and a lower electrode formed on the surface of the lower electrode. An information storage capacitor having a formed capacitor insulating film and an upper electrode formed to face the lower electrode with the capacitor insulating film interposed therebetween is used as a memory cell selecting MISF.
A semiconductor integrated circuit device having a DRAM disposed above an ET, wherein an upper end of a lower electrode does not have a sharp tip.

Such a semiconductor integrated circuit device can be manufactured by the method for manufacturing a semiconductor integrated circuit device described in (6) above, and it is possible to suppress a decrease in dielectric strength or an increase in leak current due to electric field concentration. it can.

(24) Further, in the semiconductor integrated circuit device of the present invention, a memory cell is constituted by a memory cell selecting MISFET and an information storage capacitor connected in series to the MISFET.
A lower electrode made of a cylindrical polycrystalline silicon film having an opening above; a capacitor insulating film formed on the surface of the lower electrode; and an upper electrode formed opposite the lower electrode with the capacitor insulating film interposed therebetween. The capacitance element for information storage is changed to M for memory cell selection.
In a semiconductor integrated circuit device having a DRAM disposed above an ISFET, the capacitance insulating film includes a silicon nitride film or a silicon oxynitride film, and a tantalum oxide film.

Such a semiconductor integrated circuit device can be manufactured by the method for manufacturing a semiconductor integrated circuit device described in (8) above, has no silicon oxide film on the surface of the lower electrode, and has a substantially capacitance insulation. An increase in the thickness of the film can be prevented, and the amount of charge stored in the information storage capacitor can be increased.

(25) The thickness of the silicon nitride film is 5
nm or less, and the thickness of the silicon oxynitride film is 3 to 4.5 n.
m, and the thickness of the tantalum oxide film is 10 to 20 nm.
In the range.

(26) The tantalum oxide film may have a single layer or a plurality of layers.

According to such a semiconductor integrated circuit device,
The leakage current of the information storage capacitor can be reduced by improving the insulating property of the capacitor insulating film.

(27) The average grain size of the crystals constituting the tantalum oxide film can be set to 1.5 μm or less, and the grain size of the crystals can be made substantially uniform.

According to such a semiconductor integrated circuit device,
The leakage current of the information storage capacitor can be reduced by improving the insulating property of the capacitor insulating film.

(28) The semiconductor integrated circuit device according to the present invention
A memory cell is composed of a memory cell selecting MISFET and an information storage capacitor connected in series with the MISFET, and a lower electrode made of a cylindrical polycrystalline silicon film having an opening above, and a lower electrode formed on the surface of the lower electrode. An information storage capacitor having a formed capacitor insulating film and an upper electrode formed to face the lower electrode with the capacitor insulating film interposed therebetween is used as a memory cell selecting MISF.
In a semiconductor integrated circuit device having a DRAM disposed above an ET, an upper electrode includes a titanium nitride film formed by a CVD method, and has an intrinsic stress of less than 1 Gpa.

Such a semiconductor integrated circuit device can be manufactured by the method for manufacturing a semiconductor integrated circuit device described in the above (19) to (21), and the stress of the upper electrode affects the insulating property of the capacitive insulating film. , The leak current of the information storage capacitor can be reduced.

(29) In the information storage capacitor, when the upper electrode side is under a negative bias condition relative to the lower electrode side, the current density flowing between the upper electrode and the lower electrode is 10 nA / the absolute value of the bias voltage to the cm ² is
It has characteristics of 1.5 V or more.

Such a semiconductor integrated circuit device can be manufactured by the above-described method for manufacturing a semiconductor integrated circuit device. Thus, the leakage current of the information storage capacitor can be reduced, and the reliability of the semiconductor integrated circuit device can be improved.

(30) An apparatus for manufacturing a semiconductor integrated circuit device according to the present invention includes a first means for forming a silicon nitride film or a silicon oxynitride film, a second means for depositing a tantalum oxide film, and an oxidizing atmosphere. A third means for performing heat treatment at
A fourth means for depositing a titanium nitride film by the VD method, wherein the first, second, third and fourth means are provided in the same reaction chamber. , A first, a second, a third and a fourth means, each in a separate reaction chamber, the separate reaction chambers being connected by a transfer chamber which can be kept under reduced pressure or inert atmosphere. Configuration.

According to such a semiconductor integrated circuit device manufacturing apparatus, formation of a silicon nitride film or a silicon oxynitride film, deposition of a tantalum oxide film, heat treatment of the tantalum oxide film, and deposition of a titanium nitride film are performed in a clean atmosphere. As a result, the amount of charge stored in the information storage capacitor can be increased, and the leakage current can be reduced.

(31) The apparatus for manufacturing a semiconductor integrated circuit device may further include fifth means for performing a heat treatment in a hydrogen atmosphere. In such a case, the fifth means is provided in all stages of the first means to clean the surface of the lower electrode on which the silicon nitride film or the silicon oxynitride film is to be formed, thereby providing a highly reliable semiconductor integrated circuit. The device can be manufactured.

[0074]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM of this embodiment is formed.
As shown, a semiconductor chip 1 made of single crystal silicon
X direction (long side direction of semiconductor chip 1A) on the main surface of A
And a large number of memory arrays MARY are arranged in a matrix along the Y direction (the short side direction of the semiconductor chip 1A). Memory arrays M adjacent to each other along the X direction
A sense amplifier SA is arranged between ARY. A word driver W is provided at the center of the main surface of the semiconductor chip 1A.
D, control circuits such as data line selection circuits, input / output circuits,
Bonding pads and the like are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM. As shown, the memory array of this DRAM (MA
RY) includes a plurality of word lines W arranged in a matrix.
L (WLn-1, WLn, WLn + 1...), A plurality of bit lines BL, and a plurality of memory cells (MC) arranged at their intersections. One memory cell for storing one bit of information is composed of one information storage capacitor C
And one memory cell selecting MI connected in series
SFET Qs. M for memory cell selection
One of a source and a drain of the ISFET Qs is electrically connected to the information storage capacitor C, and the other is a bit line BL.
Is electrically connected to One end of the word line WL is connected to a word driver WD, and one end of the bit line BL is
It is connected to the sense amplifier SA.

Next, a method of manufacturing the DRAM of the present embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 3, a p-type semiconductor substrate 1 having a specific resistance of about 10 Ωcm is wet-oxidized at about 850 ° C. to form a thin silicon oxide film 2 having a thickness of about 10 nm on its surface. CV is formed on the silicon oxide film 2
A silicon nitride film 3 having a thickness of about 140 nm is deposited by a D (Chemical Vapor Deposition) method. Silicon oxide film 2
Is formed to alleviate the stress applied to the substrate when sintering (burning) a silicon oxide film embedded in the element isolation groove in a later step. Since the silicon nitride film 3 has the property of being hardly oxidized, it is used as a mask for preventing the oxidation of the substrate surface below (the active region).

Next, as shown in FIG. 4, the silicon nitride film 3, the silicon oxide film 2 and the semiconductor substrate 1 are dry-etched using the photoresist film 4 as a mask, so that the semiconductor substrate 1 in the element isolation region is deeply etched. 300-400
A groove 5a of about nm is formed. In order to form the groove 5a, the silicon nitride film 3 is dry-etched using the photoresist film 4 as a mask, the photoresist film 4 is removed, and then the silicon oxide film 2 and the semiconductor substrate are etched using the silicon nitride film 3 as a mask. 1 may be dry-etched.

Next, after removing the photoresist film 4,
As shown in FIG. 5, in order to remove a damaged layer formed on the inner wall of the groove 5a by the above-described etching, the semiconductor substrate 1 is wet-oxidized at about 850 to 900 ° C. and the inner wall of the groove 5a has a film thickness of about 10 nm. A thin silicon oxide film 6 is formed.

Next, as shown in FIG. 6, after a silicon oxide film 7 having a thickness of about 300 to 400 nm is deposited on the semiconductor substrate 1, the semiconductor substrate 1 is dry-oxidized at about 1000 ° C. (Sintering) for improving the film quality of the silicon oxide film 7 embedded in the substrate. The silicon oxide film 7 is deposited by, for example, a thermal CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 7, after a silicon nitride film 8 having a thickness of about 140 nm is deposited on the silicon oxide film 7 by the CVD method, the photoresist film 9 is masked as shown in FIG. Then, the silicon nitride film 8 is dry-etched to leave the silicon nitride film 8 only on the upper portion of the groove 5a having a relatively large area such as the boundary between the memory array and the peripheral circuit. When the silicon nitride film 8 remaining on the groove 5a is planarized by polishing the silicon oxide film 7 by a CMP method in the next step, the silicon oxide film 7 inside the groove 5a having a relatively large area is removed. It is formed in order to prevent a phenomenon (dishing) that is polished deeper than the silicon oxide film 7 inside the groove 5a having a relatively small area.

Next, after removing the photoresist film 9,
As shown in FIG. 9, the element isolation groove 5 is formed by polishing the silicon oxide film 7 by a CMP method using the silicon nitride films 3 and 8 as stoppers and leaving the silicon oxide film 7 inside the groove 5a.

Next, after removing the silicon nitride films 3 and 8 by wet etching using hot phosphoric acid, as shown in FIG. 10, an n-type semiconductor substrate 1 in a region (memory array) where a memory cell is to be formed is formed. An n-type semiconductor region 10 is formed by ion-implanting an impurity, for example, P (phosphorus), and a p-type impurity, for example, B (boron) is added to a part of the memory array and peripheral circuits (a region for forming an n-channel MISFET). The p-type well 11 is formed by ion implantation, and n is formed in another part of the peripheral circuit (the region where the p-channel MISFET is formed).
An n-type well 12 is formed by ion implantation of a type impurity, for example, P (phosphorus). Subsequent to the ion implantation, impurities for adjusting the threshold voltage of the MISFET, for example, BF ₂ (boron fluoride) are ion-implanted into the p-type well 11 and the n-type well 12. The n-type semiconductor region 10 is formed to prevent noise from entering the p-type well 11 of the memory array from the input / output circuit and the like through the semiconductor substrate 1.

Next, the p-type well 11 and the n-type well 1
After removing the silicon oxide film 2 on each surface of the semiconductor substrate 1 using a HF (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is wet-oxidized at about 850 ° C. to form a p-type well 11 and an n-type well 1.
Then, a clean gate oxide film 13 having a thickness of about 7 nm is formed on each surface of No. 2.

Although not particularly limited, after the gate oxide film 13 is formed, the semiconductor substrate 1 is subjected to a heat treatment in an NO (nitrogen oxide) atmosphere or an N ₂ O (nitrogen oxide) atmosphere to form the gate oxide film. Nitrogen may be segregated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 (oxynitriding treatment). When the thickness of the gate oxide film 13 is reduced to about 7 nm, distortion generated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 due to a difference in thermal expansion coefficient becomes apparent, and hot carriers are generated. Nitrogen segregated at the interface with the semiconductor substrate 1 relaxes this distortion.
The above oxynitriding process can improve the reliability of the ultra-thin gate oxide film 13.

Next, as shown in FIG. 11, gate electrodes 14A, 14B and 14C are formed on the gate oxide film 13. The gate electrode 14A is provided with a memory cell selecting MISF.
It forms a part of the ET, and is used as a word line WL in a region other than the active region. The width of the gate electrode 14A (word line WL), that is, the gate length is the minimum dimension (for example, within an allowable range) in which the short channel effect of the memory cell selecting MISFET can be suppressed and the threshold voltage can be secured to a certain value or more. (About 0.24 μm). The distance between the adjacent gate electrodes 14A (word lines WL) is the minimum dimension (for example, 0.2) determined by the resolution limit of photolithography.
2 μm). The gate electrode 14B and the gate electrode 14C constitute each part of the n-channel MISFET and the p-channel MISFET of the peripheral circuit.

For the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C, a polycrystalline silicon film having a thickness of about 70 nm doped with an n-type impurity such as P (phosphorus) is formed on the semiconductor substrate 1 by the CVD method. Then, a WN (tungsten nitride) film having a thickness of about 50 nm and a W film having a thickness of about 100 nm are deposited thereon by sputtering, and a silicon nitride film 15 having a thickness of about 150 nm is further deposited thereon. After deposition by the CVD method, these films are formed by patterning these films using the photoresist film 16 as a mask. The WN film functions as a barrier layer that prevents the W film and the polycrystalline silicon film from reacting during the high-temperature heat treatment to form a high-resistance silicide layer at the interface between them. As the barrier layer, a TiN (titanium nitride) film or the like can be used in addition to the WN film.

When a part of the gate electrode 14A (word line WL) is made of low-resistance metal (W), its sheet resistance can be reduced to about 2 to 2.5 Ω / □, so that the word line delay is reduced. Can be reduced. Also, the gate electrode 1
Since the word line delay can be reduced without backing 4 (word line WL) with an Al wiring or the like, the number of wiring layers formed above the memory cells can be reduced by one.

Next, after removing the photoresist film 16, the semiconductor substrate 1 is etched using an etching solution such as hydrofluoric acid.
Dry etching residues and photoresist residues remaining on the surface of the substrate are removed. When this wet etching is performed, the gate oxide film 13 in a region other than the region under the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C is formed.
At the same time that the gate oxide film 1 under the gate sidewall is removed.
3 is also isotropically etched and an undercut occurs, so that the breakdown voltage of the gate oxide film 13 is reduced as it is. Therefore, the film quality of the shaved gate oxide film 13 is improved by wet oxidizing the semiconductor substrate 1 at about 900 ° C.

Next, as shown in FIG.
A p ^- type semiconductor region 17 is formed in the n-type well 12 on both sides of the gate electrode 14C by ion implantation of a p-type impurity, for example, B (boron) into the gate electrode 14C. In addition, the p-type well 11 has n
An n ^- type semiconductor region 18 is formed in the p-type well 11 on both sides of the gate electrode 14B by ion-implanting a p-type impurity, for example, P (phosphorus), and an n ^- type semiconductor region 19 is formed in the p-type well 11 on both sides of the gate electrode 14A. To form As a result, the memory cell selecting MISFET Qs is formed in the memory array.

Next, as shown in FIG.
After a silicon nitride film 20 having a thickness of about 50 to 100 nm is deposited thereon by the CVD method, the silicon nitride film 20 of the memory array is covered with a photoresist film 21 as shown in FIG. Is anisotropically etched to form sidewall spacers 20a on the side walls of the gate electrodes 14B and 14C. In this etching, an etching gas that increases the etching rate of the silicon nitride film 20 with respect to the silicon oxide film is used in order to minimize the shaving amount of the silicon oxide film 7 buried in the gate oxide film 13 and the element isolation trench 5. Use to do.
The silicon nitride film 1 on the gate electrodes 14B and 14C
In order to minimize the shaving amount of No. 5, the amount of over-etching is kept to a necessary minimum.

Next, after removing the photoresist film 21, as shown in FIG. 15, the n-type well 1 in the peripheral circuit region is formed.
2 is ion-implanted with a p-type impurity, for example, B (boron) to form ap ⁺ -type semiconductor region 22 of a p-channel MISFET.
(Source, drain) are formed, and an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 11 in the peripheral circuit region to form an n ⁺ -type semiconductor region 23 (source, drain) of the n-channel MISFET. I do. This allows
A p-channel MISFET Qp and an n-channel MISFET Qn having an LDD (Lightly Doped Drain) structure are formed in the peripheral circuit region.

Next, as shown in FIG.
After spin coating an SOG (spin-on-glass) film 24 having a thickness of about 300 nm on the semiconductor substrate 1,
The heat treatment is performed for about a minute, and the SOG film 24 is sintered (sintered).

Next, as shown in FIG.
After a silicon oxide film 25 having a thickness of about 600 nm is deposited on the upper surface of the silicon oxide film 25, the silicon oxide film 25 is polished by a CMP method to flatten the surface. The silicon oxide film 25 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

As described above, in the present embodiment, the gate electrode 14A (word line WL) and the gate electrodes 14B, 1
SOG film 24 with good flatness even immediately after film formation on top of 4C
Is applied, and a silicon oxide film 2 deposited on the
5 is flattened by a CMP method. Thereby, the gate electrode 1
4A (word line WL) improves the gap fill property of a minute gap between the gate electrodes 14A (word line WL).
L) and planarization of the insulating film on the gate electrodes 14B and 14C can be realized.

Next, as shown in FIG. 18, a silicon oxide film 26 having a thickness of about 100 nm is formed on the silicon oxide film 25.
Is deposited. The silicon oxide film 26 is deposited in order to repair fine scratches on the surface of the silicon oxide film 25 generated when the silicon oxide film 25 is polished by the CMP method. Silicon oxide film 2
6 is deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. On top of the silicon oxide film 25, a PSG (Phospho Silicate Glas
s) A film or the like may be deposited.

Next, as shown in FIG. 19, the silicon oxide films 26, 25 on the n-type semiconductor region 19 (source, drain) of the memory cell selecting MISFET Qs are dry-etched using the photoresist film 27 as a mask. The SOG film 24 is removed. This etching is performed under such a condition that the etching rates of the silicon oxide films 26 and 25 and the SOG film 24 with respect to the silicon nitride film 20 are increased, and the silicon nitride film covering the n-type semiconductor region 19 and the upper part of the element isolation trench 5 is formed. 20 is not completely removed.

Subsequently, as shown in FIG. 20, the n-type semiconductor region 19 of the memory cell selecting MISFET Qs is dry-etched using the photoresist film 27 as a mask.
By removing the silicon nitride film 20 and the gate oxide film 13 above the (source, drain), a contact hole 28 is formed in one upper part of the n-type semiconductor region 19 (source, drain) and in the other upper part. Contact hole 2
9 is formed.

This etching is performed under such conditions that the etching rate of the silicon nitride film 15 with respect to the silicon oxide film (the gate oxide film 13 and the silicon oxide film 7 in the element isolation trench 5) is increased. The element isolation groove 5 is prevented from being cut deeply. This etching is performed under such conditions that the silicon nitride film 20 is anisotropically etched, and the gate electrode 14A (word line W
The silicon nitride film 20 is left on the side wall of L). As a result, the contact holes 28 and 29 having a fine diameter smaller than the resolution limit of photolithography are formed in the gate electrode 1.
4A (word line WL) is formed in a self-aligned manner.
In order to form the contact holes 28 and 29 in a self-aligned manner with respect to the gate electrode 14A (word line WL), the silicon nitride film 20 is anisotropically etched in advance to form a sidewall on the side wall of the gate electrode 14A (word line WL). A spacer may be formed.

Next, after removing the photoresist film 27, dry etching residues or photoresist residues on the substrate surface exposed at the bottoms of the contact holes 28 and 29 are etched using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. And so on. At that time, the contact hole 28,
The SOG film 24 exposed on the side wall of the S.sub.29 is also exposed to the etching solution. However, the SOG film 24 has a reduced etching rate with respect to a hydrofluoric acid-based etching solution by the above-described sintering at about 800.degree. The sidewalls of the contact holes 28 and 29 are not largely undercut by the etching process. As a result, it is possible to reliably prevent a short circuit between plugs embedded in the contact holes 28 and 29 in the next step.

Next, as shown in FIG. 21, plugs 30 are formed inside the contact holes 28 and 29. The plug 30 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 26 by CVD.
After the deposition by the method, the polycrystalline silicon film is polished by the CMP method and is formed by being left inside the contact holes 28 and 29.

Next, as shown in FIG. 22, a silicon oxide film 31 having a thickness of about 200 nm is formed on the silicon oxide film 26.
Is deposited, the semiconductor substrate 1 is heat-treated at about 800 ° C. The silicon oxide film 31 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. By this heat treatment,
An n-type impurity in the polycrystalline silicon film forming the plug 30 is supplied from the bottom of the contact holes 28 and 29 to the n-type semiconductor region 19 (source,
Drain) and the resistance of the n-type semiconductor region 19 is reduced.

Next, as shown in FIG. 23, the surface of the plug 30 is exposed by removing the silicon oxide film 31 above the contact hole 28 by dry etching using the photoresist film 32 as a mask. Next, after removing the photoresist film 32, as shown in FIG. 24, the silicon oxide films 31, 26, 25 and the SOG film 24 in the peripheral circuit region are dry-etched using the photoresist film 33 as a mask.
By removing the gate oxide film 13 and contact holes 34 and 35 above the n ⁺ -type semiconductor region 23 (source and drain) of the n-channel MISFET Qn, the p ⁺ -type semiconductor region 22 of the p-channel MISFET Qp Contact holes 36 and 37 are formed above (source, drain).

Next, after removing the photoresist film 33, as shown in FIG. 25, the bit lines BL and the first layer wirings 38 and 39 of the peripheral circuit are formed on the silicon oxide film 31. In order to form the bit line BL and the first layer wirings 38 and 39, first, a film thickness 5
A Ti film of about 0 nm is deposited by a sputtering method, and the semiconductor substrate 1 is heat-treated at about 800 ° C. Next, a TiN film having a thickness of about 50 nm is deposited on the Ti film by a sputtering method, and a W film having a thickness of about 150 nm and a silicon nitride film 40 having a thickness of about 200 nm are further deposited thereon by a CVD method. These films are patterned using the photoresist film 41 as a mask.

After a Ti film is deposited on the silicon oxide film 31, the semiconductor substrate 1 is subjected to a heat treatment at about 800 ° C., whereby the Ti film reacts with the underlying Si to form an n-channel type M.
Surface of n ⁺ -type semiconductor region 23 (source, drain) of ISFET Qn, surface of p ⁺ -type semiconductor region 22 (source, drain) of p-channel MISFET Qp, and plug 3
0 surface and low resistance TiSi ₂ (titanium silicide)
Layer 42 is formed. Thereby, the n ⁺ type semiconductor region 2
3. The contact resistance of the wiring (bit line BL, first layer wirings 38 and 39) connected to p ⁺ type semiconductor region 22 and plug 30 can be reduced. In addition, bit line B
By configuring L with a W film / TiN film / Ti film, the sheet resistance can be reduced to 2 Ω / □ or less, so that the information reading speed and the writing speed can be improved, and the bit line BL and the periphery can be improved. Since the first layer wirings 38 and 39 of the circuit can be formed simultaneously in one step, the DRAM manufacturing steps can be shortened.
Further, when the first layer wirings (38, 39) of the peripheral circuit are formed of the same layer as the bit line BL, the peripheral wiring is more peripheral than the case where the first layer wiring is formed of the upper layer Al wiring of the memory cell. MISFET (n-channel MISFETQ)
Since the aspect ratio of the contact holes (34 to 37) connecting the n-channel and p-channel MISFETs Qp) to the first layer wiring is reduced, the connection reliability of the first layer wiring is improved.

The bit line BL is used to reduce the parasitic capacitance formed between the bit line BL and the adjacent bit line BL as much as possible to improve the information reading speed and the writing speed.
The gap is formed so as to be longer than the width. The interval between the bit lines BL is, for example, about 0.24 μm, and the width thereof is, for example, about 0.22 μm.

Next, after removing the photoresist film 41, as shown in FIG. 26, sidewall spacers 43 are formed on the side walls of the bit lines BL and the side walls of the first layer wirings 38 and 39.
To form The side wall spacer 43 is formed by depositing a silicon nitride film on the bit line BL and the first layer wirings 38 and 39 by the CVD method, and then anisotropically etching the silicon nitride film.

Next, as shown in FIG.
Then, an SOG film 44 having a thickness of about 300 nm is spin-coated on the first layer wirings 38 and 39. Next, the semiconductor substrate 1 is heat-treated at 800 ° C. for about 1 minute to sinter (bake) the SOG film 44.

Since the SOG film 44 has a higher reflow property than the BPSG film and is excellent in the gap fill property between fine wirings, the gap between the bit lines BL miniaturized to the resolution limit of photolithography is obtained. Can be satisfactorily embedded. In addition, since the SOG film 44 can obtain high reflow properties without performing a high-temperature and long-time heat treatment required for the BPSG film, the source and drain of the memory cell selection MISFET Qs formed under the bit line BL are formed. And MISFETs for peripheral circuits (n-channel MISFE
TQn, the p-channel type MISFET Qp) can suppress the thermal diffusion of the impurities contained in the source and drain, and can achieve a shallow junction. Further, since the deterioration of the metal (W film) forming the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C can be suppressed, the performance of the MISFET forming the memory cell and the peripheral circuit of the DRAM can be improved. Can be. Further, a Ti film, a TiN film, and a W film constituting the bit line BL and the first layer wirings 38 and 39 are formed.
Wiring resistance can be reduced by suppressing film deterioration.

Next, as shown in FIG.
After a silicon oxide film 45 having a thickness of about 600 nm is deposited on the upper surface of the substrate, the silicon oxide film 45 is polished by a CMP method to flatten the surface. The silicon oxide film 45 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

As described above, in the present embodiment, the SOG film 44 having a high reflow property is applied on the bit line BL and the first layer wirings 38 and 39, and the silicon oxide film 45 deposited on the SOG film 45 is further subjected to the CMP. Flattening by the method. Thereby, the gap fill property of the minute gap between the bit lines BL is improved, and the bit lines BL and the first layer wiring 3 are formed.
The flattening of the insulating film on the upper part of 8, 39 can be realized. Further, since heat treatment at a high temperature for a long time is not performed, deterioration of characteristics of the MISFETs constituting the memory cell and the peripheral circuit can be prevented and high performance can be realized.
The resistance of the bit line BL and the first layer wirings 38 and 39 can be reduced.

Next, as shown in FIG. 29, a silicon oxide film 46 having a thickness of about 100 nm is formed on the silicon oxide film 45.
Is deposited. The silicon oxide film 46 is deposited to repair fine scratches on the surface of the silicon oxide film 45 generated when the silicon oxide film 45 is polished by the CMP method. Silicon oxide film 4
6 is deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 30, the silicon oxide films 46 and 45 over the contact holes 29 are removed by dry etching using the photoresist film 47 as a mask.
After removing the film 44 and the silicon oxide film 31, the plug 30
Is formed to reach the surface of the substrate. This etching is performed on the silicon oxide films 46, 45, 31 and SO
The etching is performed under such a condition that the etching rate of the silicon nitride film with respect to the G film 44 becomes small.
To prevent the silicon nitride film 40 and the sidewall spacers 43 on the upper portion from being etched deeply. As a result, the through hole 48 is formed in self alignment with the bit line BL.

Next, after the photoresist film 47 is removed, a dry etching residue or a photoresist residue on the surface of the plug 30 exposed at the bottom of the through hole 48 is etched using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. And so on. At this time, the SOG film 44 exposed on the side wall of the through hole 48 is also exposed to the etching solution.
Since the etching rate of the OG film 44 with respect to the hydrofluoric acid-based etchant is reduced by the sintering at about 800 ° C., the side wall of the through hole 48 is not largely undercut by the wet etching process. Accordingly, a short circuit between the plug buried in the through hole 48 and the bit line BL in the next step can be reliably prevented. Also, since the plug and the bit line BL can be sufficiently separated from each other,
An increase in the parasitic capacitance of the bit line BL can be suppressed.

Next, as shown in FIG. 31, a plug 49 is formed inside the through hole 48. The plug 49 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 46 by a CVD method, and then etching back the polycrystalline silicon film to form a through hole 48. It is formed by leaving it inside.

Next, as shown in FIG. 32, a silicon nitride film 51 having a thickness of about 100 to 200 nm is deposited on the silicon oxide film 46 by the CVD method.
The silicon nitride film 51 in the peripheral circuit region is removed by dry etching using 2 as a mask. The silicon nitride film 51 remaining in the memory array is used as an etching stopper when etching a silicon oxide film between the lower electrodes in a step of forming a lower electrode of the information storage capacitor element described later. Therefore, the silicon nitride film 51 is made of a silicon nitride material whose etching rate is lower than the etching rate of the silicon oxide film between the lower electrodes described later.

Next, after removing the photoresist film 52, a silicon oxide film 53 having a thickness of about 0.8 μm is deposited on the silicon nitride film 51 as shown in FIG.
By removing the silicon oxide film 53 and the silicon nitride film 51 by dry etching using the photoresist film 54 as a mask, a groove 55 is formed above the through hole 48 in which the plug 49 is embedded. Silicon oxide film 53
Is, for example, ozone (O ₃ ) and tetraethoxysilane (T
EOS) is deposited by a plasma CVD method using a source gas. At this time, a strip-shaped long groove 55a surrounding the memory array may be formed around the memory array at the same time.
FIG. 34 shows a groove 55 formed above the through hole 48.
FIG. 9 is a plan view showing an example of a pattern of a strip-shaped long groove 55a surrounding a memory array.

Next, after removing the photoresist film 54, as shown in FIG. 35, an upper portion of the silicon oxide film 53 is doped with an n-type impurity (for example, P (phosphorus)) to a thickness of 70 nm.
An amorphous silicon film 56 of about nm is deposited by a CVD method.
The amorphous silicon film 56 will be a lower electrode of the information storage capacitor later. The amorphous silicon film 56 is converted into a polycrystalline silicon film to be a lower electrode as described later. However, as compared with a film deposited as a polycrystalline silicon film from the beginning, the amorphous silicon film is changed from a polycrystalline silicon film to a polycrystalline silicon film. When converted, the surface can be made extremely flat, and generation of defective capacitors can be suppressed.

The amorphous silicon film 56 is deposited by, for example, monosilane (SiH ₄ ) and phosphine (P
H ₃ ) can be performed by a low-pressure CVD method using a gas containing H ₃ ) as a source gas. Amorphous silicon film using monosilane as a source gas is a film with excellent step coverage,
The amorphous silicon film 56 can be formed in the trench 55 with good coverage. As a result, the thickness of the lower portion of the amorphous silicon film 56 is not reduced, and the mechanical strength of the lower electrode formed thereby is improved, so that the lower electrode can be prevented from collapsing.

Next, as shown in FIG. 36, a silicon oxide film 57 is deposited on the amorphous silicon film 56 so as to completely fill the groove 55 and the long groove 55a (for example, about 400 nm). That is, the silicon oxide film 57 is
The film thickness is set to １ ／ or more of the width of No. 5. Silicon oxide film 57
Is, for example, ozone (O ₃ ) and tetraethoxysilane (T
EOS) can be deposited by a plasma CVD method using a source gas, but it can also be an SOG film.

Next, as shown in FIG. 37, the silicon oxide film 57 and the amorphous silicon film 56 on the silicon oxide film 53 are polished and removed by using a CMP (Chemical Mechanical Polishing) method, and the groove 55 and the long groove 55a are removed. The amorphous silicon film 56 is left inside (the inner wall and the bottom). At this time, the silicon oxide film 57 that has not been polished and removed also remains inside the groove 55 and the long groove 55a.

As described above, the CMP (Chemical Mechanical
Since the silicon oxide film 57 and the amorphous silicon film 56 are polished and removed using the Polishing method, the upper end of the amorphous silicon film 56 can be flattened. In the case where a polycrystalline silicon film is deposited on a conventional cylindrical insulator support and is etched by dry etching to form a lower electrode stand on the side wall of the cylindrical insulator support, the lower electrode stand is formed. Has a sharp tip shape,
In some cases, the electric field concentration easily occurs, resulting in a decrease in the withstand voltage. However, when the CMP method is used as described above,
The upper end of the amorphous silicon film 56 becomes flat, and electric field concentration hardly occurs. Therefore, the leakage current of the capacitor can be reduced, and a highly reliable DRAM can be obtained.

Next, after cleaning the surface of the semiconductor substrate 1,
For example, heat treatment at 800 ° C. for 3 minutes is performed in a nitrogen atmosphere. By this heat treatment, the amorphous silicon film 56 is solid-phase grown and converted into a polycrystalline silicon film 56b. At this stage, the amorphous silicon film 56 is converted into the polycrystalline silicon film 56b if the nitriding process described later is performed in the state of the amorphous silicon film 56 during the formation of the silicon nitride film. At the same time, the crystallization of the amorphous silicon film 56 into the polycrystalline silicon film simultaneously proceeds, and distortion of the silicon nitride film occurs. In extreme cases, cracks occur in the silicon nitride film. In such a state, when a heat treatment of the tantalum oxide film described later is performed in an oxygen atmosphere, the oxidizing agent diffused in the tantalum oxide passes through the crack portion, and the polycrystalline silicon film in the crack portion causes abnormal oxidation. As a result, the tantalum oxide film is locally lifted. In such a state, the tantalum oxide film itself is distorted, does not function as a good insulating film, and increases the leakage current. In order to prevent such a problem from occurring, it is necessary to convert the amorphous silicon film 56 into a polycrystalline silicon film 56b before forming the silicon nitride film. The heat treatment (800 ° C., 3 minutes) at this stage is performed at a temperature higher than or equal to the heat treatment temperature for crystallization of the tantalum oxide film described later. Thus, thermal stress in a subsequent heat treatment can be reduced and a highly reliable capacitor can be formed.

Next, as shown in FIG. 38, the silicon oxide film 53 in the peripheral circuit region is covered with a photoresist film 58,
The silicon oxide film 57 inside the trench 55 and the silicon oxide film 53 in the gap between the trenches 55 are removed by wet etching using a hydrofluoric acid-based etchant. Since the silicon nitride film 51 is formed at the bottom of the gap between the grooves 55, even if the silicon oxide film 53 is entirely removed, the silicon oxide film 46 thereunder is not shaved by the etching solution.
That is, the silicon nitride film 51 can function as an etch stopper for wet etching.

By the above-mentioned wet etching, the cylindrical lower electrode 60 is completed. Further, the silicon nitride film 51 remaining outside the lower electrode 60 (outside the groove 55) serves as a reinforcing member for reinforcing the lower electrode 60, thereby improving the mechanical strength of the lower electrode 60. Therefore, even when the height of the lower electrode 60 is increased, the separation and collapse thereof are suppressed.

Although the present embodiment exemplifies the photoresist film 58, the present invention is not limited to this.

The silicon oxide film 53 in the peripheral circuit region
Is disposed on the boundary between the memory array and the peripheral circuit region, that is, above the long groove 55a. Therefore, when the above-described wet etching is performed, the silicon oxide film 57 remains inside the long groove 55a. The silicon oxide film 57 serves as a reinforcing member for reinforcing the inner wall of the long groove 55a.
Electrode material (polycrystalline silicon film 56) constituting the inner wall of
Since the mechanical strength of b) is improved, even when the long groove 55a is formed deeply, the peeling and falling of the long groove 55a are suppressed.

On the other hand, the silicon oxide film 53 in the peripheral circuit region
Is covered by the photoresist film 58,
The surface is not shaved by the above wet etching. As a result, the step between the memory array and the peripheral circuit is eliminated, and the peripheral circuit region is also flattened.

Although the long groove 55a is provided in the present embodiment, the photoresist film 58 is not provided without the long groove 55a.
Using silicon as a mask, the silicon oxide film 57 and the silicon oxide film 53 inside the trench 55 can be removed by wet etching. In this case, as shown in FIG. 39, the silicon oxide film 53 on the peripheral circuit is over-etched. However, if the silicon oxide film 53 is later covered with a film having a high self-flatness such as an SOG film, the flatness is ensured and no particular problem occurs. Further, by using wet etching, the end surface of the silicon oxide film 53 becomes tapered as shown in the figure, so that the SOG film or the like can be easily embedded. In addition, especially the long groove 5
Since it is not necessary to form 5a, the occupied area can be saved and the chip area can be reduced. In this case, there is also an effect that the alignment accuracy of the photoresist film 58 does not need to be particularly high.

Next, the photoresist film 58 covering the peripheral circuit region is removed, and the semiconductor substrate 1 is cleaned. By this cleaning, the polycrystalline silicon film 56 forming the lower electrode 60 is formed.
The natural oxide film formed on the surface of b can be removed.

Next, as shown in FIG.
To form A detailed method of forming the capacitance insulating film 61 will be described with reference to enlarged views of the lower electrode 60 (FIGS. 41 and 42).

First, the semiconductor substrate 1 is subjected to a heat treatment, for example, at 800 ° C. for 3 minutes in a hydrogen atmosphere. Such a hydrogen heat treatment promotes the cleaning of the surface of the polycrystalline silicon film 56b, and is effective in reducing the defect density of the capacitance insulating film 61.

Thereafter, as shown in FIG.
The silicon nitride film 6 is formed on the surface of the polycrystalline silicon film 56b.
1a is formed. The silicon nitride film 61a can be formed by heat-treating the semiconductor substrate 1 in an ammonia atmosphere at about 800 ° C. for about 3 minutes to nitride the surface of the polycrystalline silicon film 56b.

By forming the silicon nitride film 61a on the surface of the polycrystalline silicon film 56b in this manner, the oxidizing agent that has passed through the tantalum oxide film 61b during the heat treatment in the oxidizing atmosphere of the tantalum oxide film 61b described later. Transmission can be prevented, and oxidation of the polycrystalline silicon film 56b can be suppressed. If the polycrystalline silicon film 56b is oxidized, the silicon oxide film having a low dielectric constant becomes a part of the capacitance insulating film 61, and the thickness of the capacitance insulating film 61 is substantially increased, and the capacitance value is reduced. It is not preferable to lower it. But,
As described above, the formation of the silicon nitride film 61a can prevent such a problem from occurring.

Next, as shown in FIG. 42, a tantalum oxide film 61b is deposited. The deposition of the tantalum oxide film 61b
For example, it can be formed by a CVD method using pentaethoxy tantalum (Ta (OC ₂ H ₅ ) ₅ ) as a raw material in an isothermal atmosphere at 450 ° C. The tantalum oxide film 6
The thickness of 1b is 15 nm. When a tantalum oxide film is used as the capacitor insulating film 61, (1) the film can be formed uniformly regardless of the size of the film-formed substrate, (2) the step coverage of the film is good, and (3) the film formation A necessary condition is that the film speed can be formed with good reproducibility without depending on the underlying material. In the case of deposition in a non-isothermal atmosphere, the above conditions may not be satisfied. However, in the present embodiment, since the tantalum oxide film 61b is deposited in an isothermal atmosphere, the tantalum oxide film 61b can be formed stably while satisfying the above conditions. is there. Further, in an apparatus for depositing a film in an isothermal atmosphere, gas cleaning in a reaction chamber is easy, so that the production yield can be improved.

Next, the semiconductor substrate 1 is subjected to a heat treatment in an oxygen atmosphere at, for example, 800 ° C. for 3 minutes to crystallize the amorphous tantalum oxide film 61b to form a polycrystalline tantalum oxide film 61.
c (Ta ₂ O ₅ ). At this time, active oxygen as an oxidant passes through the tantalum oxide film 61b. However, since the silicon nitride film 61a is formed as described above,
Oxygen permeation to the polycrystalline silicon film 56b can be prevented. In the present embodiment, the silicon nitride film 6
Since cleaning is performed as described above before the deposition of 1a,
The silicon nitride film 61a is formed uniformly, so that the permeation of oxygen can be more reliably prevented.

As described above, the capacitance insulating film 61 composed of the silicon nitride film 61a and the tantalum oxide film 61c is formed.

The thermal process for crystallizing the tantalum oxide film 61b is performed in the same manner as in the above-described amorphous silicon film 56.
At a temperature equal to or lower than the heat treatment for crystallization of Thus, the heat treatment for crystallizing the tantalum oxide film 61b does not cause the polycrystalline silicon film 56b formed by heat treatment at a temperature higher than this heat treatment to undergo deformation or the like due to thermal stress and to stably maintain the capacitance. The insulating film 61 can be formed.

Next, as shown in FIG.
After a TiN film 62 having a thickness of about 150 nm is deposited on the upper part 1, the TiN film 62 and the capacitor insulating film 61 are patterned by dry etching using a photoresist film 63 as a mask, thereby forming an upper electrode made of the TiN film 62. ,
The information storage capacitance element C composed of the capacitance insulating film 61 and the lower electrode 60 made of the polycrystalline silicon film 56b is formed. Thereby, the memory cell selecting MISFET Qs
And a memory cell of the DRAM composed of the information storage capacitance element C connected in series to this.

The TiN film 62 can be deposited by low pressure CVD at 450 ° C. using titanium tetrachloride and ammonia as source gases. Since the deposition of the TiN film 62 can be performed with good step coverage, it is possible to completely fill the recess formed by the lower electrode 60. As a result, the surface of the memory cell array
The N film 62 itself can be almost flattened. Since the surface can be flattened in this way, it is not necessary to deposit another insulating film, for example, and bury the concave portion. When the recess is buried with the insulating film, a void or the like may be generated at the bottom of the recess or the like, and it may be difficult to completely fill the recess. In particular, in the case of a miniaturized DRAM, the width of the lower electrode 60 is reduced and the depth of the lower electrode 60 must be increased. Therefore, the problem of embedding the concave portion is important. In the present embodiment, as described above, since the concave portion can be completely buried and the surface can be flattened, such a problem does not occur, and
Reliability can be improved.

The TiN film 62 is deposited by the above-described C method.
The present invention is not limited to the case where the TiN film is formed as a single layer by the VD method, and the surface may be planarized by depositing a thin TiN film by the CVD method and then stacking the TiN film by the sputtering method.

Further, the intrinsic stress of the TiN film 62 is 1 GPa.
It has been found by the present inventors that the characteristics of the information storage capacitive element C are deteriorated when the value exceeds. By the way, the stress of the TiN film strongly depends on the heat treatment temperature. According to the experimental studies by the present inventors, if heat is applied at a temperature exceeding 550 ° C. after the formation of the TiN film 62, the characteristics of the information storage capacitor C deteriorate almost in proportion to the temperature. Since this characteristic deterioration also occurs at the temperature at the time of forming the TiN film 62, it must be formed at a temperature of 550 ° C. or less. At a temperature of 400 ° C. or less, although the stress of the TiN film 62 is reduced,
2 are deposited on the surface and become foreign matters, resulting in a decrease in yield. Therefore, it is preferable that the TiN film 62 be formed at a temperature of 400 ° C. or higher.

After the upper electrode is formed of the TiN film 62, heat can be applied again in a temperature range of 450 ° C. to 550 ° C. By this reheating process, the leak current of the information storage capacitor C can be reduced as compared to before the reheating. It has been found from experiments by the present inventors that this phenomenon is peculiar to the TiN film formed by the CVD method. Therefore, the upper electrode is made of T by CVD.
When a laminated film of an iN film and a TiN film formed by a sputtering method is used, a TiN film formed by a CVD method is formed as a lowermost layer in contact with the tantalum oxide film 61c, and a reheating process is performed to reduce a leak current. In addition, this reheating treatment
A heat treatment for forming an insulating film in a later step may also serve as a heat treatment. After the formation of the TiN film 62, heat treatment at a temperature exceeding 550 ° C. is not performed. Thereby, the characteristics of the information storage capacitive element C can be favorably maintained.

Next, after removing the photoresist film 63, as shown in FIG. 44, an information storage capacitor is formed by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. After depositing a silicon oxide film 64 having a thickness of about 100 nm on the element C, the silicon oxide film 64 on the first layer wiring 38 of the peripheral circuit is formed by dry etching using the photoresist film 65 as a mask.
The through holes 66 are formed by removing the 53, 46, 45, the SOG film 44 and the silicon nitride film 40.

Next, after removing the photoresist film 65, as shown in FIG. 45, a plug 67 is formed inside the through hole 66, and then second layer wirings 68 and 69 are formed on the silicon oxide film 64. To form The plug 67 is formed on the silicon oxide film 64 with a thickness of 100 by a sputtering method.
A TiN film having a thickness of about nm is deposited, and a W film having a thickness of about 500 nm is further deposited thereon by a CVD method. Then, these films are etched back and left inside the through-hole 66. The second layer wirings 68 and 69 are formed on the silicon oxide film 64 by sputtering to a thickness of about 50 nm.
an iN film, an Al (aluminum) film having a thickness of about 500 nm,
After a Ti film having a thickness of about 50 nm is deposited, these films are formed by patterning by dry etching using a photoresist film as a mask.

Next, as shown in FIG.
An interlayer insulating film is deposited on the upper portions of 8 and 69. The interlayer insulating film includes, for example, a silicon oxide film 71 having a thickness of about 300 nm, an SOG film 72 having a thickness of about 400 nm, and a silicon oxide film 73 having a thickness of about 300 nm. Silicon oxide film 7
Reference numerals 1 and 73 denote plasma CVs using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as source gases.
Deposit by D method. The baking of the SOG film 72 is performed by using Al
This is performed at a temperature of about 400 ° C. in order to prevent the deterioration of the second layer wirings 68 and 69 mainly composed of the film.

Next, as shown in FIG. 47, a through-hole 74 is formed in the interlayer insulating film above the information storage capacitive element C, and a through-hole is formed in the interlayer insulating film above the second layer wiring 69 of the peripheral circuit. After forming the through holes 75, the through holes 74, 75
Is formed, and then third layer wirings 77, 78, 79 are formed above the interlayer insulating film. The through holes 74 and 75 are formed by removing the silicon oxide film 73, the SOG film 72, and the silicon oxide film 64 by dry etching using a photoresist film as a mask.
The plug 76 is formed by depositing a TiN film with a thickness of about 100 nm on the interlayer insulating film by a sputtering method, further depositing a W film with a thickness of about 500 nm on the TiN film by a CVD method, and then etching back these films. And formed in the through holes 74 and 75. Third layer wiring 77 to 79
Has a thickness of 50 nm on the interlayer insulating film by sputtering.
TiN film, Al film with thickness of about 500 nm, thickness of 50
After depositing a Ti film of about nm, these films are patterned and formed by dry etching using a photoresist film as a mask.

Thereafter, a passivation film composed of a stacked film of a silicon oxide film and a silicon nitride film is deposited on the third layer wirings 77 to 79, but is not shown. Through the above steps, the DRAM of the present embodiment is substantially completed.

In this embodiment, the bit line BL is formed of a laminated film containing a metal, and the tantalum oxide film 61c is used as the capacitance insulating film 61 even if the heat resistance of the contact with the silicon substrate or the like becomes poor. Therefore, there is an advantage that the temperature of the heat treatment can be lowered and the conduction failure at the contact portion can be avoided. In addition, since no step is formed between the information storage capacitor element C and the peripheral circuit area after the formation of the information storage capacitor element C, there is an advantage that the height of the lower electrode 60 is increased to easily secure the capacitance.

(Embodiment 2) DRAM of this embodiment
Will be described with reference to FIGS.

First, as shown in FIG. 48, according to the manufacturing method of the first embodiment (FIGS. 3 to 31), plugs 49 are formed.
Is formed, and a film thickness of 10 is formed on the silicon oxide film 46.
A silicon nitride film 51 of about 0 to 200 nm is deposited by a CVD method. Thereafter, a thickness of 0.8 is formed on the silicon nitride film 51.
After depositing a silicon oxide film 53 of about μm, the silicon oxide film 53 and the silicon nitride film 51 are removed by dry etching using the photoresist film 54 as a mask, thereby forming a groove above the through hole 48 in which the plug 49 is embedded. 55 are formed.

Next, after removing the photoresist film 54, as shown in FIG. 49, an upper portion of the silicon oxide film 53 is doped with an n-type impurity (for example, P (phosphorus)) to a thickness of 70 nm.
An amorphous silicon film 56 of about nm is deposited by a CVD method.
The amorphous silicon film 56 is to be a lower electrode of the information storage capacitor later. When the amorphous silicon film 56 is used, when the amorphous silicon film is converted to a polycrystalline silicon film. As in the first embodiment, the surface can be made extremely flat and the occurrence of defective capacitors can be suppressed. The deposition of the amorphous silicon film 56 is performed, for example, by using monosilane (SiH ₄ ).
As in the first embodiment, it can be performed by a low-pressure CVD method using a gas containing phosphine (PH ₃ ) as a source gas.

Next, as shown in FIG. 50, a silicon oxide film 57 is deposited on the amorphous silicon film 56 so as to completely fill the groove 55 and the long groove 55a (for example, about 400 nm). The silicon oxide film 57 is formed according to the first embodiment.
Similarly to the above, for example, plasma CVD using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas
Although it can be deposited by a method, it can also be an SOG film.

Next, as shown in FIG. 51, the silicon oxide film 57 and the amorphous silicon film 56 on the silicon oxide film 53 are polished and removed by using a CMP (Chemical Mechanical Polishing) method. The amorphous silicon film 56 is left on the inner wall and the bottom). At this time, the silicon oxide film 57 that has not been removed by polishing remains inside the groove 55.

Next, after cleaning the surface of the semiconductor substrate 1,
For example, heat treatment at 800 ° C. for 3 minutes is performed in a nitrogen atmosphere. By this heat treatment, the amorphous silicon film 56 is solid-phase grown and converted into a polycrystalline silicon film 56b.

Next, as shown in FIG. 52, a silicon oxide film 57 inside the groove 55 is etched using a hydrofluoric acid-based etching solution.
And the silicon oxide film 53 are removed by wet etching. Since wet etching is performed without using a mask, the silicon oxide film 53 is formed over the entire surface of the semiconductor substrate 1.
Is removed, and the silicon oxide film 53 in the peripheral circuit region is also completely removed. Since the silicon nitride film 51 is formed at the bottom of the gap of the groove 55 and the peripheral circuit region, even if the silicon oxide film 53 is entirely removed, the silicon oxide film 46 thereunder is not shaved by the etchant.

By the above wet etching, the cylindrical lower electrode 60 is completed. Also, the mechanical strength of the lower electrode 60 is improved by the silicon nitride film 51 remaining outside the lower electrode 60 (outside the groove 55), as in the first embodiment.

Next, the semiconductor substrate 1 is cleaned. By this cleaning, the polycrystalline silicon film 5 forming the lower electrode 60 is formed.
The natural oxide film formed on the surface of 6b can be removed.

Next, as shown in FIG.
To form The detailed method of forming the capacitor insulating film 61 is the same as that of the first embodiment, and thus the description is omitted.

Next, as shown in FIG. 54, first etching of the peripheral circuit is performed by dry etching using a photoresist film as a mask.
Capacitance insulating film 61 and silicon nitride film 5 above layer wiring 38
1. Through holes 81 are formed by removing the silicon oxide films 46 and 45, the SOG film 44, and the silicon nitride film 40.

Next, after removing the photoresist film, as shown in FIG. 55, a TiN film 8 having a thickness of about 150 nm is formed on the entire surface of the semiconductor substrate 1 including the inner surface of the through hole 81.
2 is deposited. The deposition of the TiN film 82 is the same as that of the TiN film 62 of the first embodiment, and a description thereof will be omitted.

Next, as shown in FIG. 56, the TiN film 82 and the capacitor insulating film 61 are patterned by dry etching using a photoresist film as a mask, so that T
An information storage capacitor C composed of an upper electrode 83 made of an iN film, a capacitor insulating film 61, and a lower electrode 60 made of a polycrystalline silicon film 56b is formed. As a result, a DRAM memory cell including the memory cell selection MISFET Qs and the information storage capacitor C connected in series thereto is completed. At the same time, a plug 84 made of a TiN film is formed in the peripheral circuit region. Thus, by forming the plug 84 in the peripheral circuit region, it is possible to easily open a connection hole formed in the peripheral circuit region, which will be described later. Although the plug 84 is illustrated here, it may be a wiring.

Next, as shown in FIG.
The insulating film 85 is deposited with a thickness slightly higher than the surface of the insulating film 85. The insulating film 85 can be deposited by a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas, for example, but can also be an SOG film.

Next, as shown in FIG. 58, the insulating film 85 is polished by the CMP method to flatten the surface. At this time,
A dummy pattern may be provided in a relatively concave area of the peripheral circuit area to ensure polishing flatness.

Next, as shown in FIG. 59, the through-hole 86 is formed by removing the insulating film 85 by dry etching using the photoresist film as a mask. Thereafter, the plug 67 and the second-layer wirings 68 and 69 of the first embodiment are used.
Similarly, the plug 87 and the second layer wiring 88 are formed. Since the plug 84 is formed below the through hole 86, the through hole 86 is not deepened, and the aspect ratio can be reduced. For this reason, the processing of the through hole 86 is facilitated, and the height of the lower electrode 60 can be increased, so that the amount of accumulated charges can be increased.

The subsequent steps are the same as in the first embodiment, and a description thereof will not be repeated. Through the above steps, the DRAM of the present embodiment is substantially completed.

According to the present embodiment, it is possible to lower the temperature of the process by using the tantalum oxide film 61b as the capacitor insulating film 61, and at the same time, to form the plug 84 or the wiring in the peripheral circuit region in the same layer as the upper electrode 83. The second layer wiring 88
Can be easily formed when the first through hole 86 is connected to the first layer wiring 38, or a higher information storage capacitor C can be formed to secure a large amount of stored charge.

(Embodiment 3) FIG. 60 shows Embodiment 1.
3 schematically shows the result of observing the crystal state after crystallizing the tantalum oxide film 61b of Example 2 and 2 using a transmission electron microscope. (A) shows a case where heat treatment was performed at 750 ° C. for 30 minutes in an oxygen atmosphere, and (b) shows a case where heat treatment was performed at 800 ° C. for 3 minutes in an oxygen atmosphere. The thickness of each tantalum oxide film 61b is 15 nm. (A)
In the case of (1), there is a tantalum oxide crystal 89 in which an extremely large grain growth of 1000 times the film thickness has occurred. On the other hand, (b)
In the case of (1), the tantalum oxide crystal 90 has a particle diameter of at most 100 times the thickness of the film and has a substantially uniform particle diameter. In the tantalum oxide film composed of the tantalum oxide crystal 89 having a large grain size, undulations are generated on the surface in order to alleviate the strain generated during the crystal growth, and the thickness of the grain boundary portion 91 is reduced, so that defects are likely to occur. . On the other hand, when heat treatment is performed at a high temperature, a tantalum oxide crystal with a large grain size does not grow due to an increase in nucleation density, and a tantalum oxide film having a relatively small and uniform tantalum oxide crystal 90 can be obtained. . For this reason, the strain can be reduced, the thickness of the grain boundary portion 92 can be increased, and the occurrence of defects can be suppressed. Therefore, when used for the tantalum oxide film 61b, 8
It is preferable to perform heat treatment at 00 ° C. for about 3 minutes.

(Embodiment 4) DRAM of this embodiment
A method of manufacturing the device will be described with reference to FIGS.

First, the manufacturing method of the first embodiment (FIG.
37), an amorphous silicon film 56 is buried in the trench 55 by the CMP method.

Then, without being converted into a polycrystalline silicon film by a heat treatment, wet etching is performed using the photoresist film 58 as a mask, as shown in FIG. 38, to expose the cylindrical amorphous silicon film 56. .

Next, the amorphous silicon film 56 is subjected to a nucleation process and crystallized to form a hemispherical silicon crystal 93. Thereafter, the same heat treatment as in the first embodiment is performed to convert the amorphous silicon film 56 into a polycrystalline silicon film 56b.
The lower electrode 60 is formed. FIG. 61A is an enlarged sectional view of a cylindrical amorphous silicon film 56. Here, an important point in the formation of the hemispherical silicon crystal 93 is to maintain the cleanness of the surface of the amorphous silicon film 56 before the nucleation process, and a natural oxide film and attached organic substances hinder the formation. It becomes a factor to do.

As a cleaning method, for example, after performing wet cleaning, UV (ultraviolet) and ozone (O ₃ ) cleaning, and HF gas etching can be exemplified. In addition, it is desirable that the cleaning step and the step of forming the hemispherical silicon crystal 93 be performed by an integrated apparatus.

FIG. 61B is a cross-sectional view schematically showing a problem in the case where the capacitive insulating film 61 is formed on the lower electrode 60. After forming the hemispherical silicon crystal 93, 80
A heat treatment is performed at 0 ° C. for 3 minutes to complete the crystallization of the amorphous silicon film 56 and convert it to a polycrystalline silicon film 56b.

Next, at 800.degree.
A partial heat treatment is performed to form a silicon nitride film 94 on the surface of the polycrystalline silicon film 56b having the hemispherical silicon crystal 93. After depositing the tantalum oxide film 95 by using the CVD method, a heat treatment is performed at 800 ° C. for 3 minutes in an oxygen atmosphere to crystallize the tantalum oxide film 95 and to form a polycrystalline tantalum oxide film 96.
To form

The thickness of the silicon nitride film 94 formed by the thermal nitriding method used here strongly depends on the impurity concentration on the surface of the underlying Si. The impurities which originally existed uniformly segregate when the hemispherical silicon crystal 93 is formed, and a region having a low impurity concentration is generated. For this reason, the thickness of the silicon nitride film 94 is reduced as in the region indicated by A in the figure. As a result, in the oxidation heat treatment after the formation of the tantalum oxide film 95, this A
Is abnormally oxidized, and the tantalum oxide film 95 itself is distorted, causing an increase in leak current.

To prevent this, silicon nitride film 94 is used.
Can be formed by a CVD method. The CVD method is a deposition reaction and can be formed without being affected by the impurity concentration of the base. Thereby, the silicon nitride film 94 can be formed with a uniform thickness regardless of the impurity concentration, thereby preventing abnormal oxidation.

It is also effective to form a silicon oxynitride film by oxidizing the silicon nitride film 94 before forming the tantalum oxide film 95 after forming the silicon nitride film 94 by the CVD method. It is.

On the other hand, as shown in B in the figure, the grain boundary 97 sometimes encounters the protrusion T of the base when the tantalum oxide film 95 is crystallized. The grain boundary 97 of tantalum oxide is formed so as to penetrate from the surface to the underlying nitride film, resulting in a thin film, which results in an increased leakage current at this portion, which is not preferable.

In order to prevent this, a plurality of layers formed by crystallizing a relatively thin tantalum oxide film can be formed so that the grain boundaries 97 do not penetrate. Thereby, the leak current can be reduced.

Thereafter, an upper electrode is formed and an information storage capacitor C is formed in the same manner as in the first embodiment. Subsequent steps are the same as those in the first embodiment, and a description thereof will not be repeated.

FIG. 62 is a graph showing an example of the current-voltage characteristic of the information storage capacitor C using the polycrystalline silicon film 56b having the hemispherical silicon crystal 93 as the lower electrode 60. The horizontal axis indicates the voltage applied to the upper electrode, and the vertical axis indicates the leak current density. The dotted line in the figure is 10 nA
The arrow V indicates the level of the leak current density of −1.5 cm / cm ^2.
V voltage is shown.

[0184] The characteristics of B are as follows. In the case of a capacitor insulating film formed by combining a silicon nitride film formed by thermal nitridation and a single-layer tantalum oxide film, the characteristics of A are obtained by combining a silicon nitride film formed by CVD with a plurality of layers. Of the capacitor insulating film formed by combining the tantalum oxide film of FIG. A,
The characteristics of B are similar in the positive side leakage current density, but there is a large difference in the negative side leakage current. Although the refresh characteristic of the DRAM cannot be satisfied with the characteristic of B, the characteristic of A can be satisfied. That is, when the silicon nitride film formed by the CVD method is used as the silicon nitride film 61a of the capacitor insulating film 61 and the tantalum oxide film 61b is formed in a plurality of layers, the refresh characteristics of the DRAM can be satisfied.

(Embodiment 5) FIG. 63 is a conceptual diagram showing an embodiment of a device suitable for suppressing the occurrence of defects in the information storage capacitive element C.

FIG. 63A shows a silicon nitride film forming portion 9.
8, an apparatus configuration in which a tantalum oxide film forming unit 99, a heat treatment unit 100, and a titanium nitride film forming unit 101 are connected. After the formation of the lower electrode 60, the semiconductor substrate 1 can be processed consistently from the formation of the silicon nitride film 61a to the formation of the upper electrode 62 without exposing the semiconductor substrate 1 to air. The occurrence can be suppressed. The apparatus may have a single reaction chamber having the above functions.

FIG. 63B shows that a cleaning section 102 is further provided in front of the silicon nitride film forming section 98 of FIG. 63A to more effectively reduce the occurrence of defects in the information storage capacitor C. Can be suppressed.

[0188] Each forming portion may be shut off by the gate valve 103.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, the material of the lower electrode is not limited to a polycrystalline silicon film, but may be a metal film or the like.

[0191]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) It is possible to provide a semiconductor integrated circuit device having an information storage capacitor element capable of securing a required amount of stored charge even if it is miniaturized, and a technique for manufacturing the same.

(2) To provide a structure and a manufacturing technique of a semiconductor integrated circuit device capable of easily opening a connection hole formed in a peripheral circuit region when a step between a memory cell array region and a peripheral circuit region is eliminated. can do.

(3) The leak current of the information storage capacitor can be reduced, and the amount of stored charge can be easily secured.

(3) It is possible to provide a structure and a manufacturing technique of the lower electrode, the capacitor insulating film, and the upper electrode constituting the information storage capacitor, which contribute to reducing the leak current of the information storage capacitor.

(4) A highly reliable semiconductor integrated circuit device can be obtained by securing a required amount of accumulated charge and lowering the temperature of the entire manufacturing process.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to an embodiment of the present invention is formed.

FIG. 2 is an equivalent circuit diagram of the DRAM according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 34 is a plan view showing a groove formed above a through hole and a pattern of a strip-shaped long groove surrounding a memory array.

FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 36 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 37 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 38 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 39 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 40 is an essential part cross sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 41 is an enlarged sectional view of a lower electrode portion.

FIG. 42 is an enlarged sectional view of a lower electrode portion.

FIG. 43 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 44 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 45 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 46 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 47 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 48 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 49 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 50 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 51 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 52 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 53 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 54 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 55 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 56 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 57 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 58 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 59 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the second embodiment of the present invention;

FIGS. 60 (a) and 60 (b) are schematic diagrams showing the results of observing the crystal state of the tantalum oxide film according to the third embodiment of the present invention after crystallization by using a transmission electron microscope. FIGS.

FIG. 61 is a cross-sectional view of a principal part showing the method of manufacturing the DRAM according to the fourth embodiment of the present invention, where (a) is an enlarged cross-sectional view of a cylindrical amorphous silicon film portion, and (b) FIG. 4 is a cross-sectional view schematically showing a problem when a capacitive insulating film is formed on a lower electrode.

FIG. 62 is a graph showing current-voltage characteristics of an information storage capacitor using a polycrystalline silicon film having a hemispherical silicon crystal as a lower electrode according to a fourth embodiment of the present invention.

FIGS. 63 (a) and (b) are conceptual diagrams showing an example of a manufacturing apparatus according to a fifth embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 1A semiconductor chip 2 silicon oxide film 3 silicon nitride film 4 photoresist film 5 element isolation groove 5a groove 6 thin silicon oxide film 7 silicon oxide film 8 silicon nitride film 9 photoresist film 10 n-type semiconductor region 11 p-type well Reference Signs List 12 n-type well 13 gate oxide film 14 gate electrode 14A gate electrode 14B gate electrode 14C gate electrode 15 silicon nitride film 16 photoresist film 17 p ^- type semiconductor region 18 n ^- type semiconductor region 19 n-type semiconductor region 20 silicon nitride film 20a sidewall spacers 21 the photoresist film 22 p ⁺ -type semiconductor region 23 n ⁺ -type semiconductor region 24 SOG film 25 a silicon oxide film 26 a silicon oxide film 27 a photoresist film 28 contact hole 29 the contact hole 30 plug 31 oxidized Con film 32 Photoresist film 33 Photoresist film 34 Contact hole 36 Contact hole 38 First layer wiring 40 Silicon nitride film 41 Photoresist film 42 Silicon oxide film 43 Sidewall spacer 44 SOG film 45 Silicon oxide film 46 Silicon oxide film 47 Photo Resist film 48 Through hole 49 Plug 51 Silicon nitride film 52 Photoresist film 53 Silicon oxide film 54 Photoresist film 55 Groove 55a Long groove 56 Amorphous silicon film 56b Polycrystalline silicon film 57 Silicon oxide film 58 Photoresist film 60 Lower electrode 61 Capacitance insulating film 61a Silicon nitride film 61b Tantalum oxide film 61c Tantalum oxide film 62 TiN film (upper electrode) 63 Photoresist film 64 Silicon oxide film 65 Photoresist film 6 Through hole 67 Plug 68 Second layer wiring 69 Second layer wiring 71 Silicon oxide film 72 SOG film 73 Silicon oxide film 74 Through hole 75 Through hole 76 Plug 77 Third layer wiring 81 Through hole 82 TiN film 83 Upper electrode 84 Plug 85 Insulating film 86 through hole 87 plug 88 second layer wiring 89 tantalum oxide crystal 90 tantalum oxide crystal 91 grain boundary part 92 grain boundary part 93 hemispherical silicon crystal 94 silicon nitride film 95 tantalum oxide film 96 tantalum oxide film 97 grain boundary 98 nitridation Silicon film forming part 99 Tantalum oxide film forming part 100 Heat treatment part 101 Titanium nitride film forming part 102 Cleaning processing part 103 Gate valve BL Bit line C Information storage capacitance element MARY Memory array Qn N-channel MISFET Qpp Channel Type MISFET Qs for memory cell selection MISFET SA sense amplifier WD word driver

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Isamu Isano 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Tsuyoshi Tamaru 2326, Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Center, Ltd. (72) Inventor Masato Kunitomo 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Masayuki Nakata 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Semiconductor, Hitachi, Ltd. Within the Business Division (72) Inventor Joe Yuji 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Semiconductor Business Division, Hitachi, Ltd.

Claims (33)

[Claims] 1. A lower electrode comprising a cylindrical polycrystalline silicon film having a memory cell comprising a memory cell selecting MISFET and an information storage capacitor connected in series with the MISFET, and having an opening above. The information storage capacitance element having a capacitance insulating film formed on the surface of the lower electrode and an upper electrode formed opposite to the lower electrode with the capacitance insulating film interposed therebetween is provided above the memory cell selecting MISFET. A method of manufacturing a semiconductor integrated circuit device having a DRAM arranged therein, comprising: (a) depositing a first insulating film on a memory cell selecting MISFET formed on a main surface of a semiconductor substrate;
Forming a groove by opening the first insulating film, and (b) the groove is not filled with an amorphous silicon film containing impurities on the first insulating film including the inside of the groove. (C) depositing a second insulating film having a thickness such that the trench is filled on the amorphous silicon film;
(D) removing the amorphous silicon film above the second insulating film and the first insulating film in a region where the groove is formed, thereby forming the amorphous silicon film only inside the groove; (E) performing a first heat treatment to solid-phase grow the amorphous silicon film to convert it to a polycrystalline silicon film; (f) forming a gap between the groove and a groove adjacent thereto. Removing the first insulating film and the second insulating film inside the trench to form a cylindrical lower electrode having an opening above; (g) depositing the capacitive insulating film on the surface of the lower electrode; Forming and performing a second heat treatment to modify the capacitance insulating film. 2. A lower electrode comprising a cylindrical polycrystalline silicon film having a memory cell selection MISFET and an information storage capacitance element connected in series with the memory cell selection MISFET and having an opening above the memory cell. The information storage capacitor having a capacitor insulating film formed on the surface of the lower electrode and an upper electrode formed opposite to the lower electrode with the capacitor insulating film interposed therebetween is provided above the memory cell selecting MISFET. A method of manufacturing a semiconductor integrated circuit device having a DRAM arranged therein, comprising: (a) depositing a first insulating film on a memory cell selecting MISFET formed on a main surface of a semiconductor substrate;
Forming a groove by opening the first insulating film, and (b) the groove is not filled with an amorphous silicon film containing impurities on the first insulating film including the inside of the groove. (C) depositing a second insulating film having a thickness such that the trench is filled on the amorphous silicon film;
(D) removing the amorphous silicon film above the second insulating film and the first insulating film in a region where the groove is formed, thereby forming the amorphous silicon film only inside the groove; (E) removing the first insulating film in the gap between the groove and the groove adjacent thereto and the second insulating film inside the groove, and forming a cylindrical amorphous material having an opening above. Exposing the amorphous silicon film, (f) performing a first heat treatment, solid-phase growing the amorphous silicon film, converting the amorphous silicon film into a polycrystalline silicon film, and forming the lower electrode; Forming the capacitive insulating film on the surface of the lower electrode, and performing a second heat treatment to modify the capacitive insulating film. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein after exposing a cylindrical amorphous silicon film having an opening above, the amorphous silicon film is removed. A method for manufacturing a semiconductor integrated circuit device, comprising a step of forming irregularities on a surface. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the amorphous silicon film is formed before forming irregularities on the surface of the cylindrical amorphous silicon film having an opening above. A method for manufacturing a semiconductor integrated circuit device, comprising a step of cleaning a surface of a porous silicon film. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said amorphous silicon film is formed by a low pressure CVD method using a gas containing at least monosilane (SiH4) as a source gas. And a method for manufacturing a semiconductor integrated circuit device. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the removal of the second insulating film and the amorphous silicon film is performed by a first CMP method. A second method performed by etching the first conductive film after exposing the first conductive film on the first insulating film by etching the second insulating film. And a method of manufacturing a semiconductor integrated circuit device. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first heat treatment comprises:
A method for manufacturing a semiconductor integrated circuit device, wherein the method is performed at a temperature equal to or higher than the second heat treatment. 8. A lower electrode comprising a cylindrical polycrystalline silicon film having a memory cell comprising a memory cell selecting MISFET and an information storage capacitance element connected in series with the MISFET, and having an opening above. The information storage capacitor having a capacitor insulating film formed on the surface of the lower electrode and an upper electrode formed opposite to the lower electrode with the capacitor insulating film interposed therebetween is provided above the memory cell selecting MISFET. A method for manufacturing a semiconductor integrated circuit device having a DRAM arranged therein, comprising: (a) forming a cylindrical lower electrode having an opening above on a memory cell selecting MISFET formed on a main surface of a semiconductor substrate; Forming; (b) forming a silicon nitride film on the surface of the lower electrode; (c) depositing a tantalum oxide film on the silicon nitride film by a CVD method; Performing a heat treatment on the tantalum oxide film to modify the tantalum oxide film to form the capacitive insulating film. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein the silicon nitride film is formed at a temperature of 600 ° C. to 8 ° C.
A method for manufacturing a semiconductor integrated circuit device, which is formed by heat treatment in an ammonia (NH ₃ ) atmosphere at 50 ° C. or by low-pressure CVD. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein said low-pressure CVD method uses a gas containing at least dichlorosilane (SiH ₂ Cl ₂ ) and ammonia as a source gas. A method for manufacturing a semiconductor integrated circuit device. 11. A method of manufacturing a semiconductor integrated circuit device according to claim 8, further comprising a step of forming a silicon oxynitride film before depositing said tantalum oxide film. Production method. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein a surface of said lower electrode is cleaned before forming said silicon nitride film or silicon oxynitride film. A method for manufacturing a semiconductor integrated circuit device, comprising: 13. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the surface of said lower electrode is cleaned.
A reaction for forming the silicon nitride film or the silicon oxynitride film in the same reaction chamber as the reaction chamber for forming the silicon nitride film or the silicon oxynitride film, or in a transfer chamber which can be in a reduced pressure or an inert atmosphere A method for manufacturing a semiconductor integrated circuit device, comprising performing heat treatment in a hydrogen atmosphere in another reaction chamber connected to the chamber. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein the tantalum oxide film is deposited in an isothermal atmosphere at 450 ° C. or higher. A method for manufacturing a circuit device. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the heat treatment of the tantalum oxide film is performed so that the tantalum oxide has a uniform crystal grain size. A method for manufacturing a semiconductor integrated circuit device, comprising: 16. The method for manufacturing a semiconductor integrated circuit device according to claim 15, wherein the heat treatment is performed at 730 ° C. or higher and 85 ° C.
A method for manufacturing a semiconductor integrated circuit device, wherein the method is performed in an oxidizing atmosphere in a temperature range of 0 ° C. or less. 17. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein said silicon nitride film is converted into a film containing a silicon oxynitride film by said heat treatment. A method for manufacturing an integrated circuit device. 18. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein after the heat treatment of the tantalum oxide film, a second tantalum oxide film is further formed by CVD.
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: depositing by a method and heat-treating the second tantalum oxide film. 19. A memory cell comprising a memory cell selecting MISFET and an information storage capacitance element connected in series with the memory cell selecting MISFET, a cylindrical lower electrode having an opening above and a surface of the lower electrode. A semiconductor having a DRAM in which the information storage capacitor having the formed capacitor insulating film and an upper electrode formed opposite to the lower electrode with the capacitor insulating film interposed therebetween is arranged above the memory cell selecting MISFET. A method of manufacturing an integrated circuit device, comprising: (a) forming the lower electrode on a memory cell selecting MISFET formed on a main surface of a semiconductor substrate, and forming the capacitive insulating film on at least a surface of the lower electrode; (B) depositing a titanium nitride film to be the upper electrode on the entire surface of the semiconductor substrate on which the capacitive insulating film is formed, and forming a concave portion formed by the cylindrical shape of the lower electrode. Burying a portion to planarize the surface of the titanium nitride film on the lower electrode. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein a connection hole is formed in a peripheral circuit region around a memory cell array region in which said memory cell is formed before depositing said titanium nitride film. Opening, depositing the titanium nitride film on the entire surface of the semiconductor substrate including the connection hole, patterning the titanium nitride film, forming the upper electrode so as to cover the memory cell array region, and simultaneously filling the connection hole. A method for manufacturing a semiconductor integrated circuit device, wherein a plug or a wiring is formed. 21. The method for manufacturing a semiconductor integrated circuit device according to claim 19, wherein the titanium nitride film is
The first method of depositing only by the CVD method, and the second method of depositing the second titanium nitride film by sputtering after depositing the first titanium nitride film by CVD. A method for manufacturing a semiconductor integrated circuit device. 22. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein the titanium nitride film formed by the CVD method includes a gas containing at least titanium tetrachloride and ammonia in a temperature range of 430 ° C. to 500 ° C. A method for manufacturing a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is deposited using a raw material gas. 23. The method for manufacturing a semiconductor integrated circuit device according to claim 19, wherein after depositing said titanium nitride film, a heat treatment at a temperature exceeding 550 ° C. is not performed. Device manufacturing method. 24. An information storage device comprising: a memory cell selection MISFET and an information storage capacitor connected in series with the MISFET, and comprising a cylindrical lower electrode having an opening above. The capacitor is replaced with the memory cell selecting MI.
1. A method of manufacturing a semiconductor integrated circuit device having a DRAM disposed above an SFET, comprising: (a) a first step above a memory cell selecting MISFET formed on a main surface of a semiconductor substrate;
Depositing an insulating film, depositing a second insulating film having an etching rate different from that of the first insulating film, and then forming a groove by opening the first insulating film and the second insulating film; (b) Depositing a first conductive film constituting a lower electrode of the information storage capacitor on the second insulating film including the inside of the groove so as to fill the groove, and (c) the first conductive film Depositing a third insulating film having a thickness so as to fill the groove on the film, and (d) forming the first insulating film on the third insulating film in the region where the groove is formed and the first insulating film on the second insulating film. Removing the conductive film to leave the first conductive film only inside the groove; (e) forming the second insulating film in the gap between the groove and a groove adjacent to the groove, and forming the first conductive film inside the groove. Etching the third insulating film using the first insulating film as an etching stopper;
Forming the cylindrical lower electrode having an opening above. 11. A method of manufacturing a semiconductor integrated circuit device, comprising: 25. A lower electrode comprising a cylindrical polycrystalline silicon film having a memory cell comprising a memory cell selecting MISFET and an information storage capacitor connected in series with the MISFET and having an opening above. The information storage capacitor having a capacitor insulating film formed on the surface of the lower electrode and an upper electrode formed opposite to the lower electrode with the capacitor insulating film interposed therebetween is provided above the memory cell selecting MISFET. A semiconductor integrated circuit device having a DRAM arranged therein,
A semiconductor integrated circuit device, wherein an upper end of the lower electrode does not have a sharp tip. 26. A lower electrode comprising a cylindrical polycrystalline silicon film having a memory cell comprising a memory cell selecting MISFET and an information storage capacitance element connected in series with the MISFET, and having an opening above. The information storage capacitor having a capacitor insulating film formed on the surface of the lower electrode and an upper electrode formed opposite to the lower electrode with the capacitor insulating film interposed therebetween is provided above the memory cell selecting MISFET. A semiconductor integrated circuit device having a DRAM arranged therein,
The semiconductor integrated circuit device according to claim 1, wherein the capacitance insulating film includes a silicon nitride film or a silicon oxynitride film, and a tantalum oxide film. 27. The semiconductor integrated circuit device according to claim 26, wherein said silicon nitride film has a thickness of 5 nm or less, and said silicon oxynitride film has a thickness of 3 to 4.5 nm. The thickness of the tantalum oxide film is 10 to 20 nm.
Semiconductor integrated circuit device characterized by the above-mentioned range. 28. The semiconductor integrated circuit device according to claim 26, wherein the tantalum oxide film is formed as a single layer or a plurality of layers. 29. The semiconductor integrated circuit device according to claim 26, 27 or 28, wherein the crystal constituting the tantalum oxide film has an average grain size of 1.5 μm or less, and the crystal grain size is substantially equal to or smaller than 1.5 μm. A semiconductor integrated circuit device which is uniform. 30. A lower electrode comprising a cylindrical polycrystalline silicon film having a memory cell comprising a memory cell selecting MISFET and an information storage capacitor connected in series with the MISFET, and having an opening above. The information storage capacitor having a capacitor insulating film formed on the surface of the lower electrode and an upper electrode formed opposite to the lower electrode with the capacitor insulating film interposed therebetween is provided above the memory cell selecting MISFET. A semiconductor integrated circuit device having a DRAM arranged therein,
The semiconductor integrated circuit device, wherein the upper electrode includes a titanium nitride film formed by a CVD method, and has an intrinsic stress of less than 1 Gpa. 31. The semiconductor integrated circuit device according to claim 25, wherein the information storage capacitor is configured such that the upper electrode side is in a negative bias condition relatively to the lower electrode side. Wherein the current density flowing between the upper electrode and the lower electrode is 10 nA / cm ^2, and the absolute value of the bias voltage is 1.5 V or more. apparatus. 32. A first means for forming a silicon nitride film or a silicon oxynitride film, a second means for depositing a tantalum oxide film, a third means for performing heat treatment in an oxidizing atmosphere, and a CVD method. A semiconductor integrated circuit device manufacturing apparatus having a fourth means for depositing a titanium nitride film, wherein the first, second, third and fourth means are provided in the same reaction chamber. A second, each having a first, second, third and fourth means in a separate reaction chamber, wherein said separate reaction chambers are connected by a transfer chamber capable of maintaining a reduced pressure or an inert atmosphere; A manufacturing apparatus for a semiconductor integrated circuit device, comprising: 33. An apparatus for manufacturing a semiconductor integrated circuit device according to claim 32, wherein said first, second, third and fourth devices are manufactured.
5. An apparatus for manufacturing a semiconductor integrated circuit device, comprising: a fifth means for performing a heat treatment in a hydrogen atmosphere in addition to the means.