JPH11261106A - Semiconductor device - Google Patents

Abstract

[PROBLEMS] To provide a high-quality semiconductor light-emitting element, semiconductor light-receiving element, semiconductor optical modulator, and an optical integrated circuit in which these elements are integrated at a low cost. A semiconductor device formed on an insulating or semi-insulating substrate, comprising: a laminated structure of active element portions;
1 and an electrode 15 close to the substrate 1, wherein the semiconductor device has a stacked structure including a semiconductor layer 4 having a small electron affinity and a semiconductor layer 5 having a large electron affinity with an impurity added thereto. Solve the problem.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using an insulating or semi-insulating substrate, and more particularly to a method for simplifying element isolation when it is necessary to use an insulating or semi-insulating substrate. The present invention relates to a semiconductor device having a low parallel current path resistance. More specifically, in the present invention, an insulated or semi-insulated substrate must be used because a substrate having a desired conductivity, high crystal quality, and large area cannot be obtained as a growth substrate for a crystal layer constituting an element. The present invention relates to a semiconductor device such as a semiconductor light emitting element, a semiconductor light receiving element, and a semiconductor optical modulator.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device using an insulating or semi-insulating substrate, that is, a semiconductor light emitting element, a semiconductor light receiving element, a semiconductor optical modulator, and an optical integrated circuit in which these elements are integrated, p, n When injecting or extracting carriers from the metal electrode closer to the substrate to the semiconductor, the carriers travel in the semiconductor layer near the substrate in the direction perpendicular to the film thickness direction, that is, in the in-plane direction. Will do. At this time, heat is generated because the semiconductor has a higher specific resistance than the metal. The heat generated in this way hastened the deterioration of the element. Also,
The rise in temperature due to heat generation has caused a decrease in the efficiency of energy conversion of light-emitting elements and light-receiving elements from electricity to light or from light to electricity. Further, the temperature characteristics of the device have also been reduced. In particular, in the semiconductor laser, the heat generation and the decrease in the energy conversion efficiency have led to an increase in the threshold current. I on the semi-insulating InP substrate actually produced by the inventor
nGaAsP / InP embedded laser (T. Matsuoka,
K. Takahei, Y. Noguchi and H. Nagai, "1.5 μm regio
n InP / GaInAsP buried heterostructure lasers on sem
i-insulating substrates ", Electron. Lett., 17 (198
1) In the case of 12), in the case of continuous oscillation at room temperature, when the electrodes are taken out from one side of the substrate using an insulating substrate and when both electrodes are taken out from both sides of the substrate using a conductive substrate, Differences occurred. That is, at that time, when a conductive substrate was used, the threshold current during pulse driving was 50 m.
The devices A and below always continually oscillated at room temperature when mounted on a heat sink. However, when an insulating substrate was used, the threshold current at the time of pulse driving had to be 40 mA or less for continuous oscillation at room temperature.

In order to take out electrodes only from one side of the substrate, it is necessary to form electrodes in a layer in a lower region of a plurality of stacked semiconductors. At that time, it is necessary to shorten the current path in order to improve the element characteristics. for that reason,
When the element is viewed from the upper surface of the substrate, it is necessary to bring the electrode in this lower region as close to the upper electrode as possible. However, when the lower electrode is formed, a process having a step is performed, so that fine processing becomes difficult. Therefore, bringing both electrodes close to each other has also caused a decrease in yield. In addition, since the carrier resistance of the carrier traveling path is high, the carrier cannot be injected or withdrawn at a high speed.
It could not cope with high-speed modulation.

Further, when the elements are integrated, the same voltage cannot be applied to each element, and the characteristics of each element cannot be sufficiently obtained.

[0005] The cause of the above-mentioned problems in the prior art is that the carrier running path connected to the electrode closer to the substrate among the carrier running paths connected to both the p and n electrodes has a higher resistivity than the metal. This is because the semiconductor layer was in the in-plane direction of the semiconductor layer having a large value.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a high quality semiconductor light emitting device, a semiconductor light receiving device, a semiconductor optical modulator, and a semiconductor light modulator. An object is to provide an optical integrated circuit in which elements are integrated at a low cost.

[0007]

In order to achieve the above object, the present invention provides a method of forming a conductive layer serving as a carrier traveling path connected to an electrode close to a substrate on a first semiconductor layer having a small electron affinity. A semiconductor device characterized by being formed by stacking a second semiconductor layer with a high electron affinity to which an impurity is added, which is the main feature, is provided. As the first semiconductor layer, a semiconductor layer having a small electron affinity without adding an impurity can be used. In the semiconductor device according to the present invention, the resistance of the carrier traveling path connected to the electrode closer to the substrate is extremely small as compared with the semiconductor device according to the related art, and the calorific value in the carrier traveling path can be significantly reduced. . Further, as compared with the semiconductor device according to the prior art, even if the distance between the p and n electrodes is increased, the resistance of the carrier traveling path does not increase. improves.

In the semiconductor device according to the present invention, by using a structure having a stacked structure of the first semiconductor layer having a small electron affinity and the second semiconductor layer having a large electron affinity having an impurity added thereto, both layers are formed. A two-dimensional electron gas is generated near the interface. The carrier concentration of the two-dimensional electron gas is high, and the mobility of the carrier therein is high. Therefore, the electric resistance in the two-dimensional electron gas region is much lower than that of a conventional semiconductor carrier traveling path made of one kind of material. Therefore, since the carrier passes through the low-resistance two-dimensional electron gas region, the amount of heat generated on the carrier traveling path can be significantly reduced. Further, as compared with the semiconductor device according to the prior art, even if the distance between the p and n electrodes is increased, the resistance of the carrier traveling path does not increase. improves. Further, since the resistance of the carrier traveling path is small, the use of the present carrier traveling path makes it possible to inject and extract carriers at high speed, and as a result, it is possible to cope with high-speed modulation by the present element.

[0009]

Embodiments of the present invention will be described. It is to be noted that this description is one example, and it goes without saying that various changes or improvements can be made without departing from the spirit of the present invention.

Embodiment 1 FIG. 1 is a view for explaining a first embodiment of the present invention, and is a cross-sectional view in a direction in which guided light reciprocates in a resonator, that is, perpendicular to the axis of the resonator. is there. Here, (0001) sapphire having a thickness of 330 μm was used as the substrate single crystal. The element structure has a nitride layer 2 (nitride depth 1.2 nm) formed on the surface of a sapphire (0001) substrate 1 and a film thickness of 20 nm.
nm GaN buffer layer 3 and 1 μm thick undoped G
aN layer 4, 2 μm-thick Si-doped n-type Al _0.14 Ga
_0.86 N electron supply layer 5, Si-doped n-type Al _0.1 Ga _0.9 N clad layer 6 having a thickness of 0.5 μm, Si having a thickness of 0.1 μm
Doped n-type GaN waveguide layer 7, 40 nm thick In _0.1
A multiple quantum well 8 comprising a pair of a Ga _0.9 N well layer and a 7 nm-thick GaN barrier layer, and a 20 nm thick Mg-doped p.
-Type Al _0.2 Ga _0.8 N conduction band energy step forming layer 9, Mg-doped p-type GaN waveguide layer 1 having a thickness of 0.1 μm
0, Mg-doped p-type Al _0.1 Ga _0.9 N with a thickness of 0.5 μm
It comprises a cladding layer 11 and a Mg-doped p-type GaN contact layer 12 having a thickness of 0.1 μm. Pd having a thickness of 50 nm is formed on p-type GaN 12 as metal electrode 13 for p-type.
And Au having a thickness of 200 nm are stacked. In order to limit the electrode injection region, Si having an opening window having a width of 40 μm
The O ₂ current limiting insulating layer 14 is used. Further, as the metal electrode 15 for n-type, a film thickness of 50
nm of Ti and 200 nm of Au are laminated. In this device, the undoped GaN layer 4 and the Si-doped n-type A
The l _0.14 Ga _0.86 N electron supply layer 5 corresponds to the first semiconductor layer having a small electron affinity and the second semiconductor layer having a high electron affinity to which an impurity is added, respectively.

Next, a method for manufacturing the present element will be described. For the crystal growth, a metal organic chemical vapor deposition apparatus having a vertical growth furnace was used. At the beginning of crystal growth, the sapphire substrate surface is
Nitrided at 0 ° C. Thereafter, a GaN buffer layer was grown at 550 ° C. and annealed at 1050 ° C. for 9 minutes to achieve single crystallization of the buffer layer. Next, at 1020 ° C.,
The i-doped GaN layer 12 was grown. In _0.1 Ga _0.9
In growing the N / GaN multiple quantum well layer 8, the growth temperature was set at 8 in order to take indium.
The temperature was set to 00 ° C. In addition, in order to protect the present multiple quantum well layer, the energy of the Mg-doped p-type Al _0.2 Ga _0.8 N conduction band
The growth temperature was set to the same 800 ° C. even when growing the step formation layer 9. The growth temperature of each layer on it is 10
20 ° C. After the crystal growth, a dry etching apparatus using chlorine gas was used as a method for etching the crystal layer into the shape shown in FIG. The apparatus used here is a high-speed atomic beam reactive etching apparatus. In this apparatus, the etching rate of the GaN-based material is at least one order of magnitude higher than the etching rate of the AZ-based photoresist used for the photolithography technique. Therefore, etching with high perpendicularity is possible. After the etching, an electrode metal was deposited using an electron beam deposition apparatus. Photolithography technology was used for patterning the electrodes.

Next, the characteristics of the device having the structure shown in FIG. 1 will be described. Si-doped n-type Al _0.14 Ga _0.86 N electron supply layer 5
Is sufficiently thick at 2 μm, a two-dimensional electron gas always exists at the interface between the undoped GaN layer 4 and the 1 μm-thick GaN layer 4. Therefore, when a current flows between the p and n electrodes, the electric resistance between the n-type metal electrode 15 and the n-type Al _0.1 Ga _0.9 N clad layer 6 decreases. Therefore, the electrode 15
The sheet resistance from the substrate to the n-type cladding layer 6 does not impair the laser characteristics of the device. Therefore, the temperature characteristic of the oscillation threshold current was also greatly improved as compared with a normal structure using no two-dimensional electron gas. In addition, the temperature rise due to the generation of Joule heat on the carrier traveling path when a large current was passed for high output operation could be reduced.

Embodiment 2 FIG. 2 is a view for explaining a second embodiment of the present invention, and is a sectional view in a direction in which guided light reciprocates in a resonator, that is, a cross section perpendicular to the axis of the resonator. is there. Here, (0001) sapphire having a thickness of 330 μm was used as the substrate single crystal. The element structure includes a nitride layer 17 (nitride depth 1.2 nm) formed on the surface of a sapphire (0001) substrate 16, a GaN buffer layer 18 having a thickness of 20 nm, an undoped GaN layer 19 having a thickness of 1 μm, and a thickness of 0.1 μm. Si-doped n-type A
l _0.14 Ga _0.86 N electron supply layer 20, 0.5 μm thick S
i-doped n-type Al _0.1 Ga _0.9 N clad layer 21, Si-doped n-type GaN waveguide layer 22 having a thickness of 0.1 μm, a well layer of In _0.1 Ga _0.9 N having a thickness of 40 nm and G having a thickness of 7 nm
Multiple quantum well 23 composed of three pairs of aN barrier layers, film thickness 20
nm-doped p-type Al _0.2 Ga _0.8 N conduction band energy step formation layer 24, 0.1 μm-thick Mg-doped p
-Type GaN waveguide layer 25, Mg-doped p having a thickness of 0.5 μm
Type Al _0.1 Ga _0.9 N cladding layer 26 and a film thickness of _0.1 mm.
It is made of a 1 μm Mg-doped p-type GaN contact layer 27. Compared to the first embodiment, Si-doped n-type Al _0.14 G
The feature is that the thickness of the a _0.86 N electron supply layer 20 is much thinner. As the p-type metal electrode 28, the p-type GaN layer 27
Pd having a thickness of 50 nm and Au having a thickness of 200 nm are laminated thereon. In order to limit the electrode injection region, the same SiO ₂ current limiting insulating layer 29 as in the first embodiment is used. In addition, as the metal electrode 30 for n-type, undoped G
50 nm thick Ti and 200 nm Au on the aN layer 19.
Are laminated. In addition, this element has a gate electrode 31 which is not provided in the first embodiment. The electrode material and the film thickness are the same as those of the n-type metal electrode. In this device, the undoped GaN layer 19 and the Si-doped n-type Al _0.14 Ga
_{The 0.86} N electron supply layer 20 corresponds to the first semiconductor layer having a small electron affinity and the second semiconductor layer having a large electron affinity to which an impurity is added, respectively.

The method of manufacturing the device is the same as that of the first embodiment.

Next, the characteristics of the device having the structure shown in FIG.
Bell. Si-doped n-type Al_0.14Ga _0.86N electron supply layer 2
0 is as thin as 0.1 μm,
The interface with the doped GaN layer 19 depends on the gate voltage.
Exist, there is a two-dimensional electron gas. That is, the gate
The electrode 31 has a large negative voltage with respect to the n-type GaN electrode 30.
When a voltage is applied, the depletion layer expands from just below the gate electrode,
The two-dimensional electron gas no longer exists at the interface. That
From n-type GaN to n-type Al_0.1Ga_0.9N cladding layer 2
The current path to 1 is cut off. Therefore, both p and n metal electrodes
A constant voltage is applied between the poles and applied to the gate electrode.
Control the laser oscillation output by controlling the voltage
Or turn on / off laser oscillation. You
That is, by inputting an electric signal to the gate voltage,
The optical signal can be controlled. In this way, the electrical signal is
Can be converted to an issue.

Third Embodiment FIG. 3 is a view for explaining a third embodiment of the present invention, and is a cross-sectional view showing a direction parallel to a crystal growth direction. Here, as the substrate single crystal, (000) having a thickness of 330 μm is used.
1) Sapphire was used. The element structure is sapphire (0
001) The nitride layer 33 (nitride depth 1.2 nm) formed on the surface of the substrate 32 and the GaN buffer layer 3 having a thickness of 20 nm
4. 1 μm thick undoped GaN layer 35, 2 μm thickness
Si-doped n-type Al _0.14 Ga _0.86 N electron supply layer 36 of
A 0.5 μm-thick Si-doped n-type Al _0.1 Ga _0.9 N cladding layer 37, a multiple quantum well 38 comprising a pair of a 40 nm-thick In _0.1 Ga _0.9 N well layer and a 7 nm-thick GaN barrier layer, 0.5 μm Mg-doped p-type Al _0.1 Ga
_0.9 N clad layer 39 and 0.1 μm thick Mg
It comprises a doped p-type GaN contact layer 40. The electrode structure and the element formation method are the same as in the first embodiment. Further, a p-type metal electrode 41, a SiO ₂ current limiting insulating layer 42, and an n-type metal electrode 43 are arranged in this element. This device has a structure in which a plurality of light emitting diodes are arranged. In this device, the undoped GaN layer 35 and the Si-doped n-type Al _0.14 Ga _0.86 N electron supply layer 36 are respectively composed of the first semiconductor layer having a small electron affinity and the second semiconductor having a large electron affinity with an impurity added. Layers and falls.

Next, the characteristics of the device having the structure shown in FIG. 3 will be described. As in the first embodiment, Si-doped n-type Al _0.14 G
Since the a _0.86 N electron supply layer 36 has a sufficiently large thickness of 2 μm, a two-dimensional electron gas is always present at the interface between the undoped GaN layer 35 having a thickness of 1 μm. Therefore, p,
When a current flows between the n electrodes, the n-type metal electrode and the n-type Al
The electric resistance between the cladding layer 37 and the _0.1 Ga _0.9 N layer 37 is reduced. Therefore, even when a plurality of elements are integrated on the same substrate and the n-type electrode is taken out from one end of the element as in the present element, each element is not inferior to a single element. The characteristics were shown.

In the third embodiment, the light emitting elements are arranged one-dimensionally, but it is also possible to arrange them two-dimensionally.

In the first to third embodiments, the light emitting element has been described. However, it is needless to say that the present invention can be applied to a light receiving element and an optical semiconductor modulation element. Of course, the concept of the present invention can be applied to an element obtained by mixing them. Further, in the above description, an InGaAlN-based material has been described, but the present invention is naturally applicable to other materials such as GaAs and InP. The composition is Ga _1-x Al _x
N (0 ≦ x ≦ 1) , In 1-yz Ga y Al z N (0 ≦ y,
z, y + z ≦ 1) can be appropriately selected. Further, although the n-type metal electrode is formed on the semiconductor layer having a small electron affinity, this electrode may be formed over the n-type electron supply layer having a large electron affinity. Also, as the substrate,
In addition to an insulating substrate (for example, the above-described sapphire), a semi-insulating substrate (for example, a semi-insulating InP substrate) can also be used.

[0020]

As described above, a sheet-like current path necessary for forming a semiconductor element formed on an insulating substrate is made up of a semiconductor layer having a small electron affinity and a semiconductor layer having a large electron affinity with impurities. There is an advantage that the resistance of the sheet-like current path can be remarkably reduced as compared with the conventional structure by using a structure in which are laminated. As a result, the temperature characteristics of the device can be improved, and a large current can be injected. In addition, the conversion efficiency between electricity and light is improved. Further, since it is not necessary to reduce the distance between the p and n electrodes, the manufacturing process is facilitated and the device manufacturing yield is improved. Further, there is an advantage that it is only necessary to form an n-type electrode on a part of the substrate when the elements are integrated. Further, by selecting the thickness of the layer structure, the current path can be turned off or turned on.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a semiconductor light emitting device according to the present invention.

FIG. 2 is a diagram showing a structure of a semiconductor light emitting device according to the present invention.

FIG. 3 is a diagram showing a structure of a one-dimensionally arranged semiconductor light emitting device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Sapphire (0001) substrate, 2 ... nitride layer, 3 ... G
aN buffer layer, 4 ... undoped GaN layer, 5 ... Si-doped n-type Al _0.14 Ga _0.86 N layer, 6 ... Si-doped n-type A
l _0.1 Ga _0.9 N layer, 7 ... Si-doped n-type GaN layer, 8 ...
An In _0.1 Ga multi-quantum well made of _0.9 N / GaN barrier layer, 9 ... Mg-doped p-type Al _0.2 Ga _0.8 N layer, 10 ... M
g-doped p-type GaN layer, 11 ... Mg-doped p-type Al _0.1
Ga _0.9 N layer, 12... Mg-doped p-type GaN layer, 13.
p-type metal electrode, 14: SiO ₂ layer, 15: n-type metal electrode, 16: sapphire (0001) substrate, 17: nitride layer, 18: GaN buffer layer, 19: undoped GaN
Layer, 20 ... Si-doped n-type Al _{0. 14} Ga _0.86 N layer, 21
... Si-doped n-type Al _0.1 Ga _0.9 N layer, 22 ... Si-doped n-type GaN layer, a multiple quantum well composed of _{23 ... In 0.1 Ga 0.9 N /} GaN, 24 ... Mg -doped p-type Al _0.2 Ga
_0.8 N layer, 25: Mg-doped p-type GaN layer, 26: Mg
Doped p-type Al _0.1 Ga _0.9 N layer, 27: Mg-doped p-type GaN layer, 28: p-type metal electrode, 29: SiO ₂ layer, 3
0 ... n-type metal electrode, 31 ... gate electrode, 32 ... sapphire (0001) substrate, 33 ... nitride layer, 34 ... GaN buffer layer, 35 ... undoped GaN layer, 36 ... Si-doped n-type Al _0.14 Ga _0.86 N layer, 37 ... Si-doped n-type Al
_0.1 Ga _0.9 N layer, multiple quantum wells composed of 38... In _0.1 Ga _0.9 N / GaN, 39... Mg-doped p-type Al _0.1 Ga
_0.9 N layer, 40... Mg-doped p-type GaN layer, 41.
Type metal electrode, 42: SiO ₂ layer, 43: n-type metal electrode.

Claims (2)

[Claims] In a semiconductor device formed on an insulating or semi-insulating substrate and having a conductive layer for allowing carriers to travel in a lateral direction below a laminated structure of an element portion, the conductive layer has an electron affinity. A semiconductor device comprising: a first semiconductor layer having a small size; and a second semiconductor layer having a high electron affinity to which impurities are added, which are stacked in this order. 2. The semiconductor device according to claim 1, wherein the first semiconductor layer is made of GaN, the second semiconductor layer is made of AlGaN, and at least one of the stacked structures of the element portion is made of InGaN. 2. The semiconductor device according to 1.