JPH1125697A - Semiconductor device and semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor storage device which reduce testing time. SOLUTION: In the test of a long cycle system of DRAM, a select circuit 1 combines the word line WLm which is to be tested and brought to a boost potential VPP by a line decoder 67 with a leak circuit 3. Since current leaks from the word line WLm and the potential of the word line WLm promptly lowers below the reference potential VR, it is rapidly discriminated whether the leakage of the word line WLm is present or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor memory device, and more particularly, to a semiconductor device and a semiconductor memory device having a test mode for testing whether or not power supply wiring is normal.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a conventional dynamic random access memory (hereinafter referred to as DRAM). Referring to FIG. 6, the DRAM includes control signal input terminals 51 to 53 and 55, an address signal input terminal group 54, a data signal input / output terminal group 56, and a ground terminal 57.
And a power supply terminal 58. Also, this DRAM is
VBB generation circuit 60, VSG generation circuit 61, VBL generation circuit 62, VPP generation circuit 63, and VDC generation circuit 6
4 is provided. The DRAM further includes a clock generation circuit 65, a row and column address buffer 66, a row decoder 67, a column decoder 68, a memory mat 69, an input buffer 72, and an output buffer 73.
9 includes a memory array 70 and a sense refresh amplifier + input / output control circuit 71.

[0003] VBB generation circuit 60, VSG generation circuit 6
1, VBL generating circuit 62, VPP generating circuit 63 and V
DC generation circuit 64 includes a charge pump circuit, and receives ground potential VSS and power supply potential VCC (for example, 5 V) from the outside via ground terminal 57 and power supply terminal 58,
Substrate potential VBB (-2V), cell potential VSG (1.5
V), bit line potential VBL (1.5 V), boosted potential (4
V) and an internal power supply potential VDC (3 V).

[0006] Clock generation circuit 65 receives a signal / RA externally applied through control signal input terminals 51 and 52.
A predetermined operation mode is selected based on S and / CAS, and D
It controls the entire RAM.

A row and column address buffer 66 receives a row address signal RA0 to RAi and a column address signal based on address signals A0 to Ai (where i is a natural number) externally applied through an address signal input terminal group 54. Generate signals CA0-CAi and generate signals RA0-RA0.
RAi and CA0-CAi are respectively applied to row decoder 67.
And the column decoder 68.

Memory array 70 includes a plurality of memory cells each storing 1-bit data. Each memory cell is arranged at a predetermined address determined by a row address and a column address.

Row decoder 67 has row and row address signals RA0-RA applied from row and column address buffer 66.
In response to i, the row address of the memory array 70 is specified. Column decoder 68 includes a row and column address buffer 6
6 designates a column address of the memory array 70 in response to the column address signals CA0 to CAi given from the controller 6.

A sense refresh amplifier + input / output control circuit 71 connects a memory cell at an address designated by a row decoder 67 and a column decoder 68 to one end of a data signal input / output line pair IOP. Data signal input / output line pair I
The other end of the OP is connected to the input buffer 72 and the output buffer 7.
3 is connected. In a write mode, input buffer 72 responds to an externally applied signal / W via control signal input terminal 53 to transmit data input from data signal input / output terminal group 56 to data signal input / output terminal pair IOP. To the selected memory cell via Output buffer 73
Outputs read data from the selected memory cell to data input / output terminal group 56 in response to signal / OE input from control signal input terminal 55 in the read mode.

FIG. 7 is a partially omitted circuit block diagram showing the configuration of the memory mat 69 of the DRAM shown in FIG.

Referring to FIG. 7, a memory array 70 includes a plurality of memory cells MC arranged in rows and columns, word lines WL provided corresponding to each row, and provided corresponding to each column. Bit line pair BL, / BL.

Each memory cell MC has, as shown in FIG.
An access N-channel MOS transistor 80 and a capacitor 81 for storing information are included. The gate of N channel MOS transistor 80 of each memory cell MC is connected to word line WL of the corresponding row. N channel MOS transistor 80 is connected to bit line BL or / B of the corresponding column.
L and one electrode (storage node SN) of capacitor 81 of memory cell MC. The other electrode of the capacitor 81 of each memory cell MC has a cell potential VS
Receive G. Word line WL transmits the output of row decoder 67 and activates memory cells MC in the selected row. Bit line pair BL, / BL inputs and outputs a data signal to and from selected memory cell MC.

The sense refresh amplifier + input / output control circuit 71 includes a column selection gate 7 provided corresponding to each column.
4. Sense refresh amplifier 75 and equalizer 7
6 inclusive. The column selection gate 74 is connected to the bit line pair B
It includes a pair of N-channel MOS transistors connected between L, / BL and data signal input / output lines IO / IO. N
The gate of the channel MOS transistor is connected to the column selection line CS
It is connected to the column decoder 68 via L. Column decoder 6
When the column selection line CSL is raised to the "H" level of the selection level by the pair 8, the pair of N-channel MOS transistors of the column selection gate 74 conducts, and the bit line pair BL, / B
L is coupled to data signal input / output line pair IO, / IO.

The sense refresh amplifier 75 internally stores a small potential difference between the pair of bit lines BL and / BL in response to the sense amplifier activation signals SE and / SE attaining the "H" level and the "L" level, respectively. Amplify to power supply voltage VDC. The equalizer 33 outputs a bit line equalize signal B
In response to LEQ attaining the “H” level of the activation level, the potentials of bit lines BL and / BL are changed to bit line potential VB.
Equalize to L.

Next, the operation of the DRAM shown in FIGS. 6 to 8 will be briefly described. In the write mode, column decoder 68 raises column select line CSL of a column corresponding to column address signals CA0 to CAi to an activation level of “H” level (boosted potential VPP) to set column select gate 74. Make it conductive.

In response to signal / W, input buffer 72 transfers write data from data signal input / output terminal group 56 to bit line pair BL, // of the column selected through data signal input / output terminal pair IOP. Give to BL. Write data is applied as a potential difference between bit lines BL and / BL. Next, row decoder 67 raises word line WL of the row corresponding to row address signals RA0 to RAi to the selected level “H” level (boosted potential VPP), and sets MO of memory cell MC of the row to the selected level.
The S transistor 80 is turned on. The capacitor 81 of the selected memory cell MC has the bit line BL or / B
An amount of charge corresponding to the potential of L is stored.

In the read mode, first, bit line equalize signal BLEQ falls to "L" level, and equalization of bit lines BL and / BL is stopped. Row decoder 67 raises word line WL of the row corresponding to row address signals RA0-RAi to the selected level “H”. The potentials of bit lines BL and / BL change by a small amount according to the amount of charge of capacitor 81 of activated memory cell MC.

Next, a sense amplifier activation signal SE, /
SE goes to “H” level and “L” level, respectively, and sense refresh amplifier 75 is activated. When the potential of bit line BL is slightly higher than the potential of / BL, the potential of bit line BL is raised to "H" level, and the potential of bit line / BL is lowered to "L" level. Conversely, when the potential of bit line / BL is slightly higher than the potential of bit line BL, the potential of bit line / BL is raised to "H" level and the potential of bit line BL is lowered to "L" level. .

Next, column decoder 68 raises column select line CSL of the column corresponding to column address signals CA0-CAi to the selected level "H" level, and conducts column select gate 74 of that column. The bit line pair BL in the selected column,
BL data is applied to output buffer 73 via column select gate 74 and data signal input / output line pair IO, / IO. Output buffer 73 outputs read data to data signal input / output terminal group 56 in response to signal / OE.

By the way, in such a DRAM, a cycle in which a normal operation is possible is defined by a shortest cycle and a longest cycle, and various tests such as a long cycle test and a disturb test are performed to guarantee the cycle.

In the long cycle system test, as shown in FIG. 9, the signal / RAS is set to the "L" level of the activation level for a time corresponding to the longest cycle, and one word line WL is set.
Is raised to the “H” level of the selection level. When the word line WL is normal, the potential of the word line WL is boosted potential V
Maintained at PP. If the word line WL is defective and a current leaks, the current supply capability of the VPP generation circuit 63 is insufficient, and the potential of the word line WL drops below the reference potential VR (for example, VPP / 2).

[0021]

However, in the conventional long cycle test, it is necessary to apply the "H" level to each word line WL at a time corresponding to the longest cycle. There was a problem that the cost was high.

Therefore, a main object of the present invention is to provide a semiconductor device and a semiconductor memory device capable of shortening the test time.

[0023]

The invention according to claim 1 is
An internal potential generation circuit for outputting an internal power supply potential; and a power supply line for receiving an output potential of the internal potential generation circuit. What is claimed is: 1. A semiconductor device having a test mode for determining whether or not a power supply wiring is normal based on a result, comprising: leak means for leaking a predetermined current from the power supply wiring; and coupling the power supply wiring and the leak means in the test mode. Connection means for making the connection.

According to a second aspect of the present invention, a plurality of sets of the internal potential generating circuit and the power supply wiring according to the first aspect of the invention are provided, and the semiconductor device further includes a plurality of sets of the internal potential generating circuit and the power supply wiring. Selecting means for selecting the set; and the connecting means couples the power supply wiring of the set selected by the selecting means and the leak means.

According to the third aspect of the present invention, the leak current of the leak means according to the first or second aspect of the invention can be adjusted.

According to a fourth aspect of the present invention, the leakage means according to the third aspect of the present invention provides a plurality of parallel-connected paths through which different currents flow, and an electric connection between one of the plurality of paths. And adjusting means for adjusting the leak current.

According to a fifth aspect of the present invention, a plurality of memory cells arranged in a matrix, a word line provided corresponding to each row, a bit line pair provided corresponding to each column, and A memory array including a column selection line provided corresponding to a bit line pair, a row decoder for selecting any word line in the memory array in accordance with a row address signal and setting the word line to a selection potential, and a column A column decoder for selecting one of the column selection lines in the memory array in accordance with the address signal and setting the column selection line to a selection potential; detecting a potential of the word line selected by the row decoder; 1. A semiconductor memory device having a test mode for judging whether or not a word line is normal based on a leak means for causing a predetermined current to leak from a word line, and It is characterized by comprising a connecting means for coupling the word line and a leak means selected by the row decoder at.

According to a sixth aspect of the present invention, a plurality of memory cells arranged in a matrix, a word line provided corresponding to each row, a bit line pair provided corresponding to each column, and A memory array including a column selection line provided corresponding to a bit line pair, a row decoder for selecting any word line in the memory array in accordance with a row address signal and setting the word line to a selection potential, and a column A column decoder for selecting one of the column selection lines in the memory array according to the address signal and setting the column selection line to a selection potential; detecting a potential of the column selection line selected by the column decoder; A memory device having a test mode for judging whether or not a column selection line is normal based on a test circuit, wherein a leak means for causing a predetermined current to leak from the column selection line; Dude is characterized by comprising a connecting means for coupling the column selecting line and the leakage circuit selected by the column decoder.

In the invention according to claim 7, the leak current of the leak means according to claim 5 or 6 can be adjusted.

According to an eighth aspect of the present invention, the leakage means according to the seventh aspect of the present invention is configured to conduct a plurality of parallel-connected paths through which different currents flow and any one of the plurality of paths. And adjusting means for adjusting the leak current.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a partially omitted circuit block diagram showing a main part of a DRAM according to a first embodiment of the present invention.

Referring to FIG. 1, this DRAM is a conventional DRAM.
The difference from the RAM is that a select circuit 1 and a leak circuit 3 are newly provided. Select circuit 1
Are N-channel MOS transistors 2.1 to 2... Provided corresponding to word lines WL1 to WLm (m is a natural number). m. N channel MOS transistors 2.1 to 2. m is the corresponding word line WL1
WLm and the output node N1 of the select circuit 1, and each gate is connected to a select signal φ2.1.
~ Φ2. m.

Select signals φ2.1 to φ2. “m” is a signal that becomes an “H” level of an activation level at the time of a long cycle test of the corresponding word lines WL1 to WLm, and is generated by, for example, a well-known address key circuit. Leak circuit 3 is connected between output node N1 of select circuit 1 and ground potential V
Including the resistance element 4 connected between the line of SS.

FIG. 2 is a time chart for explaining the operation of this DRAM at the time of a long cycle test in comparison with a conventional DRAM. Referring to FIG. 2, signal / R
AS falls to the “L” level of the activation level, for example, select signal φ2. m rises to the activation level “H” level, and the word line WLm to be tested rises to the selected level “H” level. Accordingly, N-channel MOS transistor 2. m
Are turned on, and N channel MOS transistors 2.. m and the ground potential VS through the leak circuit 3.
Current leaks to the S line.

As a result, even when the word line WLm is normal, the current supply capability of the VPP generation circuit 63 is insufficient, and the potential of the word line WLm decreases. If the word line WLm is defective and there is a current leak, the word line WL
The potential of Lm decreases. Therefore, the test time can be shortened by Δt in FIG.

[Second Embodiment] FIG. 3 is a circuit diagram showing a configuration of a main part of a DRAM according to a second embodiment of the present invention.

Referring to FIG. 3, this DRAM differs from the DRAM of the first embodiment in that leak circuit 3 is replaced by leak circuit 10. The leak circuit 10
Select circuit 11 includes resistance elements 15 to 17, and select circuit 11 includes N-channel MOS transistors 12 to
14 inclusive. The N-channel MOS transistor 12 and the resistance element 15, the N-channel MOS transistor 13 and the resistance element 16, and the N-channel MOS transistor 14 and the resistance element 17 are connected to the output node N of the select circuit 1 in FIG.
1 and the line of the ground potential VSS.
The gates of the N-channel MOS transistors 12 to 14
Receiving select signals φ12 to φ14, respectively.

Select signals .phi.12 to .phi.14 are signals that at the time of a long cycle test of word lines WL1 to WLm, one of them becomes an active level of "H" level. Generated by the circuit. The size of the symbol of each of the resistance elements 15 to 17 in FIG. 3 indicates the magnitude of its resistance value.
The resistance values of No. to No. 17 are sequentially reduced.

In the test mode, when signal φ12, φ13 or φ14 rises to the activation level “H”,
N-channel MOS transistor 12, 13 or 14 conducts, and output node N1 of select circuit 1 is connected to resistance element 1
5, 16, or 17 is connected to the ground potential VSS line. Therefore, it is possible to adjust the amount of leak of leak circuit 10 by adjusting which of signals φ12 to φ14 is set to the activation level “H” level, and to adjust the test time and the rejection rate of failure. Can be.

[Third Embodiment] FIG. 4 is a partially omitted circuit block diagram showing a main part of a DRAM according to a third embodiment of the present invention.

Referring to FIG. 4, this DRAM is a conventional DRAM.
The difference from the RAM is that a select circuit 20 and a leak circuit 3 are newly provided. Select circuit 2
0 are N-channel MOS transistors 21.1 to 21.n provided corresponding to column select lines CSL1 to CSLn (n is a natural number). n. N-channel MO
S transistors 21.1 to 21. n are connected between the corresponding column select lines CSL1 to CSLn and the output node N20 of the select circuit 20, respectively, and each gate is connected to a select signal φ21.1 to φ21. n.

Select signals φ21.1 to φ21. n is
These signals are activated to an "H" level at the time of a long cycle test of the corresponding column select lines CSL1 to CSLn, and are generated by, for example, a well-known address key circuit. Leak circuit 3 includes a resistance element 4 connected between output node N20 of select circuit 20 and a line of ground potential VSS.

In the long cycle system test, for example, select signal φ21. n rises to the “H” level of the activation level, and the column selection line CSL to be tested is
n rises to the selected level "H". Accordingly, N-channel MOS transistors 21. n is conducted, and the ground potential VS is supplied from the column selection line CSLn through the leak circuit 3.
Current leaks to the S line.

As a result, even when the column selection line CSLn is normal, the current supply capability of the VPP generation circuit 63 is insufficient, and the potential of the column selection line CSLn decreases. When the column selection line CSLn is defective and there is a current leak, the potential of the column selection line CSLn decreases more quickly. Therefore, the test time can be reduced as compared with the related art.

[Fourth Embodiment] FIG. 5 is a circuit block diagram showing a configuration of a main part of a DRAM according to a fourth embodiment of the present invention.

Referring to FIG. 5, this DRAM is a conventional DRAM.
The difference from the RAM is that a select circuit 40 and a leak circuit 3 are newly provided. Select circuit 4
0 includes N-channel MOS transistors 40 to 44 provided corresponding to power supply lines 30 to 34, respectively.
The power supply wirings 30 to 34 are respectively connected to the VBB generation circuit 60,
Output potentials VBB of VSG generation circuit 61, VBL generation circuit 62, VPP generation circuit 63 and VDC generation circuit 64,
VSG, VBL, VPP and VDC are received.

N channel MOS transistors 40-44
Are connected between corresponding power supply lines 30 to 34 and output node N40 of select circuit 40, and their gates receive select signals φ40 to φ44, respectively. The select signals φ40 to φ44 correspond to the corresponding power supply lines 30 to 3
4 is a signal which becomes an activation level "H" level in a long cycle system test of 4, and is generated by, for example, a well-known address key circuit. Leak circuit 3 includes a resistance element 4 connected between output node N40 of select circuit 40 and a line of ground potential VSS.

In the long cycle system test, for example, select signal φ43 rises to the active level of “H”, and power supply line 33 to be tested rises to boosted potential VPP. In response, N-channel MOS transistor 43 conducts, and current leaks from power supply line 33 to line of ground potential VSS via leak circuit 3.

As a result, even when the power supply wiring 33 is normal, the current supply capability of the VPP generating circuit 63 is insufficient, and the potential of the power supply wiring 33 decreases. When the power supply wiring 33 is defective and there is a current leak, the potential of the power supply wiring 33 decreases more quickly. Therefore, the test time can be shortened as compared with the related art.

[0050]

As described above, according to the first aspect of the present invention, in the test mode, the power supply wiring is coupled to the leak means to leak a predetermined current from the power supply wiring. Therefore, the potential of the power supply wiring can be reduced more quickly than before, and the test time can be reduced.

According to a second aspect of the present invention, a plurality of sets of the internal potential generating circuit and the power supply wiring according to the first aspect of the present invention are provided, and the set of power supply wirings selected by the selection means and the leakage means are connected. Therefore, even when there are a plurality of sets of the internal potential generating circuit and the power supply wiring, only one leak means is required.

In the invention according to claim 3, the leak current of the leak means according to claim 1 or 2 can be adjusted. In this case, the test time and the rejection rate of the defect can be adjusted by adjusting the leak current.

According to a fourth aspect of the present invention, the leakage means according to the third aspect of the present invention makes the plurality of parallel-connected paths through which different leak currents flow, and any one of the plurality of paths conductive. Adjusting means for adjusting the leakage current. Therefore, the leak means can be easily configured.

In the invention according to claim 5, the word line to be tested is coupled to the leak means in the test mode, and a predetermined current is leaked from the word line. Therefore, the potential of the word line can be reduced more rapidly than in the prior art, and the test time can be reduced.

In the invention according to claim 6, in the test mode, the column selection line to be tested is coupled to the leak means, and a predetermined current is leaked from the column selection line. Therefore, the potential of the column selection line can be reduced more quickly than before, and the test time can be reduced.

In the invention according to claim 7, the leak current of the leak means according to claim 5 or 6 can be adjusted. In this case, the test time and the rejection rate of the defect can be adjusted by adjusting the leak current.

According to an eighth aspect of the present invention, the leakage means according to the seventh aspect of the present invention is configured to make a plurality of parallel-connected paths through which different leak currents flow, and any one of the plurality of paths conductive. Adjusting means for adjusting the leakage current. Therefore, the leak means can be easily configured.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a main part of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a time chart for explaining an operation and an effect of the DRAM shown in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of a main part of a DRAM according to a second embodiment of the present invention;

FIG. 4 is a circuit diagram showing a configuration of a main part of a DRAM according to a third embodiment of the present invention;

FIG. 5 is a circuit block diagram showing a configuration of a main part of a DRAM according to a fourth embodiment of the present invention.

FIG. 6 is a circuit block diagram showing a configuration of a conventional DRAM.

FIG. 7 is a partially omitted circuit block diagram showing a configuration of a memory mat of the DRAM shown in FIG. 6;

FIG. 8 is a circuit diagram showing a configuration of a memory cell shown in FIG. 7;

FIG. 9 is a time chart for explaining a problem of the DRAM shown in FIG. 6;

[Explanation of symbols]

1, 11, 20, 35 select circuit, 2.1 to 2.
m, 12-14, 21.1-21. n, 41-44, 8
0 N-channel MOS transistor, 3,10 leak circuit, 4,15-17 resistance element, 30-34 power supply wiring, 51-53,55 control signal input terminal, 54 address signal input terminal group, 56 data signal input / output terminal group ,
57 ground terminal, 58 power supply terminal, 60 VBB generation circuit, 61 VSG generation circuit, 62 VBL generation circuit, 63
VPP generation circuit, 64 VDC generation circuit, 65 clock generation circuit, 66 row and column address buffers, 6
7 row decoder, 68 column decoder, 69 memory mat, 70 memory array, 71 sense refresh amplifier + input / output control circuit, 72 input buffer, 73 output buffer, 74 column select gate, 75 sense refresh amplifier, 76 equalizer, 81 capacitor, MC
Memory cell, WL1 to WLm word line, BL, / B
L bit line pair, CSL1 to CSLn column select line, I
O, / IO (IOP) Data signal input / output line pair.

Claims (8)

[Claims] An internal potential generation circuit for outputting an internal power supply potential; and a power supply line receiving an output potential of the internal potential generation circuit, wherein the power supply is provided after an output potential of the internal potential generation circuit is applied to the power supply line. A semiconductor device having a test mode for detecting a potential of a wiring and determining whether or not the power supply wiring is normal based on a result of the detection, a leak unit for causing a predetermined current to leak from the power supply wiring, and A semiconductor device including a connection unit that couples the power supply line and the leakage unit in the test mode. 2. The semiconductor device according to claim 2, wherein a plurality of sets of the internal potential generating circuit and the power supply wiring are provided. 2. The semiconductor device according to claim 1, wherein the connection unit couples a set of power supply wires selected by the selection unit with the leakage unit. 3. 3. The semiconductor device according to claim 1, wherein a leak current of said leak means is adjustable. 4. The leaking means includes a plurality of paths connected in parallel to flow different leak currents from each other, and an adjusting means for adjusting the leak current by conducting any one of the plurality of paths. The semiconductor device according to claim 3. 5. A plurality of memory cells arranged in a matrix, a word line provided corresponding to each row, a bit line pair provided corresponding to each column, and a bit line pair corresponding to each bit line pair. And a row decoder for selecting any word line in the memory array according to a row address signal and setting the word line to a selection potential, and the memory according to a column address signal. A column decoder for selecting one of the column selection lines in the array and setting the column selection line to a selection potential; detecting a potential of the word line selected by the row decoder; What is claimed is: 1. A semiconductor memory device having a test mode for determining whether or not a word line is normal, comprising: a leak unit for causing a predetermined current to leak from said word line; 2. The semiconductor memory device according to claim 1, further comprising connection means for connecting the word line selected by said row decoder and said leak means. 6. A plurality of memory cells arranged in a matrix, a word line provided for each row, a bit line pair provided for each column, and a bit line pair corresponding to each bit line pair. And a row decoder for selecting any word line in the memory array according to a row address signal and setting the word line to a selection potential, and the memory according to a column address signal. A column decoder for selecting one of the column selection lines in the array and setting the column selection line to a selection potential; detecting a potential of the column selection line selected by the column decoder; What is claimed is: 1. A semiconductor memory device having a test mode for determining whether or not a column select line is normal, comprising: a leak unit for causing a predetermined current to leak from the column select line; 3. A semiconductor memory device according to claim 1, further comprising connection means for connecting a column selection line selected by said column decoder and said leak means. 7. The semiconductor memory device according to claim 5, wherein a leak current of said leak means is adjustable. 8. The leak unit includes: a plurality of paths connected in parallel to flow different currents; and an adjusting unit that adjusts the leak current by conducting any one of the plurality of paths. Claim 7
3. The semiconductor memory device according to claim 1.