JPH11252110A - Decelerator - Google Patents

Abstract

(57) Abstract: The present invention relates to a decellularization device in a cell communication system, which compensates for time-series deviation when performing decellulation and reduces the processing time of a data write / read cycle. It is an object of the present invention to realize a decelerating device capable of performing the above. A data buffer including a main signal data area, a control information area for storing control information for each channel at the same address as the main signal data area in which the main signal data is written, a header processing unit, and a cell A cell loss compensation unit for compensating for the lost data in the channel when a loss occurs, a write control unit for controlling data writing to the data buffer, and the number of dummy data transmitted when an underflow occurs in the data buffer And a read control unit for controlling the reading of the data buffer based on the cell loss information notified from the write control unit and the number of transmitted dummy data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell communication system in which information to be transmitted is divided into fixed-length data and communication is performed in a cell in which destination information is added to the divided data, and is accommodated in a received cell. The present invention relates to a decelerator for converting data into a predetermined digital communication format and outputting the converted data.

In digital communication, packet communication and ATM (Asynchronous T
(ransfer Mode, asynchronous transfer mode) communication is adopted. For example, in ATM communication, data having various speeds is divided into fixed-length data called cells, and communication is performed by adding control information called a header to each of the divided fixed-length data. . In the ATM communication system, since various types of data having various traffic characteristics such as voice, digital data, and moving image data can be integrally processed, an ATM communication network is being constructed as an infrastructure of multimedia communication.

[0003] Existing STM mainly using telephones
(synchronus Transfer Mode)
It can also be accommodated in a TM network. In such a case, IWF (Interworking Facility) or CLAD (Cell
STM-ATM called Assembly and Disassembly)
The conversion device performs mutual conversion between STM data and ATM cells, and transfers data through the ATM network.

There is a need for a decellularization device that can efficiently perform such decellularization processing for converting such cell data into digital synchronous data.

[0005]

2. Description of the Related Art FIG. 20 illustrates a conventional example (part 1).
Is shown. In the figure, 110B is a data buffer for storing received ATM cell data, 610A is a control information memory for storing control information for each channel, and 200B.
Is a header processing unit for converting a received cell header into a channel number.

Reference numeral 300 denotes a data buffer 110B,
A write control unit controls writing of main signal data and control information to the control information memory 610A, and a read control unit 400 controls reading of the main signal data and control information to the data buffer 110B and the control information memory 610A.

[0007] In the configuration shown in FIG.
The header of the M cell is extracted, and the header information is converted into a channel number. In the header, a source number, a destination number, a cell sequence number, a priority, and the like are written as control information. These control information is stored in a control information memory for each channel number under the control of the write control unit 300. 6
10A, and the main signal data is written in the write controller 300.
Is written to the data buffer 110B for each channel number according to the control of. The data in the data buffer 110B is read under the control of the read control unit 400,
Output as TM data.

In an ATM network, an AT in the network
ATM cells fluctuate due to delays caused by transfer routes of M cells, contention control of buffers, and the like. Therefore, when decelerating ATM cells into STM data, it is necessary to absorb the fluctuations of the ATM cells in parallel with the cell disassembly process.

FIG. 21 is a diagram (part 2) for explaining a conventional example. Data buffer 110B in the figure, header processing unit 2
00, the write control unit 300 is the same component as described in FIG. The read control unit 400 includes a threshold memory 440 for setting a threshold of the number of cells in the data buffer 110B for absorbing fluctuation. In the figure, the control information memory 610A is not shown.

[0010] In the configuration shown in FIG.
The header of the M cell is extracted, the header information is converted into a channel number, and the main signal data is written to the data buffer 110B for each channel number. The read control unit 400 compares the number of data in the data buffer 110B with the threshold value of the threshold value memory 440 and performs reading.

[0011]

In recent years, in order to efficiently communicate, the speed of a transmission line has been increased.
/ s, 622 Mb / s, etc., have been put into practical use, and the number of channels multiplexed in the transmission path has been increasing. A transfer has been requested.

In order to solve such a problem, in the above-mentioned conventional example (No. 1), the received cell is separated into a header portion and main signal data, and the main signal data and the header are respectively shared by the data buffer 110B and the control information memory 610A. Write to address. When reading the data of the specified channel, the control information of the address corresponding to the specified channel in the control information memory 610A is first read, and the main signal of the corresponding address of the data buffer 110B is read according to the content of the control information. Since the data is read, there arises a problem that the processing time for the reading becomes long.

Further, in the conventional example (No. 2), the same fluctuation absorption processing is performed on all the channels as a decelerating device. However, since the cells received by the decelerating apparatus have different transfer paths for each cell (call), the fluctuation occurring in the network is not constant, and the width of the fluctuation occurring for each channel is different. Therefore, if the fluctuation is to be absorbed with the maximum fluctuation width generated in a plurality of channels, the delay increases, which is a problem for a call requiring real-time characteristics such as voice.

The present invention compensates for time-series deviations when restoring digital synchronous communication data from a cell, shortens the processing time of a data write / read cycle, and reduces the processing time for each channel. An attempt is made to realize a decelerating device capable of performing a fluctuation absorbing process.

[0015]

FIG. 1 is a diagram for explaining the first principle of the present invention, and shows a decellularizing apparatus for converting a plurality of cells into digital synchronization data of a plurality of channels.

In the figure, reference numeral 100 denotes a main signal data area 120 for identifying a cell based on the header information of the input cell and storing a main signal of input data for each channel, and a main signal data area 120 in which main signal data is written. Is a data buffer comprising a control information area 110 for storing control information for each channel at the same address as the above. Reference numeral 200 denotes a header processing unit for converting header information into a channel number and identifying a sequence number.

In addition, when a cell loss occurs, a cell loss compensation unit 3 compensates the lost data for the channel.
A write controller 400 for controlling data writing to the data buffer 100; and 400, a dummy data number holding unit 41 for holding the number of transmitted dummy data for each channel when an underflow occurs in the data buffer 100.
0, the data buffer 1 is determined by the cell loss information notified from the write control unit 300 and the number of dummy data transmitted.
It is a read control unit that performs read control of 00.

In this configuration, the header of the received cell is converted into a channel number by the header processing unit 200, the continuity of the cell is checked from the sequence number of the header, and the result is sent to the write control unit 300. . The write control unit 300 performs an operation so as to compensate the time series from the control information and the determination result of the continuity of the cells, and writes the result to the data buffer 100 and the main signal data.

The read control unit 400 reads the control data of the data buffer 100 corresponding to the channel number and the number of transmitted dummy data, performs an operation so as to compensate for the time series, and stores the result in the control information area of the data buffer 100. Write to 110. If there is no data in the data buffer 100, the read information is, for example, all bits 1
And output it.

With such an operation, it is possible to shorten the processing time for writing / reading data. (Claim 1) FIG. 2 is a view for explaining a second principle of the present invention. The figure shows a decellularizing device for converting a plurality of cells into digital data of a plurality of channels.

In the figure, reference numeral 100 denotes a data buffer for storing input data for each channel, reference numeral 200 denotes a header processing unit for identifying a cell based on the header information of the input cell and converting it into a channel number, and reference numeral 300 denotes a data processing unit. A write control unit that controls writing of data to the buffer 100.

Reference numeral 400 denotes a read control unit for controlling the reading of data from the data buffer 100;
Reference numeral 0 denotes a per-channel fluctuation permissible value processing unit that sets a permissible value of cell transfer fluctuation per channel.

In this configuration, the header of the received cell is extracted by the header processing unit 200 to extract the channel number.
The cell data is written to the data buffer 100 under the control of the write controller 300. The read control unit 400 reads and sets the permissible fluctuation value set in the per-channel fluctuation permissible value processing unit 420 at the time of call setting. When there is a read request, the read is performed after waiting for the time of the allowable value set in the control memory.

With such an operation, a fluctuation allowable value is set for each channel, and the fluctuation can be absorbed at the time of reading, so that communication with low delay can be performed. (Claim 2)

[0025]

FIG. 3 shows an embodiment (1--) of the present invention.
It is a figure explaining 1). The figure shows a decellularizing device for converting a plurality of cells into digital synchronization data of a plurality of channels. In the following embodiments, the cells are ATM cells, and the digital synchronous communication system is STM.

A data buffer 100 includes a main signal data area 120 and a control information area 110.
Reference numeral 20 denotes a header table storing the correspondence between the VPI and VCI of the header part of the cell and the channel number. Reference numeral 210 denotes a header conversion unit that extracts a channel number from the header by referring to the header table 220. Reference numeral 230 denotes a header conversion unit. A cell continuity determination unit that determines cell continuity from the extracted SN (Sequence Number), an SN table 240 in which an expected value of the SN for each channel to be referred to at the time of continuity determination is written, and 300 is a SN table. Write control unit,
400 is a read control unit.

In the configuration shown in the figure, the write control unit 300 uses a WP / RP (Write Pointer / Read Po
inter) read out the write pointer WP from the table 320, read out the buffer state, data loss information and information on the number of STM dummy data transmitted when an underflow occurs from the data buffer 100, using the channel number as the upper address and WP as the lower address. . Then, the cell loss compensation unit 310 performs an operation to compensate for the time series based on the information in the data buffer 100 and the result of the determination of the continuity of the cells, and stores the result in the data buffer 100.

The read control unit 400 refers to the TS / CH (TimeSlot / Channel) table 430 based on the time slot number, and uses the WP /
The read pointer RP is read from the RP table 320, and the stored data, the buffer state, the data loss information, and the dummy data number holding unit 410 are read from the data buffer 100 using the channel number as the upper address and the read pointer RP as the lower address. The information of the number of STM dummy data transmitted when an underflow occurs is read out, and is calculated to compensate for the time series, and the result is stored in the data buffer 100. If there is no data in the data buffer 100, the read data is replaced with, for example, all-bit 1 dummy data and output.

With this processing, it is possible to reduce the processing time for writing / reading data. FIG. 4 is a diagram illustrating a configuration of the data buffer according to the embodiment (1-1) of the present invention.

The control information written in the data buffer 100 shown in FIG. OVR; indicates an overflow of the data buffer 100;
“1” indicates an overflow, and “0” indicates no overflow. When writing the main signal data, the write control unit 30
At 0, if EN = “1” in the control information read from the data buffer 100, OVR is updated to “1” and written to the data buffer 100. If EN = "0", the OVR is not updated.

At the time of reading main signal data, read control unit 4
At 00, if OVR = “1” in the control information read from the data buffer 100, OVR is updated to “0” and written to the data buffer 100. OVR =
If "0", the OVR is not updated.

EN: Data buffer 10 of the address
0 indicates the presence or absence of data, "1" indicates that there is data,
“0” indicates no data. At the time of writing the main signal data, the write control unit 300 updates EN = “1” only when EN = “0” and satisfies Expression (1) based on the control information read from the data buffer 100, Write, otherwise do not update EN.

(Arrival cell loss number × C−LOS) × 47 + B−LOS ≧ C−DMY × 47 + B−DMY (1) When reading main signal data, the read control unit 400 reads from the data buffer 100. Of the control information, OVR
= "0" and C-LOS = C-DMY and B-LO
Only when S = B-DMY is EN updated to "0" and written to the data buffer 100. Otherwise, do not update EN.

C-LOS: Indicates the number of lost data in cell units. When writing the main signal data, the write control unit 300
CL of control information read from data buffer 100
A value obtained by adding the cell loss number notified from the cell continuity determination unit 230 to the OS is updated as the C-LOS, and written into the data buffer 100.

When the main signal data is read, the read control unit 4
In the case of 00, an operation is performed to compensate the time series based on the result of determination of continuity and the result is stored in the data buffer 100.
In the read control unit 400, C-LOS = C-DM
The initial value "0" is written to the data buffer 100 only when Y and B-LOS = B-DMY. Otherwise, the C-LOS is not updated.

B-LOS: Indicates the number of lost data in byte units. 0 ≦ B-LOS ≦ 46 (in the case of AAL Type 1) At the time of writing the main signal data, the write control unit 300 uses the control information read from the data buffer 100 as (1)
Only when the expression is not satisfied, the value is updated by adding “+1” and written to the data buffer 100. Otherwise, B-LOS
Do not update

When the main signal data is read, the read control section 400 sets C-LOS = C-DMY and BL-L
The initial value “0” is written to the data buffer 100 only when OS = B-DMY. Otherwise, B-LOS
Does not update.

C-DMY: Indicates the number of STM dummy data transmitted when an underflow occurs in a cell unit. The write controller 300 does not update C-DMY.

At the time of reading main signal data, read control unit 4
In 00, C-LOS = C-DMY and B-LOS =
The initial value “0” is written to the data buffer 100 only for B-DMY, and the value updated to “+1” otherwise, when B-DMY = 46.

B-DMY: Indicates the number of STM dummy data transmitted when an underflow occurs in byte units. 0 ≦ B−
LOS ≦ 46 (in the case of AAL Type 1) The write controller 300 does not update the B-DMY.

At the time of reading main signal data, read control unit 4
In 00, C-LOS = C-DMY and B-LOS =
The initial value “0” is written to the data buffer 100 only for B-DMY, and the value updated to “+1” otherwise, when B-DMY = 46.

FIGS. 5 to 7 show an embodiment (1-1) of the present invention.
2 shows the control information (Nos. 1 to 3) of the data buffer of FIG. The figure illustrates the operation of writing / reading data in the control information area for one channel, and the operation is the same for other channels.

In the figure, OVER is OV and C-LOS is C
BL for L, B-LOS, CD for C-DMY, B-DMY
Are denoted by BD, and the main signal data is denoted by DT. Also, the control information enclosed by the thick line frame is different from the previous control information.

(1): The write pointer WP and the read pointer RP indicate the same address, each parameter is "0", indicating an initial state. (2); Data read request was issued, but EN = "0"
Since there is no data in the data buffer 100, as an underflow, the BD is updated by "+1". At this time, the read pointer RP remains as it is,
As data, for example, dummy data of all bits = 1 is transmitted.

(3): The state of (2), that is, the state in which the underflow state is repeated 46 times. (4): A state in which underflow has occurred 48 times. 4
In the state where the seventh underflow occurs, CD =
“0”, BD = “46”, and when updating, the CD
= “1” and BD = “0”.

(5); When a cell arrives after the state of (4) and is notified by the cell continuity determining unit 230 that a loss of two cells has occurred, the updated state of each parameter is changed. Show. The value of each parameter when reading the data buffer 100 at the address is CD = “1”, BD = “1”
, And the loss information is “2” cells. Therefore, since the loss information> the number of dummy data, the arriving cell is stored in the data buffer 100. Here the write pointer WP
Are control information of CL = “2” and EN =
“1”, CD = “1”, BD = “1”, and stored together with one byte of main signal data. Further, the write pointer WP is updated by adding “+1”.

(6): The operation of sequentially writing the next byte of the main signal data stored in (5) will be described. (7), (8); data buffer 1 after state (6)
The case where there is a read request instruction of 00 is shown. The operation of comparing the values of CL, CD, BL, and BD by a read control unit (not shown) and outputting dummy data until CL = CD and BL = BD is shown. Here, dummy data up to DM-93 in the figure is output.

(9) According to the control information read from the data buffer 100, since CL = CD and BL = BD, the number of losses = the number of dummy data, the time series compensation is completed, and EN = “1” From "Data Buffer 1"
Since the main signal data is stored in 00, the main signal data at the address is read out, and all control information is updated as the initial state of all bits “0”.

8 to 11 show an embodiment of the present invention (1-
The control information (4 to 7) of the data buffer in 1) is shown, and the operation when an overflow / underflow occurs is shown.
(1), (2): Same as the operation in FIG.

(3): A state in which the underflow has occurred twice and the control information BD = “2” has been written. In this case, one byte of the main signal data is discarded, and BL indicating the number of discarded bytes is updated by adding “+1” to the data buffer 1.
Write to 00. Then, CL = CD and BL = BD
This operation is repeated until (4).

(5); Since CL = CD and BL = BD, it is assumed that the time series compensation has been completed, and data writing is started from this point. The control information read from the data buffer 100 is BL = “2”, BD = “2”
Since the others are “0”, the number of losses = the number of dummy data, and EN = “1” to write the main signal data to the data buffer 100 and simultaneously write the write pointer WP
To “+1” and update.

In (6), since the number of losses = the number of dummy data, EN = “1” and the main signal data is written to the data buffer 100, and the write pointer WP is set to “+”.
1 "to update.

(7) to (9) show a normal read operation. Since each control information read from the data buffer 100 at the time of a read request of the data buffer 100 is "0" except for EN, the number of losses = E is the number of dummy data
Since N = “1”, there is data in the data buffer 100 and the data read from the data buffer 100 is output. The read address of the data buffer 100 is updated by setting the EN = “0” indicating no data, updating the data buffer 100, and updating the write pointer WP by “+1”.

(10) shows the operation when an overflow occurs. At the time of a data write request, since the EN of the control information read from the data buffer 100 is “1”, it is determined that an overflow of the data buffer 100 has occurred, and
V is updated to "1" and written to the data buffer 100. The main signal data at this time is discarded.

(11) shows a read operation in the overflow state. When the data read request is issued, the data buffer 10
Since the OV in the control information read from 0 is “1”, it is determined that the data buffer 100 is in the overflow state, and the OV is updated to “0” and written to the data buffer 100. At this time, the main signal data read from the data buffer 100 is output as valid STM data.

FIG. 12 is a diagram for explaining the embodiment (1-2) of the present invention. The figure shows a decellularizing device for converting a plurality of cells into digital synchronization data of a plurality of channels.
In FIG. 3, the data buffer 100 is divided and the divided area is allocated to each channel according to the individual buffer method. However, when the number of channels increases with the speeding up of the transmission path, a large-capacity data buffer 100 is required. Becomes Therefore, in the embodiment (1-2), a common buffer method is used to reduce the capacity of the data buffer 100, and an address first-in first-out memory (first-in first-out memory) that performs first-in first-out processing on the address memory in order to reduce the write / read processing time (FIFO) 600.

A data buffer 100 as a common buffer having a main signal data area 120 is a header conversion unit 210, a header table 220, a cell continuity determination unit 230, an SN table 240, and a write control unit. 300, read control unit 400, TS / CH table 4
Reference numeral 30 denotes the same component as that described with reference to FIG.

Further, in the embodiment (1-2), a write address FIFO 600, a management table 610, and a chain memory 620 are provided, and the write control unit 300 receives an address for storing main signal data from the write address FIFO 600. .

The control information for writing data is read from the management table 610 storing the control information based on the channel number. At this time, if data has already been stored in the data buffer 100, the storage area specified from the address FIFO 600 is written to the chain memory 620. At the same time, the data is stored at the address specified by the address FIFO 600.

The read control unit 400 reads the corresponding channel number by referring to the TS / CH table 430 based on the time slot number, and reads the STM data of the channel in the management table 610 according to the channel number. Read management information for reading. Based on the read management information or when a chain is formed without data according to the buffer status information in the management table 610, the storage address and cell loss information of the next data are read by the chain memory 620, The optimum data read position is calculated, and the data buffer 100
The corresponding data is read from. At the same time, the calculation result is written into the management table 610.

If there is no data and no chain is formed according to the buffer status information in the management table 610, for example, dummy data of all bits 1 is sent out.
The number of transmitted dummy data is held in the management table 610.

FIG. 13 is a diagram for explaining the configuration of the management table and the chain memory according to the embodiment (1-2) of the present invention. In the management table 610, the start address START of the chain in which the data is written, the end address END of the chain, the read pointer RP, the number of lost data per cell C-LOS, the number of dummy data per cell C-DMY,
The number of dummy data B-DMY in byte units is written.

In the chain memory 620, an address is specified for each channel to which data has been written, and the next address NEXT in which the next data is written and the number of dummy data C-LOS per cell are written.

FIGS. 14 to 17 show an embodiment of the present invention (1-
The control information (1 to 4) of the management table / chain memory of 2) is shown. In the figure, the user data length in the cell is 47 bytes. Further, in the figure, the start address START is set to ST, and the last address END is set to E
D, next address NEXT indicates NT, RP, CL, C
D and BD are the same as in FIGS.

(1) Each management data is "0", indicating an initial state. (2); STM data read request was issued, but EN =
Since there is no data in the data buffer 100 at "1", the BD is set to "+1" as an underflow. At this time, the read pointer RP = "0". The data outputs dummy data.

(3): A state in which the state of (2) is repeated 46 times. (4): This indicates a state in which 48 bytes of dummy data have been transmitted since there are 48 STM data read requests and an underflow state. In this case, CD = “0” and BD = “4” read when the dummy data of the 47th byte is transmitted.
6 ”, and CD =“ 1 ”and BD =
Writing is performed as "0".

(5): When the cell of the channel arrives after the state of (4) and there is a data write instruction, and the cell continuity determining unit 230 notifies the cell continuity determination unit 230 of the loss of "2" cells. , Shows the state after the management data is updated.

First, the value of each control information at the time of reading each control information of the management data is CD = “1”, BD = “1”, and the others are “0”. Therefore, since loss information> dummy number, the arrival cell is stored. The buffer area "6" for storing the arrival cell is designated by the write address memory, ST = ED = 6, and EN = "1" indicating that there is data in the buffer is written in the management table.

(6), (7); The dummy count values CD and BD are updated until there is a read request for STM data and the number of losses equals the number of dummy data. (8); This shows a state in which reading of STM data from the data buffer has been started because a request for reading STM data has been made and time series compensation has been completed. From EN = “1”, it is determined that there is data in the data buffer, and the upper address is set to ST,
The data stored in the data buffer is read using the lower address as RP. In addition, each control information of the management table updates CL, CD and BD to the initial value “0”, respectively,
The read pointer RP is updated with “+1”.

(9); following (8), there is a read request for STM data, indicating that 46 bytes of data have been transmitted. (10); shows a state after all data in the data buffer has been read. The control information at the time of reading the management table is in the state of (9), ST = ED and read pointer R
Since P = 46, the data stored in the data buffer is 1 byte. With the upper address as ST and the lower address as read pointer RP, the last data stored in the data buffer is read. In the control information of the management table, the read pointers RP and EN are updated as the initial value “0”. At the same time, the area “6” in which the data is stored is returned to the write address memory.

(11) shows a state in which data has already been stored in the data buffer as shown in (8), a cell has arrived as a cell loss, and an address chain has been formed. When the cell arrives, a data write instruction is issued, the data buffer storage area “8” is read from the write address FIFO, and the control information of the channel is read from the management table. At this time, the value of each control information is “8”. EN = “1”, ED = “6”
Chain memory address (shown as ADD in the figure)
Data buffer storage area “8” to be read next to “6”
Is written together with the loss information “5”. Further, ED indicating the end of the chain is updated to “8” and written in the management table.

(12); After the state of (11), a state is shown in which the STM data read request has been issued 45 times and there is only one byte in the data buffer storage area. (13); In the state of (12), there is an STM read request, and all the data in the data buffer storage area "6" has been read, so the next storage area "8" is read from the chain memory and updated. Is shown. There is a read request for STM data, and the control information of the channel is read from the management table. At this time, each control information is (12)
State. Since the read pointer RP is "46", all data in the data buffer storage area "6" has been read, and the data buffer storage area "6" is returned to the write address FIFO. Since ST is not equal to ED, it indicates that there is data to be read next. Therefore, using ST “8” as an address, NT and CL are read from the chain memory, and ST = NT =
Write "8", read pointer RP = "0", and CL = "5" in the management table.

As described above, the capacity of the data buffer can be reduced by using the data buffer as the common buffer by using the management table and the chain memory.

Although the SN is used to determine the continuity of the cell, the continuity of the cell can be determined by monitoring the cell arrival time. FIG. 18 is a diagram illustrating Embodiment (2) of the present invention. In the figure, 100 is a data buffer for writing main signal data, 200 is a header processing unit, 250 is a header table storing the permissible fluctuation value τ for each channel, 300 is a write control unit, 321
Is a WP / RP table, 431 is a TS / CH table,
Reference numeral 420 denotes a per-channel fluctuation allowable value processing unit.

FIG. 19 is a diagram for explaining the configuration of the data buffer according to the embodiment (2) of the present invention. In the data buffer 100, a write pointer WP, a read pointer RP, and main signal data are written for each channel. In the figure, reference numeral 101 denotes an enlarged display of channel 1 of the data buffer 100, and the channel 1 is provided with areas 1 to m.

In the configuration of FIGS. 18 and 19, when an ATM cell is input, the header processing unit 200 converts the information of the header of the ATM cell into a channel number. The per-channel fluctuation allowable value processing unit 420 reads the fluctuation allowable value τ corresponding to the channel from the header table 250. And
The channel number and the read allowable fluctuation value τ are output to the write control unit 300 by a non-illustrated allowable fluctuation value notification unit, and the main signal data is output to the data buffer 120.

At this time, the write controller 300 reads the write pointer WP from the WP / RP table 321 based on the channel number, and writes the main signal data to the data buffer 100 using the channel number as the upper address and the write pointer WP as the lower address. Put in. After the call setup, if an ATM cell of the channel arrives, WP / R
At the same time as updating the write pointer WP of the P table 321, the fluctuation allowable value τ notified from the header processing unit 200 is written.

The read control unit 400 reads the corresponding channel number and fluctuation allowable value τ from the TS / CH table 431 based on the STM time slot number, and performs a subtraction process at a designated cycle by a subtraction processing unit (not shown). I do. Here, a subtraction flag DEC for performing a subtraction process
And read the WP / RP table 3 by the channel number.
21, the write pointer WP and the fluctuation allowable value τ are read.

Here, when the value of τs at which reading is started is “0” and the subtraction interval is in STM frame units,
In data transfer by TM, for example, 128 kb / s of 64 kb / s × 2 channels may be used as one channel as in an ISDN service. In such a case, S
If τ is subtracted for each TM frame, subtraction is performed twice for one channel, so the subtraction is performed as follows.

If τs = “0”, that is, if the cell transfer fluctuation absorbing processing is completed, the main signal data stored from the data buffer 100 with the channel number as the upper address and the read pointer RP as the lower address. Is read and output as STM data. At the same time, the read pointer RP is updated and the WP / RP table 321 is updated.
Write to

When τs ≠ 0 and DEC = 1, that is,
If the cell transfer fluctuation absorbing process is being performed, τs is subtracted by “−1” and written in the column of τ of the WP / RP table 321. At this time, the read pointer RP is not updated, the main signal data in the data buffer 100 is not read, and dummy data of all bits “1” is transmitted as output STM data.

When τs ≠ 0 and DEC = 0, that is,
During the cell transfer fluctuation absorbing process, writing of τ and the read pointer RP into the WP / RP table 321 is not performed. Therefore, dummy data of all bits "1" is transmitted as output STM data.

In the embodiment (2), for each channel,
Although an individual buffer system is used in which an area for writing main signal data is allocated, a common buffer configuration may be used.

[0084]

According to the present invention, in a cell transfer, a time series in a case where a cell is discarded or a cell fluctuates is compensated,
Since the cycle of data write / read processing can be shortened, a decellularization apparatus capable of performing high-multiplex processing can be realized.

Further, it is possible to set the cell fluctuation due to the cell transfer path at the minimum value of the fluctuation assumed for each transfer path, and it is possible to convert the cell-digital synchronous data with low delay.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a first principle of the present invention.

FIG. 2 is a diagram illustrating a second principle of the present invention.

FIG. 3 is a diagram illustrating an embodiment (1-1) of the present invention.

FIG. 4 is a diagram illustrating a configuration of a data buffer according to the embodiment (1-1) of the present invention.

FIG. 5 is control information (part 1) of a data buffer according to the embodiment (1-1) of the present invention;

FIG. 6 shows control information (part 2) of the data buffer according to the embodiment (1-1) of the present invention.

FIG. 7 is a diagram illustrating the control information (part 3) of the data buffer according to the embodiment (1-1) of the present invention;

FIG. 8 shows control information (part 4) of the data buffer according to the embodiment (1-1) of the present invention.

FIG. 9 shows control information (part 5) of the data buffer according to the embodiment (1-1) of the present invention.

FIG. 10 shows control information (part 6) of the data buffer according to the embodiment (1-1) of the present invention.

FIG. 11 shows control information (part 7) of the data buffer according to the embodiment (1-1) of the present invention.

FIG. 12 is a diagram illustrating an embodiment (1-2) of the present invention.

FIG. 13 is a diagram illustrating a configuration of a management table and a chain memory according to the embodiment (1-2) of the present invention.

FIG. 14 is control information of a management table / chain memory according to the embodiment (1-2) of the present invention (part 1);

FIG. 15 is control information of a management table / chain memory according to the embodiment (1-2) of the present invention (part 2);

FIG. 16 shows control information of a management table / chain memory (part 3) according to the embodiment (1-2) of the present invention.

FIG. 17 is control information of the management table / chain memory according to the embodiment (1-2) of the present invention (part 4);

FIG. 18 illustrates Embodiment (2) of the present invention.

FIG. 19 is a view for explaining the configuration of a data buffer according to the embodiment (2) of the present invention;

FIG. 20 illustrates a conventional example (part 1).

FIG. 21 illustrates a conventional example (part 2).

[Explanation of symbols]

 100, 110B Data buffer 110 Control information area 120 Main signal data area 200 Header processing section 210 Header conversion section 220, 250 Header table 230 Cell continuity determination section 240 SN expected value 300 Write control section 310 Cell loss compensation section 320: 321 WP / RP table 400 Read control unit 410 Number of dummy data holding unit 420 Allowable fluctuation value processing unit for each channel 430: 431 TS / CH table 440 Threshold memory 600 Address FIFO 610 Management table 610A Control information memory 620 Chain memory

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hideaki Ono 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Hiroya Sakurai 1-chome Ichibancho, Aoba-ku, Sendai-shi, Miyagi No. 25 Inside Fujitsu Tohoku Digital Technology Co., Ltd.

Claims (10)

[Claims] 1. A decellularization device for converting a plurality of cells into digital synchronization data of a plurality of channels, wherein the cell is identified based on header information of the input cells and a main signal of the input data is stored for each channel. A data buffer including a main signal data area, a control information area for storing control information for each channel at the same address as the main signal data area in which the main signal data is written, and conversion of header information to a channel number. A header processing unit that identifies a sequence number; and a write control unit that has a cell loss compensation unit that compensates for the lost data in the channel when a cell loss occurs, and that controls writing of data to the data buffer. A dummy data number holding unit that holds the number of transmitted dummy data for each channel when an underflow occurs in the data buffer. Has the disassembling apparatus characterized by being configured from read control unit by dummy data number that sent the notified cell loss information from the write control unit performs read control of the data buffer. 2. A decellularization apparatus for converting a plurality of cells into digital synchronization data of a plurality of channels, comprising a plurality of regions, a divided region shared by a plurality of channels, and a header of an input cell. A data buffer having a main signal data area for identifying a cell based on information and storing input main signal data for each channel; an address memory for holding an address indicating an area of the divided data buffer; and the divided data buffer A management table that holds the correspondence information between the area and the channel and holds the number of dummy data sent when an underflow occurs, holds the area next to the area used by a given channel, and holds the number of cell losses And a cell memory that compensates for the lost data in the channel when a cell loss occurs. A write control unit that has a filling unit and controls writing of data to the data buffer; and a dummy data holding unit that holds the number of transmitted dummy data for each channel when an underflow occurs in the data buffer, A decellularization device, comprising: a read control unit for performing a read control of the data buffer based on the cell loss information and the number of dummy data notified from a write control unit. 3. The decellularization apparatus according to claim 1, wherein the control information area has a cell loss number area storing a cell-by-cell loss number and a maximum number of user data stored in one cell. A byte loss number area for storing a byte loss number in byte units as a value, a cell dummy number area for storing a cell dummy number obtained by measuring the number of data transmitted when an underflow occurs in cell units,
A decellularizing device comprising a byte dummy number area for storing a byte dummy number in byte units having a maximum value of the number of user data stored in a cell. 4. The decellularizing device according to claim 1, wherein when a cell loss occurs, the cell loss number in said cell loss number area and the byte loss number in said byte loss number area are updated to generate an underflow. A decellularizing device comprising a read instruction unit for updating the number of byte dummy when a cell arrives later and detecting a match between the number of lost data and the number of dummy data and instructing data reading. 5. The decellularization apparatus according to claim 1, wherein the control information area measures a cell loss number area for storing a cell loss number, and measures the number of data transmitted when an underflow occurs in units of cells. Cell dummy number area for storing the set cell dummy number, and 1
A decellularizing device comprising a byte dummy number area for storing a byte dummy number in byte units having a maximum value of the number of user data stored in a cell. 6. The decelerator according to claim 1, wherein an overflow area for storing information indicating occurrence of a buffer overflow is provided in said control information area. 7. A decellularization device for converting a plurality of cells into digital data of a plurality of channels, comprising: a header processing unit for identifying a cell based on header information of the input cell and converting the cell into a channel number; A data buffer for storing data for each channel, a write control unit for controlling the writing of data to the data buffer, a read control unit for controlling the reading of data from the data buffer, A decellularization apparatus comprising a per-channel fluctuation permissible value processing unit for setting a permissible value. 8. The decellularization apparatus according to claim 7, wherein when a cell arrives, a permissible fluctuation value for each channel is read from the per-channel fluctuation permissible value processing section, and the permissible fluctuation value is written to the write control section and the read control. A decelerating apparatus, further comprising a fluctuation allowable value notifying unit for notifying the unit. 9. The decelerating apparatus according to claim 7, wherein each time a predetermined time elapses, a permissible fluctuation setting for each channel is subtracted, and when the permissible fluctuation value reaches a threshold value, the data buffer is set. A decelerating device characterized by comprising a subtraction processing unit for reading data from a device. 10. The decelerating apparatus according to claim 9, wherein the subtraction interval from the permissible fluctuation value setting for each channel is set to an STM.
A decelerating apparatus characterized by using a frame time unit.