JPH11251848A - Tunable mos linear transconductance amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an MOS transconductance amplifier which has a satisfactory linear transconductance over its whole operation input voltage range and is suitably realized on a semiconductor integrated circuit. SOLUTION: An MOS differential pair 1 is formed by source-connected MOS transistors M1 and M2. An input voltage Vi is applied across the gates of M1 and M2. As the loads of M1 and M2, MOS transistors M3 and M4 with a bias voltage VB applied in common to their gates are respectively connected. Drain currents ID1 and ID2 with a square characteristic are linearized by M3 and M4 and taken out from the drains of M1 and M2 as a differential output voltage ΔV0 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS linear transconductance amplifier which can be suitably realized on a semiconductor integrated circuit, and more particularly to a MOS linear transconductance amplifier having good linearity over the entire operation input voltage range. About the amplifier.

[0002]

2. Description of the Related Art FIG. 13 shows an example of a conventional MOS linear transconductance amplifier. This amplifier is 1
A paper entitled “Current Summing CMOSOTA” presented by Kenji Toyoda, Akira Hyogo and Keitaro Sekine at the 1994 IEICE Spring Conference held in March 994 (lecture number A)
-36).

Referring to FIG. 13, this conventional MOS linear transconductance amplifier comprises two source-coupled n-channel MOS transistors M101 and M102.
Differential pair formed by the above and four n-channel MOS transistors M105 and M10 coupled to each other
6, a quadritail cell formed by M107 and M108.

The sources of MOS transistors M101 and M102 forming a MOS differential pair are commonly connected to a power supply voltage line to which a power supply voltage V _SS is applied via a constant current source 102 (current value: I _SS ). I have. This MOS differential pair is driven by the constant current I _SS generated by the constant current source 102.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M101 and M102 is _Kd times that of the unit MOS transistor ( _Kd is a constant, but _Kd is a constant). _d ≧ 1).

[0006] The gate of the MOS transistor M101, M102 forms a pair of input terminals of the amplifier, the input voltage V _in is the input differential between those gates.

[0007] N-channel MOS transistor M103
Operates as a load of the MOS transistor M101. The source of the MOS transistor M103 is connected to the drain of the MOS transistor M101, the drain is connected to the source voltage line for the power supply voltage V _DD is applied, a bias voltage (direct current constant voltage) V _B is applied to the gate.
The bias voltage V _B is generated by the constant voltage source 110.

[0008] N-channel MOS transistor M104
Operates as a load of the MOS transistor M102. The source of the MOS transistor M104 is connected to the drain of the MOS transistor M102, the drain is connected to a power supply voltage line to which the power supply voltage V _DD is applied, and the gate is the same bias voltage V _B as applied to the MOS transistor M103. Is applied.

[0009] The ratio of the MOS transistors M103, M104 of the gate width (W) and gate length (L) (W / L) are all those of K _l times the unit MOS transistor (K _l is a constant, where K _l ≧ 1).

The four n's forming a quadritail cell
Channel MOS transistors M105, M106, M1
07 and M108 are connected to a power supply voltage line to which the power supply voltage V _SS is applied via a constant current source 104 (current value: αI _SS ). The Kuadoriteru cell is driven by a constant current .alpha. I _SS generated by the constant current source 104.
The constant current αI _SS is the tail current.

The gates of the MOS transistors M105 and M108 are connected to the drains of the MOS transistors M101 and M102, respectively. The first output voltage V _O1 of the MOS differential pair generated at the drain of the transistor M101 is applied to the gate of the MOS transistor M105. The gate of the MOS transistor M108
The second output voltage V _O2 of the MOS differential pair generated at the drain of the transistor M102 is applied. The difference between these two output voltages V _O1 and V _O2 (V _O1 −V _O2 ) (ie, M
The differential output voltage of the OS differential pair) is the input voltage of the quadrature cell.

[0012] The ratio of the MOS transistors M105, M108 of the gate width (W) and gate length (L) (W / L) is a it K _m times of unit MOS transistor (K _m is a constant,
However, K _m ≧ 1). MOS transistors M106, M1
Ratio of gate width (W) to gate length (L) of 07 (W / L)
Is that of K _s multiple of the unit MOS transistor (K _s
Is a constant, but K _s ≧ 1).

The n-channel MOS transistor M109 and the constant current source 103 (current value: I _SS / 2) constitute a control voltage generation circuit for generating a control voltage V _C applied to the quadritail cell. The source of the MOS transistor M109 is connected to one end of the constant current source 103, the drain is connected to the power supply voltage line (V _DD ), and the gate is connected to the constant voltage source 1
10 bias voltage V _B is applied to generate the.

The control voltage V _C is controlled by the MOS transistor M1.
09 equal to the source voltage. In other words, the control voltage V _C
Is generated at the source of the MOS transistor M109.
MOS transistor M106 of quadritail cell,
The gate of M107 is connected to the source of the MOS transistor M109, and a control voltage (DC constant voltage) V _C is commonly applied.

[0015] Conventional MOS linear transconductance amplifier of Figure 13 has the above configuration, the two output current proportional to the input voltage _{V in (I dm1 + I q} ), (I dm2 +
Once _Iq ) is obtained, it is described in the above-mentioned paper. However, the above article, since the relationship between the output voltage V _O1, V _O2 of the input voltage V _in and the MOS differential pair is not shown, it is impossible to understand the operation principle from the article. Therefore, an output current proportional to the input voltage _{V in (I dm1 + I q} ),
(I _dm2 + I _q ), that is, the principle of the linear operation of the MOS linear transconductance amplifier of FIG. 13 cannot be understood.

The present inventor has proposed a conventional MO shown in FIG.
A circuit analysis of the S linear transconductance amplifier was performed. Then, it was confirmed that this circuit operates linearly.

In the circuit analysis, the MOS linear transconductance amplifier shown in FIG.
S transistors M105, M106, M107, M10
8 as a unit MOS transistor (that is, K _m =
If K _s = 1), the MOS transistors M101 and M10
The ratio (W / L) between the gate width (W) and the gate length (L) of the MOS transistor M2 is twice that of the unit MOS transistor (that is, K _d = 2), and the MOS transistors M103, M104, and M109
The ratio (W / L) of the gate width (W) to the gate length (L) is four times that of the unit MOS transistor (that is, _Kl = 4), and the current value (αI _SS ) of the constant current source 104 is constant. It has been found that this corresponds to the case where the current value I _SS of the current source 102 is １ ／ times as large.

Therefore, the circuit constant of the MOS linear transconductance amplifier shown in FIG. 13 corresponds to a set of countless values that satisfy the condition for the circuit to operate linearly.

[0019]

As described above, in the conventional MOS linear transconductance amplifier shown in FIG. 13, the gate width (W) of the MOS transistor is large.
And the gate length (L) ratio (W / L) is set to a value different from 1 ×, 2 × and 4 ×, and the current value of the constant current source is also set to 1 ×, 2 ×
It must be set to a value different from double and quadruple. Therefore, when implementing this circuit on a semiconductor integrated circuit,
There is a problem that problems such as an increase in chip area and variations in circuit characteristics are likely to occur.

A MOS linear transconductance amplifier is an essential function block in analog signal processing. In recent years, there has been a demand for a device capable of adjusting its transconductance value (ie, tuning the transconductance value). It is growing more and more.

An object of the present invention is to provide a MOS transconductance amplifier which has good transconductance over the entire operating input voltage range and is preferably realized on a semiconductor integrated circuit. .

Another object of the present invention is to provide a tunable MOS linear transconductance amplifier capable of adjusting a transconductance value without changing a circuit constant.

[0023]

(1) A first MOS linear transconductance amplifier according to the present invention comprises:
The first and second MOS transistors are formed by source-coupled first and second MOS transistors.
MO in which the input voltage is applied between the gates of the S transistor
An S differential pair, (b) a constant current source connected to the sources of the first and second MOS transistors for driving the MOS differential pair, and (c) a drain of the first MOS transistor. A third MOS transistor connected as a load of the first MOS transistor,
(D) a fourth MOS transistor connected to the drain of the second MOS transistor and operating as a load of the second MOS transistor, and (e) the same constant voltage is applied to the gates of the third and fourth MOS transistors. And (f) a differential output voltage proportional to the input voltage is taken out from the drains of the fifth and sixth MOS transistors.

(2) In the first MOS linear transconductance amplifier of the present invention, the first and second MO
The MOS differential pair formed by the S transistors is driven by a constant current source, and the input voltage is applied between the gates of the first and second MOS transistors.
The drain current of the second MOS transistor and the drain current of the second MOS transistor have a square characteristic with respect to the input voltage.

On the other hand, since the third and fourth MOS transistors are provided as loads of the first and second MOS transistors, respectively, the drain currents of the first and second MOS transistors are reduced by the third and fourth MOS transistors. Each is converted into a voltage by a transistor. as a result,
First and second output voltages are generated at the drains of the first and second MOS transistors, respectively.

At this time, the first and second output voltages are compressed by a square root (root) with respect to the input voltage due to the square characteristics of the third and fourth MOS transistors operating as loads. Since the same constant voltage is commonly applied to the gates of the third and fourth MOS transistors operating as loads, the square root compression of the first and second output voltages is performed in the same manner.

Therefore, the difference between the first and second output voltages of the MOS differential pair (ie, the differential output voltage of the MOS differential pair) is proportional to the input voltage. In other words, the differential output voltage of a MOS differential pair (ie, the MOS linear transconductance amplifier is linear with respect to the input voltage).

The good linearity of the differential output voltage of the amplifier spans the entire operating input voltage range. This is because the square characteristic of the MOS transistor is used.

(3) In a preferred example of the first MOS linear transconductance amplifier of the present invention,
And the ratio (W / L) of the gate width (W) to the gate length (L) of the second MOS transistor is K ₁ times that of the unit MOS transistor (K ₁ is a constant, but K ₁ ≧ 1). , The ratio (W / L) of the gate width (W) to the gate length (L) of the third and fourth MOS transistors is expressed in units of MO
_Twice that of K of S transistor (K ₂ is a constant, provided that K ₂
≧ 1).

In this case, there is an advantage that an amplifier or an attenuator can be easily realized by changing the value of the constant K ₁ and the value of K ₂ , and the amplification factor or the attenuation factor can be arbitrarily set.

(4) The second MOS linear transconductance amplifier according to the present invention comprises: (a) first to n-th (n is an integer of 2 or more) formed by two source-coupled MOS transistors, respectively; A MOS differential pair;
(B) first to n-th constant current sources for driving the first to n-th MOS differential pairs, respectively; and (c) operating as loads of the first to n-th MOS differential pairs, respectively. The first to do
(D) an input voltage is applied between the gates of two MOS transistors forming the first MOS differential pair, and (e) the second to n-th MOS differential transistors. Between the gates of the two MOS transistors forming each of the pairs, there are first to first (n-1) th MOS transistors formed between the drains of the MOS transistors forming each of the (n-1) th MOS differential pairs. The (n-1) th differential voltage is respectively applied, and (f) the same constant voltage is commonly applied to the gates of the two MOSFETs forming each of the first to n-th pairs of load MOS transistors. (G) a differential output voltage proportional to the input voltage is taken out from drains of two MOS transistors forming the n-th MOS differential pair.

(5) The second MOS linear transconductance amplifier according to the present invention is equivalent to a cascade connection of n first MOS linear transconductance amplifiers according to the present invention. Thus, for the same reasons as described in the first MOS linear transconductance amplifier of the present invention, the differential output voltage of the MOS linear transconductance amplifier is linear with respect to the input voltage over the entire operating input voltage range. Becomes

In the second MOS linear transconductance amplifier of the present invention, since n first MOS linear transconductance amplifiers of the present invention are cascaded, the number of n first MOS linear transconductance amplifiers depends on the value of the number n. There is an advantage that the amplification rate or the attenuation rate can be increased.

(6) In a preferred example of the second MOS linear transconductance amplifier according to the present invention,
The constant voltages commonly applied to the gates of the two MOS transistors forming each of the to the n-th pair of load MOS transistors are made equal to each other.

In this case, there is an advantage that the circuit is simplified.

In another preferred embodiment of the second MOS linear transconductance amplifier of the present invention, the gate width (W) and the gate length (L) of the MOS transistors forming the first to n-th MOS differential pairs are provided. Is K ₁ times that of the unit MOS transistor (K ₁ is a constant,
Where K ₁ ≧ 1), and the first to n-th M pairs of Ms that operate as loads of the first to n-th MOS differential pairs, respectively.
The ratio (W / L) of the gate width (W) to the gate length (L) of the OS transistor is set to K ₂ times that of the unit MOS transistor (K ₂ is a constant, where K ₂ ≧ 1).

In this case, an amplifier or an attenuator can be easily realized by changing the value of K ₂ with the constant K ₁ .
Further, there is an advantage that the amplification rate or the attenuation rate can be set arbitrarily.

(7) The third MOS linear transconductance amplifier of the present invention is formed by (a) first and second MOS transistors which are source-coupled, and the first and second MOS transistors are connected to each other. A MOS differential pair in which an input voltage is applied between the gates of
(B) a first constant current source connected to sources of the first and second MOS transistors for driving the MOS differential pair, and (c) connected to a drain of the first MOS transistor. A third MOS transistor that operates as a load of the first MOS transistor; and (d) a fourth M transistor that is connected to the drain of the second MOS transistor and operates as a load of the second MOS transistor.
An OS transistor, and (e) fifth, sixth, and seventh MOS transistors source-coupled to each other, and the fifth, sixth, and seventh MOS transistors are driven by the second constant current source (F) a first constant voltage is commonly applied to the gates of the third and fourth MOS transistors;
(G) the gate of the fifth MOS transistor has the M generated at the drain of the first MOS transistor.
A first output voltage of the OS differential pair is applied, and
The second gate of the MOS differential pair generated at the drain of the second MOS transistor is connected to the gate of the OS transistor.
An output voltage is applied, (h) a second constant voltage is applied to the gate of the seventh MOS transistor, and (i) a differential output current proportional to the input voltage is applied to the fifth and sixth MOS transistors. It is characterized by being taken out from the drain.

(8) The third MOS linear transconductance amplifier of the present invention corresponds to the first MOS linear transconductance amplifier of the present invention in which MOS triple tail cells are cascaded. Therefore, the differential output voltage of the MOS differential pair that is linear with respect to the input voltage is the fifth and sixth MOS transistors forming the triple tail cell.
Is applied between the gates (input terminal pair of the triple tail cell) of the MOS transistor of the third embodiment. At the same time,
A second constant voltage is applied to the gate (control terminal of the triple tail cell) of the seventh MOS transistor that constitutes the triple tail cell.

Therefore, the current flowing through the drain of the seventh MOS transistor (ie, the first output terminal of the squaring circuit) increases in proportion to the square of the input voltage, and the connected drains of the fifth and sixth MOS transistors ( That is, the current flowing through the second output terminal of the squaring circuit decreases in proportion to the square of the input voltage.

The third MOS linear transconductance amplifier of the present invention is thus equivalent to an adaptive bias differential pair, and the differential output current drawn from the drains of the fifth and sixth MOS transistors is proportional to the input voltage. , Ie, linear with respect to the input voltage.

The good linearity of these output currents generated at the first and second output terminals of the amplifier spans the entire operating input voltage range. This is because the operating input voltage range of the MOS differential pair and the operating input voltage range of the MOS triple tail cell match each other.

(9) In a preferred example of the third MOS linear transconductance amplifier according to the present invention,
And the ratio (W / L) of the gate width (W) to the gate length (L) of the second MOS transistor is K ₁ times that of the unit MOS transistor (K ₁ is a constant, but K ₁ ≧ 1). , The ratio (W / L) of the gate width (W) to the gate length (L) of the third and fourth MOS transistors is expressed in units of MO
_Twice that of K of S transistor (K ₂ is a constant, provided that K ₂
≧ 1).

In this case, an amplifier or an attenuator can be easily realized by changing the value of K ₂ with the constant K ₁ .
Further, there is an advantage that the amplification rate or the attenuation rate can be set arbitrarily.

In another preferred embodiment of the third MOS linear transconductance amplifier according to the present invention, the seventh MOS
The ratio (W / L) of the gate width (W) to the gate length (L) of the S transistor is the ratio (W / L) of the gate width (W) to the gate length (L) of the fifth and sixth MOS transistors. 2
Doubled.

In this case, there is an advantage that the circuit configuration is simplified.

In still another preferred embodiment of the third MOS linear transconductance amplifier of the present invention, the fifth and sixth MOS transistors are connected to the drains of the fifth and sixth MOS transistors, respectively. Eighth and ninth MOS transistors operating as a load are further provided, and a second constant voltage is commonly applied to the gates of the eighth and ninth MOS transistors, and a differential output proportional to the input voltage is provided. The current is voltage-converted by the eighth and ninth MOS transistors and taken out as a differential output voltage.

In this case, there is an advantage that the differential output current proportional to the input voltage is obtained by being converted into a voltage.

In another preferred embodiment of the third MOS linear transconductance amplifier according to the present invention, the second constant current source is capable of changing its current value, and the transconductance value is changed by changing the current value. Tuning is possible.

In this case, there is an advantage that a tunable MOS linear transconductance amplifier can be realized.

(10) The fourth MOS linear transconductance amplifier of the present invention is formed by (a) first and second MOS transistors which are source-coupled, and the first and second MOS transistors are connected to each other. A MOS differential pair in which an input voltage is applied between the gates of
(B) a first constant current source connected to sources of the first and second MOS transistors for driving the MOS differential pair, and (c) connected to a drain of the first MOS transistor. A third MOS transistor that operates as a load of the first MOS transistor; and (d) a fourth M transistor that is connected to the drain of the second MOS transistor and operates as a load of the second MOS transistor.
An OS transistor and (e) fifth, sixth, seventh and eighth source-coupled MOS transistors; and fifth, sixth, seventh and eighth MO transistors.
An S transistor comprising a quadrature cell driven by a second constant current source; (f) a first constant voltage is commonly applied to the gates of the third and fourth MOS transistors; The first output voltage of the MOS differential pair generated at the drain of the first MOS transistor is applied to the gate of the fifth MOS transistor, and the second output voltage is applied to the gate of the sixth MOS transistor.
A second output voltage of the MOS differential pair generated at the drain of the OS transistor is applied, (h) a second constant voltage is commonly applied to the gates of the seventh and eighth MOS transistors, and (i) A) a differential output current proportional to the input voltage is taken from the drains of the fifth and sixth MOS transistors;

(11) The fourth MOS linear transconductance amplifier of the present invention is the third MOS linear transconductance amplifier of the present invention.
This corresponds to a linear transconductance amplifier in which a triple tail cell is replaced with a quad tail cell.

The drains of the seventh and eighth MOS transistors forming the quad tail cell are connected in common or connected to the drains of the fifth and sixth MOS transistors, respectively, to perform an operation equivalent to the triple tail cell. Therefore, for the same reason as described in the third MOS linear transconductance amplifier of the present invention, the differential output current drawn from the drains of the fifth and sixth MOS transistors is proportional to the input voltage, that is, the input voltage. Be linear with voltage.

The good linearity of these output currents generated at the first and second output terminals of the amplifier is as follows:
Covers the entire operating input voltage range.

(12) In a preferred example of the fourth MOS linear transconductance amplifier of the present invention, the ratio (W / L) of the gate width (W) to the gate length (L) of the first and second MOS transistors is set. ) Is K ₁ times that of the unit MOS transistor (K ₁ is a constant, where K ₁ ≧ 1), and the ratio of the gate width (W) to the gate length (L) of the third and fourth MOS transistors (W / L) is the unit MO
_Twice that of K of S transistor (K ₂ is a constant, provided that K ₂
≧ 1).

In this case, an amplifier or an attenuator can be easily realized by changing the value of K ₂ with the constant K ₁ .
Further, there is an advantage that the amplification rate or the attenuation rate can be set arbitrarily.

In another preferred embodiment of the fourth MOS linear transconductance amplifier of the present invention, the ratio (W / L) of the gate width (W) to the gate length (L) of the seventh and eighth MOS transistors is The ratio (W) of the gate width (W) to the gate length (L) of the fifth and sixth MOS transistors
/ L).

In this case, there is an advantage that the circuit configuration is simplified.

In still another preferred embodiment of the fourth MOS linear transconductance amplifier of the present invention, the fifth and sixth MOS transistors are connected to the drains of the fifth and sixth MOS transistors, respectively. Ninth and tenth MOS transistors operating as loads are further provided.
A second constant voltage is commonly applied to the gates of the 0 MOS transistors, and a differential output current proportional to the input voltage is converted by the ninth and tenth MOS transistors and taken out as a differential output voltage. .

In this case, there is an advantage that a differential output current proportional to the input voltage is obtained by being converted into a voltage.

In still another preferred example of the fourth MOS linear transconductance amplifier of the present invention, the drains of the seventh and eighth MOS transistors are connected to each other, or the fifth and sixth MOS transistors are connected to each other. Are connected respectively to the drains.

This is because in these cases, the quad tail cells are equivalent to the triple tail cells. Also,
Four MOS transistors forming a triple tail cell can be realized by unit MOS transistors, and there is an advantage that a chip area is reduced.

In still another preferred example of the fourth MOS linear transconductance amplifier according to the present invention, the second constant current source is capable of changing its current value, and the transconductance value is changed by changing the current value. Tuning is possible.

In this case, there is an advantage that a tunable MOS linear transconductance amplifier can be realized.

[0065]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 shows the MOS linear transconductance amplifier of the embodiment of FIG.

This amplifier is composed of two source-coupled n
MOS differential pair 1 formed by channel MOS transistors M1 and M2, and two n
It has channel MOS transistors M3 and M4.

The sources of the MOS transistors M1 and M2 forming the MOS differential pair 1 are a constant current source 2 (current value:
I _SS ). This MOS differential pair 1
Is driven by the constant current I _SS generated by the constant current source 1. The gate of the MOS transistors M1, M2 forms an input terminal pair of the amplifier, the input voltage V _i is applied between their gate.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M1 and M2 is K ₁ times that of the unit MOS transistor (K ₁ is a constant, but K _{1 1} ≧ 1).

The MOS transistor M3 operates as a load of the MOS transistor M1. The source of the MOS transistor M3 is connected to the drain of the MOS transistor M1, the drain is connected to a power supply voltage line to which the power supply voltage V _DD is applied, and the bias voltage (DC constant voltage) V _B is applied to the gate.

The MOS transistor M4 operates as a load of the MOS transistor M2. The source of the MOS transistor M4 is connected to the drain of the MOS transistor M2, the drain is connected to a power supply voltage line to which the power supply voltage V _DD is applied, and the gate is the same bias voltage V _B as applied to the MOS transistor M3. Is applied.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M3 and M4 is K ₂ times that of the unit MOS transistor (K ₂ is a constant, but K ₂ is a constant). ₂ ≧ 1).

Next, the MOS of the first embodiment shown in FIG.
The operation principle of the linear transconductance amplifier will be described.

Assuming that the relationship between the drain current I _D and the gate-source voltage V _GS of the MOS transistor operating in the saturation region obeys the square law, ignoring the body effect and channel length modulation, the drain current I _D Is the following equation (1
a) and (1b).

[0075]

(Equation 1)

In equations (1a) and (1b), K is
Gate width (W) and gate length (L) of MOS transistor
Ratio (W / L) to that of a unit MOS transistor, β is a transconductance parameter, V _TH
Is the threshold voltage.

Assuming that the effective mobility of carriers is μ and the capacitance of the gate oxide film per unit area is C _OX , the transconductance parameter β is defined as β = μ (C _OX / 2) (W / L).

The effective mobility μ of the carrier changes according to the following equation (2) according to the absolute temperature T.

[0079]

(Equation 2)

The transconductance parameter β is also
It changes according to the following equation (3) according to the absolute temperature T.

[0081]

(Equation 3)

Is obtained.

However, in the equations (3) and (4), the suffix 300 represents μ, β, T at 300 K (= 27 ° C.).
Shows the value of

Assuming that matching between elements is good, MO
The two output currents of the S differential pair 1, that is, the drain currents I _D1 and I _D2 of the MOS transistors M1 and M2, are respectively expressed by the following equations (4a) and (4b).

[0085]

(Equation 4)

As shown in equations (4a) and (4b), the MO
The operating input voltage range of the S differential pair 1 is | V _i | ≦ (I _SS /
K ₁ β) ^1/2 .

The drain currents I _D1 and I _D2 of the MOS transistors M1 and M2 represented by the equations (4a) and (4b) are the MOS transistors M3 and M4 serving as loads, respectively.
Is converted to a voltage by the square root (root) compression.
That is, assuming that the differential output voltage of the MOS differential pair 1 is ΔV, ΔV is expressed as follows, where A is a constant.

[0088]

(Equation 5)

Here, a and b are constants, x is a variable, and
Consider the following identity (6).

[0090]

(Equation 6)

Then, in the equation (6), a, b, x
Is set as follows.

[0092]

(Equation 7)

Then, the left side of the identity expression (6) is equal to the value obtained by substituting the expressions (4a) and (4b) into the expression (5). At this time, the right side of the identity (5) is (K ₁ β) ^1/2
V _i . Therefore, the following equation (8) holds.

[0094]

(Equation 8)

As is apparent from the equation (8), the MO
The differential output voltage ΔV of the S differential pair 1, that is, equation (4a)
The difference between the square root of the square root and the drain current I _D2 of the drain current I _D1 represented by (4b) is proportional to the input voltage V _i.

Note that the differential output current of MOS differential pair 1 is Δ
Assuming that I _D , ΔI _D is expressed by the following equation (9) using the drain currents I _D1 and I _D2 .

[0097]

(Equation 9)

Therefore, the differential output current Δ of MOS differential pair 1
_ID is a linear term

[0099]

(Equation 10)

And the nonlinear term

[0101]

[Equation 11]

It can be seen that the following is included.

[0103] When the MOS transistor M1, the voltage of the combined source of M2 forming the MOS differential pair 1 and the common source voltage V _S1, the common source voltage V _S1 is the following formula (1
It is expressed as 2).

[0104]

(Equation 12)

[0105] In Equation (12), V _CM1 is the common mode voltage of the input voltage V _i is the input differential.

As can be seen from Equation (12), since the common source voltage V _S1 is a function of the input voltage V _i , the common source voltage V _S1 varies with the input voltage V _i . Further, the third term (square root term) of the equation (12) is equal to (1/2) ^1/2 of the second square root of the nonlinear term (11).
Therefore, the nonlinear term (11) of the differential output current [Delta] I _D of the MOS differential pair 1, it can be seen that due to variations of the common source voltage V _S1.

This means that if the common source voltage V _S1 of the MOS differential pair 1 can be fixed to a constant voltage, the MOS differential pair 1 can operate linearly.

Next, the two output voltages V _O1 and V _O1 of the MOS differential pair 1 having the MOS transistors M3 and M4 as loads.
_O2 is generated at the drains of the MOS transistors M1 and M2, respectively, and is represented by the following equations (13a) and (13b).

[0109]

(Equation 13)

Therefore, the differential output voltage Δ of MOS differential pair 1
V is represented by the following equation (14).

[0111]

[Equation 14]

In the equation (14), the ratio K ₂ between the gate width (W) and the gate length (L) of the load MOS transistors M 3 and M 4 is determined by the gates of the MOS transistors M 1 and M 2 forming the MOS differential pair 1. if the ratio K ₁ is greater than the width (W) and gate length (L), this MOS differential pair becomes a reverse-phase linear attenuator, or K ₁ K ₂ is equal to K ₁
If it is smaller, this MOS differential pair 1 is a linear amplifier of opposite phase. And its good linearity extends over the entire operating input voltage range | V _i | ≦ (I _SS / K ₁ β) ^1/2 .

As is clear from equation (14), the MOS
Differential output voltage ΔV of the MOS differential pair 1, load transistors M3, M4 is proportional to the input voltage V _i. In other words, the MO having the MOS transistors M3 and M4 as loads
S differential pair 1 operates as a linear attenuator or a linear amplifier to the input voltage V _i. If (K ₂ / K ₁ ) is set to a small value, a high gain can be realized.

If the common mode voltage of the output voltages V _O1 and V _O2 is V _CM2 , V _CM2 is represented by the following equation (15).

[0115]

(Equation 15)

From the equation (15), it is found that the MOS transistor M
3, the output voltage V _O1 of the MOS differential pair 1 with M4 as a load,
The common mode voltage V _CM2 of V _O2 is equal to the common source voltage V _S1.
It can be seen that this is represented by using the above equation (12).

FIG. 2 shows calculated values of output voltage characteristics of the MOS differential pair shown in FIG.

In FIG. 2, curves 31 and 32 show output voltages V _O1 and V _O2 of MOS differential pair 1, respectively, and curve 33
Shows the common mode voltage V _CM2 of the input voltage V _i. Curve 3
4 indicates a voltage [−V _O1 +2 (V _B −V _TH )], and a straight line 3
5 shows the voltage _{[V O2 -V O1 + V B} -V TH]. Straight line 35
As is clear from FIG. 5, the differential output voltage Δ
V is proportional to the input voltage V _i .

FIG. 3 shows measured output voltage characteristics and differential output voltage characteristics of the MOS differential pair 1 when K ₂ = K ₁ = 1. The transistor array used here is an n-channel power MOS transistor array (model name: μPA
572T). The threshold voltage V _TH of this MOS transistor is about 1.5 V, and the value of the transconductance parameter β is also approximately two digits larger than the value of the transconductance parameter β of the MOS transistor of a CMOS process that is currently generally used. About big. Therefore, the power supply voltage and tail current must be increased to widen the input voltage range. In this measurement, the power supply voltage was set to 5.0 V (V _DD =
5.0 V), and tail current of 10.5 mA (I _SS = 10.
5 mA).

In FIG. 3, curves 41 and 42 show the two output voltages V _O1 and V _O2 of the MOS differential pair 1, respectively, and curves 43 and 44 show the differential output voltage ΔV (= V _O1 −V _O2 ) and −ΔV (= V _O2 −V _O1 ). FIG. 3 shows that the differential output voltage ΔV of the MOS differential pair 1 having the MOS transistors M3 and M4 as loads is linear over a wide input voltage range.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
3 shows the MOS linear transconductance amplifier of the embodiment of FIG.

This amplifier includes a first MOS differential pair 1A formed by source-coupled n-channel MOS transistors M1A and M2A, and a second MOS differential pair formed by source-coupled n-channel MOS transistors M1B and M2B. 1B and a source coupled n-channel M
Third formed by OS transistors M1C and M2C
MOS differential pair 1C. These first to third MOS differential pairs 1A, 1B and 1C have the same configuration as the MOS linear transconductance amplifier 1 of the first embodiment, respectively, and are cascaded to each other.

The source of the MOS transistors M1A and M2A forming the first MOS differential pair 1A is a constant current source 2A.
(Current value: I _SS ). This MOS
The differential pair 1A is driven by a constant current I _SS generated by a constant current source 2A. MOS transistor M1A, a gate of M2A forms a pair of input terminals of the amplifier, the input voltage V _i is applied between their gate.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M1A and M2A is K ₁ times that of the unit MOS transistor (K ₁ is a constant, however, K _{1 1} ≧ 1).

The n-channel MOS transistor M3A is
It operates as a load of the MOS transistor M1A. MO
The source of the S transistor M3A is connected to the drain of the MOS transistor M1A, and the drain is connected to the power supply voltage V _DD.
There is connected to the power supply voltage line to be applied, the bias voltage (direct current constant voltage) V _B is applied to the gate.

The MOS transistor M4A operates as a load of the MOS transistor M2A. The source of the MOS transistor M4A is connected to the drain of the MOS transistor M2A, the drain is connected to the power supply voltage line to which the power supply voltage V _DD is applied, and the gate is the same bias voltage V _B applied to the MOS transistor M3A. Is applied.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M3A and M4A is K ₂ times that of the unit MOS transistor (K ₂ is a constant, but K ₂ is a constant). ₂ ≧ 1).

Similarly, the sources of the MOS transistors M1B and M2B forming the second MOS differential pair 1B are grounded via a constant current source 2B (current value: I _SS ). This MOS differential pair 1B includes a constant current I generated by a constant current source 2B.
Driven by _SS . MOS transistors M1B, M
The gate of 2B is connected to the drains of the MOS transistors M1A and M2A of the first MOS differential pair 1A. The two output voltages V _{O1 A} and V 2 of the first MOS differential pair 1A are connected to the gates of the MOS transistors M1B and M2B.
_O2A is applied respectively.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M1B and M2B is K ₁ times that of the unit MOS transistor (K ₁ is a constant, but K _{1 1} ≧ 1).

An n-channel MOS transistor M3B is
It operates as a load of the MOS transistor M1B. MO
The source of the S transistor M3B is connected to the drain of the MOS transistor M1B, and the drain is connected to the power supply voltage V _DD.
Is connected to the power supply voltage line to which
Transistors M3A, the same bias voltage (direct current constant voltage) as applied to M4A V _B is applied.

The MOS transistor M4B operates as a load of the MOS transistor M2B. The source of the MOS transistor M4B is connected to the drain of the MOS transistor M2B, the drain is connected to the power supply voltage line to which the power supply voltage V _DD is applied, and the gate is the same as that applied to the MOS transistors M3A, M4A, M3B. bias voltage V _B is applied.

[0132] The ratio of the MOS transistor M3B, the gate width of M4B (W) and gate length (L) (W / L) are both _twice that of K of unit MOS transistor.

The sources of the MOS transistors M1C and M2C forming the third MOS differential pair 1C are connected to a constant current source 2C.
(Current value: I _SS ). This MOS
The differential pair 1C is driven by the constant current I _SS generated by the constant current source 2C. The gates of the MOS transistors M1C and M2C are connected to the drains of the MOS transistors M1B and M2B of the second MOS differential pair 1B, respectively.
The gates of the MOS transistors M1C and M2C have a second
Two output voltages V _O1B and V _{O2B of the} MOS differential pair 1B are respectively applied.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M1C and M2C is K ₁ times that of the unit MOS transistor.

The n-channel MOS transistor M3C is
It operates as a load of the MOS transistor M1C. MO
The source of the S transistor M3C is connected to the drain of the MOS transistor M1C, and the drain is connected to the power supply voltage V _DD.
Is connected to the power supply voltage line to which
Transistors M3A, M4A, M3B, the same bias voltage (direct current constant voltage) as applied to M4B V _B is applied.

The MOS transistor M4C operates as a load of the MOS transistor M2C. The source of the MOS transistor M4C is connected to the drain of the MOS transistor M2C, the drain is connected to a power supply voltage line to which the power supply voltage V _DD is applied, and the gate is applied to the MOS transistors M3A, M4A, M3B, M4B, M3C. that the same bias voltage V _B is applied as.

[0137] The ratio of the MOS transistor M3C, the gate width of M4C (W) and gate length (L) (W / L) are both _twice that of K of unit MOS transistor.

The differential output voltage ΔV _O of the MOS linear transconductance amplifier according to the second embodiment is the output voltage V _O1C and V _O2C generated at the drains of the MOS transistors M1C and M2C of the third differential pair 1C. Equal to the difference. That is, ΔV _O = V _O1C -V _O2C. This differential output voltage ΔV _O is taken out from the drains of the MOS transistors M1C and M2C.

The MOS linear transconductance amplifier according to the second embodiment shown in FIG. 4 differs from the MOS linear transconductance amplifier according to the first embodiment by three.
It is equivalent to those connected in tandem. Therefore, for the same reason as that described in the MOS linear transconductance amplifier of the first embodiment described above, the differential output voltage [Delta] V _O of the amplifier and the linear to the input voltage V _i across the operating input voltage range Become.

In the MOS linear transconductance amplifier of the second embodiment, three MOS linear transconductance amplifiers of the first embodiment are used.
Since the S linear transconductance amplifier is cascade-connected, there is an advantage that the amplification factor or the attenuation factor can be increased as compared with the first embodiment.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
9 shows a MOS triple-tail cell 3 used in the MOS linear transconductance amplifier (see FIG. 6) of the embodiment. In the MOS linear transconductance amplifier according to the third embodiment, FIG.
The MOS triple tail cell shown in FIG.
It has a configuration in which the MOS linear transconductance amplifier of the embodiment is combined.

As shown in FIG. 5, this MOS triple-tail cell 3 has three n-channel source-coupled n-channels.
It is formed by OS transistors M5, M6 and M7.
The sources of the MOS transistors M5, M6, M7 are commonly grounded via a constant current source 4 (current value: I ₀ ). This MOS triple tail cell 3 is composed of a constant current source 4
It is driven by a constant current I ₀ which generates the.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M5 and M6 is equal to that of the unit MOS transistor. The ratio of the gate width (W) to the gate length (L) of the MOS transistor M7 (W /
L) is K ₃ times that of the unit MOS transistor (K ₃ is a constant, but K ₃ ≧ 1).

The gate of the MOS transistor M5 has M
The first output voltage V _O1 of the MOS differential pair 1 generated at the drain of the MOS transistor M1 forming the OS differential pair 1 (that is, the MOS linear transconductance amplifier of the first embodiment) is applied. At the same time, MO
The second output voltage V _O2 of the MOS differential pair generated at the drain of the MOS transistor M2 forming the MOS differential pair 1 is applied to the gate of the S transistor M6. The difference between these two output voltages V _O1 and V _O2 (ie, the differential output voltage of the MOS differential pair) ΔV is the triple tail cell 3
Input voltage.

The drain of the MOS transistor M7 is connected to a power supply voltage line (V _DD ), and a control voltage (DC constant voltage) V _C is applied to its gate.

The drains of the MOS transistors M5 and M6 form an output terminal pair of the triple tail cell 3, from which output currents I ⁺ and I ^- are respectively taken.

The n-channel MOS transistor M8 and the constant current source 5 (current value: I _SS / 2) 5 constitute a control voltage generating circuit for generating a control voltage V _C for the MOS transistor M7. The source of the MOS transistor M8 is grounded via the constant current source 5, the drain is connected to a power supply voltage line (V _DD ), and the gate thereof has a bias voltage V _B.
Is applied.

Next, the MOS triple tail cell 3
Will be described.

The differential output current ΔI (= I ⁺ −I ⁻ ) of the triple tail cell 3 is calculated by the same inventor as disclosed in
No. 84037. According to it, M
Assuming that the drain currents of the OS transistors M5 and M6 are I _D5 and I _D6 , respectively, the differential output current ΔI is given by the following equation (1).
6).

[0150]

(Equation 16)

Here, the differential output voltage ΔV of the MOS differential pair input between the gates of the MOS transistors M5 and M6
Is linear with respect to the input voltage V _i to the MOS differential pair 1 (ie, the amplifier in question), and
Considering that the drain currents I _D5 and I _D6 of the MOS transistors M5 and M6 forming the cell 3 each have a square characteristic with respect to the input voltage ΔV to the triple tail cell, the amplifier of FIG. In order to output a current having characteristics, the differential output current ΔI of the triple tail cell 3 expressed by the equation (16) becomes linear with respect to the input voltage ΔV, in other words, the input voltage ΔV It is necessary to be proportional.

That is, if c is a constant, it is necessary that ΔI = cΔV holds.

Therefore, the coefficient of ΔV of the numerator in the equation (16) must be equal to the constant c. That is, the following equation (17) must be satisfied.

[0154]

[Equation 17]

At this time, the differential output current ΔI of the triple tail cell 3 is as follows.

[0156]

(Equation 18)

When the control voltage V _C at this time is obtained from the equation (17), the following equation (19) is obtained.

[0158]

[Equation 19]

Therefore, the differential output current ΔI of the triple tail cell 3 expressed by the above equation (16) becomes linear with respect to the input voltage ΔV, that is, the MOS shown in FIG.
In order for the linear transconductance amplifier to output a current having a linear characteristic, the control voltage V _C is calculated according to the equation (19).
Must be set so that
Then, the differential output current ΔI of the triple tail cell 3 at that time is expressed by the above equation (18).

For example,

[0161]

(Equation 20)

At this time, the control voltage V _C needs to be set as follows.

[0163]

(Equation 21)

As described above, if the control voltage V _C to the MOS transistor M7 of the triple tail cell 3 is set so that the above equation (19) holds, the above equation (1)
6), the differential output current I ⁻ of the triple tail cell 3 becomes linear with respect to the input voltage ΔV. And
The differential output current ΔI is represented by the above equation (18).

FIG. 6 shows a MOS transistor according to a third embodiment of the present invention.
3 shows a linear transconductance amplifier. In this amplifier, a MOS composed of MOS transistors M1 and M2 and MOS transistors M3 and M4 serving as loads thereof is used.
At the output terminal of the differential pair 1 (that is, the MOS linear transconductance amplifier of the first embodiment) (see FIG. 1),
The MOS triple tail cells 3 of FIG. 5 are cascaded.

For this reason, the gate voltages of the MOS transistors M5, M6 and M7 forming the triple tail cell 3 are V _O1 , V _O2 and (V _CM2 + V _C ), respectively. If the gate voltage of the MOS transistor M7 (V _CM2 +
If V _C ) = V _G7 becomes a constant value, the gate bias circuit for generating the control voltage V _C can be greatly simplified. Therefore, next, the conditions necessary for that are obtained.

The common mode voltage V of the output voltages V _O1 and V _O2
CM2 is represented by the above equation (15), and since the control voltage V _C satisfies the above equation (19), the MOS transistor M7
Gate voltage V _G7 = (V _CM2 + V _C ) is _calculated by the following equation (2)
It is expressed as 2). Here, d is a constant.

[0168]

(Equation 22)

As described above, in order for the MOS linear transconductance amplifier of FIG. 6 to output a current having a linear characteristic, the differential output current ΔI of the triple tail cell 3 must be proportional to its input voltage ΔV. Is required, all the coefficients of the term including the input voltage ΔV in the equation (22) must be zero. That is, equation (22) must be simplified as in equation (23).

[0170]

(Equation 23)

The condition required to satisfy the equation (23) is the following relational equation (24a) in the equation (22):
(24b) is satisfied.

[0172]

(Equation 24)

Therefore, these relational expressions (24a) and (2a)
As 4b) is satisfied, when setting values such as the current value I _0, I _SS is established equation (23) is, the gate voltage V _G7 of a MOS transistor _{M7 = (V CM2 + V C} ) is constant Value. As a result, the bias circuit for generating the control voltage V _C for the MOS transistor M7 is greatly simplified as shown in FIG. And in that case,
Control voltage V _C is the formula in the circuit configuration of FIG. 6 (1
9), the differential output current ΔI of the triple tail cell 3 becomes linear with respect to the input voltage ΔV, as represented by the above equation (18).

As described above, the input voltage ΔV to the MOS triple tail cell 3 is the differential output voltage ΔV of the MOS differential pair 1 having the MOS transistors M3 and M4 as loads. _Is proportional to the input voltage V _i .

[0175] Thus, the amplifier of FIG. 6, it is confirmed that outputs an output current ΔI having a linear characteristic with respect to the input voltage V _i as a differential output current ΔI of the MOS triple-tail cell 3.

In this case, triple tail cell 3 formed of MOS transistors M5, M6, M7 is used.
Operate as an adaptive bias differential pair as disclosed in JP-A-6-152275 by the same inventor.

Next, the operation input voltage range of the MOS linear transconductance amplifier shown in FIG. 6 will be described.

MOS forming triple tail cell 3
The drain currents I _D5 and I _D6 of the transistors M5 and M6 are
The input voltage ΔV to this triple tail cell 3 respectively
, The drain currents I _D5 , I _D6 , I _{D5 of} the MOS transistors M5, M6, M7
_D7 is given by the following equations (25a), (25b), (25
It is shown as c).

[0179]

(Equation 25)

As is apparent from equations (25a) and (25b), the two output currents I ⁺
And I ^- also proportional to the square of the input voltage ΔV any case, therefore, their output currents I ⁺ and I ^- has an ideal square characteristics for the input voltage ΔV none.

Next, a condition for making the linear input voltage range of the MOS triple tail cell 3 equal to the operating input voltage range of the MOS differential pair 1 will be determined.

First, if none of the MOS transistors M5, M6 and M7 forming the MOS triple tail cell 3 pinch off, the two output voltages V _O1 and V _{O2 of} the MOS differential pair 1 and the control voltage V _C are They are respectively represented by the following equations (26a), (26b), and (26c).

[0183]

(Equation 26)

The equations (26a) and (26b) are the same as the equations (13a) and (13b).

When I _D1 = I _SS and I _D2 = 0, the above equation (2)
6a), (26b), and (26c) are as follows.

[0186]

[Equation 27]

[0187] When the formula (27a) is substituted into the equation (25a), the following equation (28) is obtained for I _D5.

[0188]

[Equation 28]

By rearranging equation (28), the following equation (2)
It becomes like 9).

[0190]

(Equation 29)

Similarly, equation (27b) is replaced by equation (25)
Substituting in b), the following equation (30) is obtained for I _D6.

[0192]

[Equation 30]

By rearranging equation (30), the following equation (3)
It becomes like 1).

[0194]

(Equation 31)

By subtracting equation (29) from equation (31),
The following equation (32) is obtained.

[0196]

(Equation 32)

Equation (32) represents the MOS triple tail
The maximum value of the differential input voltage ΔV to the cell 3 is shown.

On the other hand, the minimum value of the differential input voltage ΔV is I _D2 =
It is obtained when I _SS and I _D1 = 0, and ΔV at that time is as follows.

[0199]

[Equation 33]

Therefore, it can be seen that the range of the differential input voltage ΔV is expressed as follows.

[0201]

(Equation 34)

Further, the equation (27c) is replaced by the equation (25)
Substituting in c), the following equation (35) is obtained for I _D7.

[0203]

(Equation 35)

The equation (35) is added to the equation (31).
By substituting (32) and solving this, the following equation (36) is obtained.

[0205]

[Equation 36]

Therefore, the current values I _SS and I _SS of the constant current sources 2 and 4 are
₀ and the ratio of the gate width to the gate length of the MOS transistor (W
/ L) of the unit MOS transistor to that of the unit MOS transistor K ₂
Is set to satisfy Expression (36), MOS
The linear input voltage range of the triple tail cell is equal to the operating input voltage range of the MOS differential pair. As a result, in the MOS linear transconductance amplifier of FIG. 6, ideal linear characteristics can be obtained over the entire operating input voltage range of the circuit.

Then, in this case, the MOS triple tail cell of FIG. 5 operates as an adaptive bias differential pair having the largest linear input voltage range.

The most simplification of the circuit configuration of FIG.
For example, this is the case where K ₁ = K ₂ = 1, K ₃ = 2, and I _SS = I _0/2 . At this time, the value of the constant c is

[0209]

(37)

The following is obtained.

[0211] Equation (37) satisfies the above equation (19), respectively the control voltage V _C constant d at this time, the following equation (38a), so that the (38b).

[0212]

(38)

(Third Embodiment) FIG. 7 shows a MOS linear transconductance amplifier according to a third embodiment of the present invention.

In the amplifier according to the third embodiment, a triple tail cell (quadri-tail cell) is used instead of the triple tail cell 3.
It has the same configuration as the MOS linear transconductance amplifier of the second embodiment of FIG. 6 except that a tail cell 3 ′ is used. Therefore, the same components are denoted by the same reference numerals, and the description of the same components will be omitted.

The MOS transistor M7 constituting the triple tail cell 3 of FIG. 5 has a gate width to gate length ratio (W / L) twice as large as the unit MOS transistor (K ₃ = 2). Therefore, the MOS transistor M7 can be divided into two unit MOS transistors M7A and M7B in which all of the source, drain and gate are connected in common. That is, the quadritail shown in FIG.
It can be transformed like cell 3 '.

Since the quad tail cell 3 'is equivalent to the triple tail cell 3, the MO of the third embodiment is
The operation of the S linear transconductance amplifier is
Is exactly the same as that of the embodiment.

FIG. 8 shows the characteristics of the drain currents I _D5 , I _D6 , I _D7A and I _D7B of the MOS transistors M5, M6, M7A, M7B constituting the quadritail cell 3 '.

In FIG. 8, it can be seen from the curves 51, 52, and 53 that the drain currents I _D5 , I _D6 , I _D7A , and I _D7B all have square characteristics. Further, it can be seen from the curve 54 that the sum of the drain currents I _D7A and I _D7B also has a square characteristic. Further, from the curve 55, the drain current I
_It can also be seen from the curve 56 that the sum of _D5 and I _D7A has a linear characteristic, and that the sum of the drain currents I _D6 and I _D7B has a linear characteristic.

(Fourth Embodiment) FIG. 9 shows a MOS linear transconductance amplifier according to a fourth embodiment of the present invention.

The amplifier according to the fourth embodiment is different from the amplifier according to the third embodiment in FIG.
5, two n-channel MOS transistors M8 and M9 are added as loads. Thus, the third
The differential output current ΔI in the amplifier according to the embodiment is converted into a voltage and extracted as a differential output voltage ΔV _O.

The differential output voltage ΔV _O is calculated by using the drain voltages V _O3 and V _O4 of the MOS transistors M5 and M6.
_O = _VO3 - _VO4 .

In FIG. 9, two n-channel MOS transistors M10A and M10B and a constant current source 5A (current value: I
₀ ) generates the control voltage V _C for the MOS transistor M7. MOS transistors M10A, source of M10B are commonly grounded via a constant current source 5, their drains are commonly connected to the power supply voltage line (V _DD), commonly applied bias voltage V _B to their gates Is done.

(Fifth Embodiment) FIG. 10 shows a fifth embodiment of the present invention.
3 shows the MOS linear transconductance amplifier of the embodiment of FIG.

The amplifier according to the fifth embodiment is different from the amplifier according to the third embodiment in FIG. 7 in that the drains of the two MOS transistors M7A and M7B of the quadritail cell are connected to the MOS transistors M5 and M6, respectively. , And two resistors 6, 7 (both having a resistance value of R _L ) are added as loads of the MOS transistors M5 and M6. Thus, the differential output current ΔI in the amplifier according to the fifth embodiment is converted into a voltage and extracted as a differential output voltage ΔV _O.

As is apparent from FIG. 8, the sum of the drain currents I _D5 and I _D7A has a linear characteristic from the curve 55, and the sum of the drain currents I _D6 and I _D7B has the linear characteristic from the curve. Therefore, in the amplifier of the fifth embodiment, the differential output current ΔI can be expressed as ΔI = (I _D5 + I _D7A ) − (I _D6 + I _D7B ), which is also linear over a wide input voltage range.

Therefore, the differential output current ΔI is
_Is also linear over a wide input voltage range.

Here, the drain currents I _D5 , I _D6 , I _D7A and I _D7B of the MOS transistors M5, M6, M7A and M7B of the _{quadri-tail cell} are respectively _expressed by the following equation (39).
a), (39b) and (39c).

[0228]

[Equation 39]

Therefore, the two MOS transistors M5 and M6 forming the differential pair of the quadrature cell
Is expressed as follows.

[0230]

(Equation 40)

The circuit that can be most simplified is, for example, K
₁ = K ₂ = 1, K ₃ = 2, I _SS = I _0/2 , and the value of the constant c at this time is

[0232]

[Equation 41]

Is obtained. The equation (41) satisfies the equation (19), and the constant d and the control voltage V _C are as follows.

[0234]

(Equation 42)

The differential output current ΔI of the quadritail cell 3 ′ shown in FIG. 10 is expressed by the following equation (43).

[0236]

[Equation 43]

The operating input voltage range is as follows.

[0238]

[Equation 44]

The operating input voltage range of this equation (44) is:
It is equal to the operation input range of the MOS differential pair 1 having a MOS transistor as a load.

The transconductance is given by the following equation (43).
It is obtained by differentiating the input voltage V _i a. That is,

[0241]

[Equation 45]

FIGS. 11 and 12 show calculated values of the transfer characteristics of the MOS differential pair 1 shown in FIG. 1 and the MOS linear transconductance amplifier shown in FIG. 10, respectively.

In FIG. 11, curves 71 and 72 correspond to FIG.
MOS differential pair 1 shown in FIG.
5 shows changes in drain currents I _D1 and I _D2 in a linear transconductance amplifier. FIG. 11 shows that the drain current in the MOS linear transconductance amplifier of the first embodiment has a square characteristic.

In FIG. 12, curves 81 and 82 correspond to FIG.
0, the output currents (I _D6 + I _D7B ), (I _D ) in the MOS linear transconductance amplifier of the fifth embodiment
_D5 + I _D7A ). FIG. 12 shows that the output currents (I _D6 + I _D7B ) and (I _D5 + I _D7A ) of the MOS linear transconductance amplifier of the fifth embodiment have linear characteristics.

K ₁ = 2, K ₂ = 4, K ₃ = 2, I _SS = 2I ₀
Then, it exactly matches the MOS linear transconductance amplifier proposed by Toyota et al. (See FIG. 13).
Then, the calculated value of the transfer characteristic becomes the same as the characteristic shown in FIG.

The quadritail cell shown in FIG. 10 is equivalent to an adaptive bias differential pair, so its transconductance is proportional to the square root of the bias current, and the linear input voltage range is also proportional to the square root of the bias current.

[0247]

As described above, the first to fourth embodiments of the present invention are described.
In the MOS transconductance amplifier of the present invention, the transconductance has a good linearity over the entire operating input voltage range, and is suitably realized on a semiconductor integrated circuit.

In the third and fourth MOS transconductance amplifiers of the present invention, when the current value of the second constant current source for driving the triple tail cell or quad tail cell can be changed, The transconductance value can be adjusted without changing the circuit constant.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a MOS linear transconductance amplifier according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing calculated values of output voltage characteristics of the MOS linear transconductance amplifier according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram showing actually measured values of output voltage characteristics and differential output voltage characteristics of the MOS linear transconductance amplifier according to the first embodiment of the present invention (K ₂ = K ₁ = 1).

FIG. 4 is a circuit diagram showing a MOS linear transconductance amplifier according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a MOS triple tail cell used in a MOS linear transconductance amplifier according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a MOS linear transconductance amplifier according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a MOS linear transconductance amplifier according to a third embodiment of the present invention.

FIG. 8 is a characteristic diagram showing a drain current characteristic of a MOS transistor forming a quadritail cell in the MOS linear transconductance amplifier according to the third embodiment of the present invention.

FIG. 9 is a circuit diagram showing a MOS linear transconductance amplifier according to a fourth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a MOS linear transconductance amplifier according to a fifth embodiment of the present invention.

FIG. 11 is a characteristic diagram showing an output current characteristic of the MOS linear transconductance amplifier according to the first embodiment of the present invention.

FIG. 12 is a characteristic diagram showing output current characteristics of a MOS linear transconductance amplifier according to a fifth embodiment of the present invention.

FIG. 13 shows a conventional MOS linear transconductance.
FIG. 3 is a circuit diagram illustrating an example of an amplifier.

[Explanation of symbols]

M1, M2, M3, M4, M5, M6, M7 MOS transistors M8, M9 MOS transistors M1A, M1B, M1C, M2A, M2B, M2C M
OS transistor M3A, M3B, M3C, M4A, M4B, M4C M
OS transistor M7A, M7B, M10A, M10B 1, 1A, 1B, 1C MOS differential pair 2, 2A, 2B, 2C, 4, 5, 5A Constant current source 3 Triple tail cell 3 'Quadri tail cell 6, 7 Resistance vessel

Claims (17)

[Claims] (A) formed by source-coupled first and second MOSFETs;
And a MOS differential pair to which an input voltage is applied between the gates of the first and second MOSFETs, and (b) a constant for driving the MOS differential pair connected to the sources of the first and second MOSFETs. A current source; and (c) the first MOS
The first MOSFET connected to the drain of the FET
And (d) a second MOSFET connected to the drain of the second MOSFET.
A fourth MOSFET that operates as a load of the MOSFET; (e) a same constant voltage is commonly applied to gates of the third and fourth MOSFETs; and (f) a differential output voltage proportional to the input voltage. Is extracted from the drains of the fifth and sixth MOSFETs. 2. The ratio (W / L) of the gate width (W) to the gate length (L) of the first and second MOSFETs is K ₁ times that of the unit MOSFET (K ₁ is a constant, but K ₁ is a constant. ₁ ≧
1), and the ratio (W / L) of the gate width (W) to the gate length (L) of the third and fourth MOSFETs is expressed in units of M
K ₂ times that of the OSFET (K ₂ is a constant, but K ₂ ≧
2. The MOS linear transconductance amplifier according to claim 1, which is 1). 3. (a) two source-coupled MOSs
First to n-th (n is an integer of 2 or more) MOS differential pairs respectively formed by FETs; and (b) the first to n-th MOS differential pairs.
And (c) first to n-th pairs of loads respectively operating as the loads of the first to n-th MOS differential pairs. MOS
(D) an input voltage is applied between the gates of two MOSFETs forming the first MOS differential pair, and (e) two input terminals forming each of the second to n-th MOS differential pairs. Between the gates of the two MOSFETs, the first to (n-1) th differentials generated between the drains of the two MOSFETs forming the first to (n-1) th MOS differential pairs, respectively. (F) The same constant voltage is commonly applied to the gates of the two MOSFETs forming each of the first to n-th load MOSFETs, and (g) proportional to the input voltage. Two MOSFEs whose differential output voltages form an n-th MOS differential pair
MOS extracted from the drain of T
Linear transconductance amplifier. 4. The MOS linear transconductance amplifier according to claim 3, wherein constant voltages commonly applied to gates of two MOSFETs forming each of the first to n-th pairs of load MOSFETs are equal to each other. 5. The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOSFETs forming the first to n-th MOS differential pairs is equal to K ₁ of that of the unit MOSFET.
(K ₁ is a constant, K ₁ ≧ 1), and the gate width (W) and the gate of the first to n-th MOSFETs respectively operating as the loads of the first to n-th MOS differential pairs 5. The MOS linear transconductance according to claim 3, wherein the ratio (W / L) of the length (L) is K ₂ times that of the unit MOSFET (K ₂ is a constant, K ₂ ≧ 1). Amplifier. 6. A method comprising: (a) forming source-coupled first and second MOSFETs;
And a MOS differential pair to which an input voltage is applied between the gates of the first and second MOSFETs, and (b) a MOS differential pair connected to the sources of the first and second MOSFETs for driving the MOS differential pair. (1) a constant current source;
The first MOSF connected to the drain of the OSFET
A third MOSFET acting as a load on the ET, and (d)
A fourth MOSFET connected to the drain of the second MOSFET and operating as a load of the second MOSFET;
T, (e) fifth, sixth and seventh source coupled
And their fifth,
A sixth tail and a triple tail cell driven by a second constant current source, and (f) a first constant voltage is commonly applied to gates of the third and fourth MOSFETs. (G) the first output voltage of the MOS differential pair generated at the drain of the first MOSFET is applied to the gate of the fifth MOSFET, and the second MOSFET is applied to the gate of the sixth MOSFET.
A second output voltage of the MOS differential pair generated at the drain of the ET is applied, (h) a second constant voltage is applied to the gate of the seventh MOSFET, and (i) a differential proportional to the input voltage. The output current is equal to the fifth and sixth MOs.
A MOS linear transconductance amplifier which is taken out from the drain of an SFET. 7. The ratio (W / L) of the gate width (W) to the gate length (L) of the first and second MOSFETs is K ₁ times that of the unit MOSFET (where K ₁ is a constant; ₁ ≧
1), and the ratio (W / L) of the gate width (W) to the gate length (L) of the third and fourth MOSFETs is expressed in units of M
K ₂ times that of the OSFET (K ₂ is a constant, but K ₂ ≧
7. The MOS linear transconductance amplifier according to claim 6, wherein 1). 8. The gate width (W) of the seventh MOSFET
And the gate length (L) ratio (W / L) is 5 and 6
8. The MO according to claim 6, wherein a ratio (W / L) of a gate width (W) to a gate length (L) of the MOSFET is twice as large.
S linear transconductance amplifier. 9. An eighth and a ninth M connected to the drains of the fifth and sixth MOSFETs, respectively, which operate as loads on the fifth and sixth MOSFETs.
OSFETs, and the eighth and ninth OSFETs are provided.
7. A second constant voltage is commonly applied to the gates of the MOSFETs, and a differential output current proportional to the input voltage is converted by the eighth and ninth MOSFETs and taken out as a differential output voltage. 9. The MOS linear transconductance amplifier according to any one of items 1 to 8. 10. The transconductance value of the second constant current source is changeable, and the transconductance value can be tuned by changing the current value.
10. The MOS linear transconductance amplifier according to any one of claims 9 to 9. (A) a MOS differential pair formed by source-coupled first and second MOSFETs and having an input voltage applied between the gates of the first and second MOSFETs; b) said first and second
A first constant current source connected to the source of the MOSFET for driving the MOS differential pair; and (c) the first constant current source.
The first MOS connected to the drain of the MOSFET
A third MOSFET acting as a load on the FET;
(D) a fourth transistor connected to the drain of the second MOSFET and operating as a load of the second MOSFET;
An OSFET, and (e) a source-coupled fifth, sixth,
The fifth, sixth, seventh and eighth MOSFETs are formed by seventh and eighth MOSFETs.
Comprises a quadri-tail cell driven by a second constant current source, and (f) said third and fourth MOSFETs.
The first constant voltage is commonly applied to the gates of
The gate of the fifth MOSFET is connected to the first MOSF
The first output voltage of the MOS differential pair generated at the drain of the ET is applied, and the second output voltage of the MOS differential pair generated at the drain of the second MOSFET is applied to the gate of the sixth MOSFET. (H) a second constant voltage is commonly applied to the gates of the seventh and eighth MOSFETs; and (i) a differential output current proportional to the input voltage is applied to the fifth and sixth MOSFETs. A MOS linear transconductance amplifier, which is obtained from a drain of a MOSFET. 12. The ratio (W / L) of the gate width (W) to the gate length (L) of the first and second MOSFETs is K ₁ times that of the unit MOSFET (K ₁ is a constant, but K ₁ is a constant. ₁
≧ 1), and the ratio (W / L) of the gate width (W) to the gate length (L) of the third and fourth MOSFETs is K ₂ times that of the unit MOSFET (K ₂ is a constant; K ₂ ≧
The MOS linear transconductance amplifier according to claim 11, which is 1). 13. A ratio (W / L) of a gate width (W) to a gate length (L) of each of the seventh and eighth MOSFETs is determined by the gate width (W) and a gate length (L) of the fifth and sixth MOSFETs. 13) equal to the ratio (W / L).
2. The MOS linear transconductance amplifier according to claim 1. 14. The fifth and sixth MOSFETs connected to the drains of the fifth and sixth MOSFETs, respectively.
Ninth and Tenth Operating as Loads of MOSFET
A second constant voltage is commonly applied to the gates of the ninth and tenth MOSFETs, and a differential output current proportional to the input voltage is provided by the ninth and tenth MOSFETs. 14. The MOS linear transconductance device according to claim 11, which is converted into a voltage and taken out as a differential output voltage.
Amplifier. 15. The MOS linear transconductance element according to claim 11, wherein drains of said seventh and eighth MOSFETs are connected to each other.
Amplifier. 16. The MOS linear transconductance amplifier according to claim 11, wherein the drains of said seventh and eighth MOSFETs are connected to the drains of said fifth and sixth MOSFETs, respectively. . 17. The transconductance value of the second constant current source can be changed by changing the current value of the second constant current source.
21. The MOS linear transconductance amplifier according to any one of claims 1 to 16.