JPH11245829A - Electric motor driving device and electric power steering device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a rush current (rush current) to a power stabilizing capacitor by providing a precharge circuit. A precharge circuit including a diode and a resistor is provided. Ignition switch 52
Is turned on, the power stabilizing capacitor 41 is charged via the precharge circuit. CPU unit 2
1 outputs a relay drive signal 21 b after the time required to charge the power stabilizing capacitor 41 has elapsed, and causes the relay 31 to operate via the relay drive circuit 33. After the power stabilizing capacitor 41 is charged, the contact 31b of the relay is closed, so that an excessive rush current can be prevented from flowing through the contact 31b of the relay, and welding or damage of the relay contact can be prevented. Can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric motor driving device and an electric power steering device.
TECHNICAL FIELD The present invention relates to an electric motor drive device and an electric power steering device that are provided with a precharge circuit to suppress a rush current (rush current) to a power supply stabilizing capacitor.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional electric power steering apparatus. A conventional electric power steering device 101 includes a steering torque detector 102, a vehicle speed detector 103, a control device 104, an electric motor 105, a vehicle-mounted battery power source 106, a fuse 107, an ignition switch 108, and the like. I have. The control device 104 includes a reverse voltage blocking diode 111, a constant voltage circuit (REG) 112, and a control unit (CPU unit) 113.
, A power supply relay drive circuit 114, a power supply relay 115, a gate drive circuit 116, and a drive circuit (F
ET bridge circuit) 117, current detector 118, and power supply stabilizing capacitor 119.

When an ignition switch 108 is turned on (closed), a constant voltage circuit (REG) is supplied from a battery power supply 106 through a fuse 107, an ignition switch 108, and a reverse voltage blocking diode 111.
The battery power supply 106 is supplied to 112. The constant voltage circuit (REG) 112 receives power supply from the battery power supply 106, generates and outputs a circuit power supply VCC (for example, +5 volts).

[0004] The control unit 113 is configured using a microcomputer system. When the circuit power supply VCC is supplied, the control unit 113 starts a control operation based on a control program stored in advance in a ROM or the like. After performing the initialization process, the control unit 113 outputs a power supply relay drive control signal 113a. As a result, the power supply relay 1 via the power supply relay drive circuit 114
The excitation current is supplied to the 15 excitation windings 115a, and the contact 115b of the power supply relay 115 is turned on (closed). When the contact 115b of the power supply relay 115 is turned on (closed), the power supply stabilizing capacitor 11
9 is charged, and the battery power supply 106 is supplied to the gate drive circuit 116 and the drive circuit 117.

A voltage signal (hereinafter referred to as a steering torque signal) T relating to the steering torque detected by the steering torque detector 102 T
S is supplied to the control unit 113. A voltage signal (hereinafter, referred to as a vehicle speed signal) V relating to the vehicle speed detected by the vehicle speed detector 103
S is supplied to the control unit 113. A voltage signal (hereinafter, referred to as a motor current signal) IM related to the motor current detected by the current detector 118 is supplied to the control unit 113. Control unit 1
Reference numeral 13 includes an A / D converter, and each signal TS, V
S and IM are captured as digital quantities. Control unit 113
Calculates a steering assist torque to be supplied from the electric motor 105 based on the steering torque and the vehicle speed, and also calculates a target motor current for generating the calculated steering assist torque.
The control unit 113 obtains a deviation between the target motor current and the motor current IM actually supplied to the motor, and generates and outputs each PWM signal 113b based on the obtained deviation.
Each PWM signal 113b is supplied to the gate drive circuit 116.

The driving circuit 117 is configured by connecting four power field effect transistors Q1 to Q4 in an H-type bridge. The gate drive circuit 116 controls each PWM signal 11
3b based on the power field effect transistors Q1-Q
Gate power is supplied to the fourth gate. Thereby, the PWM operation of the electric motor 105 is performed, and the steering assist torque supplied from the electric motor 105 is controlled.

[0007] A power supply stabilizing capacitor 119 is arranged near the driving circuit 117. By using a large-capacity power supply stabilizing capacitor 119, the power supply impedance is kept low. When the power stabilizing capacitor 119 is not provided and when the power stabilizing capacitor 119 is arranged near the battery power source 106, the switching current waveform and the switching voltage are affected by the impedance of the wiring from the battery power source 106 to the drive circuit 117. The waveform is distorted, and the motor current accurately corresponds to the duty of the PWM signal.
May not be supplied.

The power field effect transistors Q1 to Q4 forming the driving circuit 117 have a parasitic diode formed between the drain and the source due to the structure. In this parasitic diode, the anode is formed on the source side, and the cathode is formed on the drain side. Therefore, when a voltage of opposite polarity is supplied to the drive circuit 117 (when the positive electrode side and the negative electrode side of the battery power supply 106 are connected in reverse), a short-circuit current flows through a parasitic diode, and the characteristics of the power field effect transistors Q1 to Q4 May deteriorate. Therefore, the battery power supply 106
A normally-open contact 115b of a power supply relay 115 is interposed between the power supply relay 115 and the power supply relay 117 to operate the power supply relay 115 when the polarity of the battery power supply 106 supplied to the control device 104 is normal. Like that.

The contact 11 of the power supply relay 115
A circuit configuration in which a power supply stabilizing capacitor 119 is arranged on the subsequent stage side (drive circuit 117 side) of FIG.
It is also shown in FIG.

[0010]

In the circuit configuration in which the power supply stabilizing capacitor 119 is disposed on the rear side (the drive circuit 117 side) of the contact 115b of the supply relay 115, the contact 1
When the power supply 15b is turned on (closed), the power supply stabilizing capacitor 119 is rapidly charged, and the rush current to the power supply stabilizing capacitor 119 causes the contact 115b to be welded. Or may be damaged.

The present invention has been made to solve such problems, and provides an electric motor drive device and an electric power steering device that suppress inrush current (rush current) to a power supply stabilizing capacitor. With the goal.

[0012]

According to the present invention, there is provided a motor drive circuit comprising a precharge circuit for charging a power stabilizing capacitor before closing a relay circuit. Features.

The electric power steering apparatus according to the present invention has a bypass circuit for connecting the battery and the power supply stabilizing capacitor without interposing a relay circuit, and the control unit performs a bypass operation before closing the relay circuit. The power supply stabilization capacitor is charged with electric charge via a circuit. The bypass circuit includes at least a resistor.

Since the motor drive circuit according to the present invention includes the precharge circuit for charging the power stabilizing capacitor with electric charge, the power stabilizing capacitor can be charged via the precharge circuit. The inrush current (rush current) can be eliminated by closing the relay circuit after the power supply stabilizing capacitor is completely charged. Further, by closing the relay circuit in a state where the power stabilizing capacitor is almost charged, the inrush current (rush current) can be suppressed to a small value.

The electric power steering apparatus according to the present invention is provided with a bypass circuit for connecting the battery and the capacitor for stabilizing the power supply without passing through a relay circuit. Therefore, the capacitor for stabilizing the power supply via the bypass circuit is provided. Can be charged. The inrush current (rush current) can be eliminated by closing the relay circuit after the power supply stabilizing capacitor is completely charged. Further, by closing the relay circuit in a state where the power stabilizing capacitor is almost charged, the inrush current (rush current) can be suppressed to a small value.

[0016]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the present embodiment, an electric power steering device will be described as a specific example of the electric motor driving device. FIG. 1 is a schematic structural diagram showing an example of the electric power steering device. The electric power steering device 1 includes an electric motor 10 in a steering system, and controls the power supplied from the electric motor 10 by using the control device 20 to reduce the steering force of the driver.

Steering wheel (steering handle) 2
Is connected to a pinion 6 of a rack and pinion mechanism 5 via a connecting shaft 4 having universal joints 4a and 4b. The rack shaft 7 includes rack teeth 7a that mesh with the pinion 6. The rack and pinion mechanism 5 converts the rotation of the pinion 6 into a reciprocating motion of the rack 7 in the axial direction. Tie rods 8 at both ends of rack shaft 7
The right and left front wheels 9 as rolling wheels are connected via the. When the steering wheel 2 is steered, the front wheels (steering wheels) are driven via the rack & pinion mechanism 5 and the tie rods 8.
9 is rocked. Thereby, the direction of the vehicle can be changed.

In order to reduce the steering force, a motor 10 for supplying a steering assist torque (assist torque) is connected to a rack shaft 7.
The rotation output of the electric motor 10 is converted into a thrust through a ball screw mechanism 11 provided substantially parallel to the rack shaft 7 so as to act on the rack shaft 7. Electric motor 1
The drive side helical gear 10a is provided integrally with the rotor 0. The helical gear 11b and the drive-side helical gear 10a provided integrally with the shaft end of the screw shaft 11a of the ball screw mechanism 11 are meshed. The nut 11c of the ball screw mechanism 11 is connected to the rack shaft 7.

A manual steering torque acting on the pinion 6 is detected by a steering torque detector (steering torque sensor) 12 provided in a steering box (not shown).
The steering torque signal 12a (T
S) is supplied to the control device 20. The control device 20
The motor 10 is operated using the steering torque signal 12a as a main signal to control the output power (steering assist torque) of the motor 10.

FIG. 2 is a block diagram showing a specific example of the control device. The control device 20 includes a CPU 21 and a CP.
U operation monitoring circuit (WDT: watchdog timer) 22
The abnormal-state output stop circuit 23 and the gate drive circuit 24
, A drive circuit (FET bridge circuit) 25, a current detector 26, an A / D converter 27, an abnormality storage unit 28, a constant voltage circuit (REG) 29, and a power-on reset circuit (POR) 30. , A power supply relay 31, a motor cut-off relay 32, relay drive circuits 33 and 34, operation state detection circuits 35, 36 and 37, power supply diodes 38 and 39, and an inrush current limit. It comprises a resistor 40, a power supply stabilizing capacitor 41, and a reverse voltage blocking diode 42 for preventing a reverse voltage from being supplied to the input side of the ignition switch operation state detecting circuit 35. Reference numeral 50 indicates a battery power supply, reference numeral 51 indicates a fuse, and reference numeral 52.
Is an ignition switch, 43 is a vehicle speed detector, and 12 is a steering torque detector.

The power supply relay 31 and the power supply relay drive circuit 33 constitute a relay circuit described in the claims. The power supply diode 38 and the rush current limiting resistor 40 constitute the precharge circuit according to the first aspect and the bypass circuit according to the second aspect. The power stabilizing capacitor 41 is arranged near the drive circuit (FET bridge circuit) 25.

The CPU section 21 includes a CPU, ROM, RA
A microcomputer system including an M, an input / output port, a system controller, and the like is configured using a one-chip microcomputer integrated on one chip. CP
The U unit 21 repeatedly executes various processes for operating the electric motor 10 based on the control program stored in the ROM, and an operation confirmation signal (pulse signal) indicating that the CPU unit 21 is operating normally. 21a is output from the output port O7 at predetermined intervals. For example, the CPU unit 2
1 is to repeat a series of processing such as input processing, arithmetic processing, and output processing and then to perform processing for outputting an operation confirmation signal, so that when the CPU unit 21 is operating normally, a predetermined cycle is performed. To output the operation confirmation signal 21a. In the present embodiment, when the CPU unit 21 is operating normally, the operation confirmation signal 21a is output at a period of about 1.5 milliseconds.

The CPU operation monitoring circuit (WDT) 22
The period of the operation confirmation signal 21a supplied from the output port O7 of the PU unit 21 is monitored. If the period of the operation confirmation signal 21a is out of the preset allowable period range, the CPU
It determines that the operation of the unit 21 is abnormal and outputs an operation abnormality detection signal 22a. In the present embodiment, the CPU operation monitoring circuit (WDT) 22 determines that the cycle of the operation confirmation signal 21a is 2
If the time exceeds milliseconds, and if the period of the operation confirmation signal 21a is less than 1 millisecond, it is determined that the operation of the CPU unit 21 is abnormal, and the L-level operation abnormality detection signal 22a is output. I do. Note that the CPU operation monitoring circuit (WD
T) 22 is configured to start the period monitoring operation of the operation confirmation signal 21a from the time when the supply of the power-on reset signal 30a is stopped.

When an abnormal operation of the CPU section 21 is detected by the CPU operation monitoring circuit (WDT) 22, the abnormal state output stop circuit 23 outputs a signal to the CPU section 21 based on the abnormal operation detection signal 22a. From being supplied to each control object.
An abnormal (undesired) control signal may be output when the CPU goes out of control, but by providing the abnormal output stop circuit 23, an abnormal control signal can be prevented from being supplied to each control target. In the present embodiment, the CP
A two-input AND circuit (logical product circuit) A1 corresponding to each control signal output from each output port O1 to O6 of the U unit 21
To A6, respectively, and each of the two-input AND circuits A1 to A6
When the CPU unit 21 is in a normal operation state, the control signal is supplied to one input terminal of each of the above and the operation abnormality detection signal 22a is supplied to the other input terminal of each of the two-input AND circuits A1 to A6. The control signals output from the output ports O1 to O6 of the CPU unit 21 are supplied to the subsequent circuit units, and when an operation abnormality of the CPU unit 21 is detected, the outputs of the AND circuits A1 to A6 are output. The control signal is set to the L level so that each control signal is not supplied to each circuit unit at the subsequent stage. It should be noted that the output stop circuit 23 at the time of abnormality
The configuration may be such that a three-state buffer circuit is used to set the output side of the three-state buffer circuit to a high impedance state when an abnormal operation of the CPU unit 21 is detected.

The gate drive circuit 24 outputs the output signals from the output ports O3 to O6 of the CPU section 21 to the AND circuits A3 to A3.
Based on the PWM signal supplied via A6, gate power is supplied to the respective gates of the power field-effect transistors Q1 to Q4 constituting the drive circuit (FET bridge circuit) 25.

The current detector 26 detects a current supplied to the motor 10 via a drive circuit (FET bridge circuit) 25, and outputs a voltage signal (motor current signal) IM corresponding to the detected current. The current detector 26 includes a current detection resistor and a DC amplifier that amplifies a voltage generated between both ends of the current detection resistor. The voltage signal IM corresponding to the detected current is supplied to the A / D converter 27. Note that the current detector 26 may be configured using a current sensor having a Hall element.

The A / D converter 27 uses a multiplex input type. Each input terminal of the A / D converter 27 has a voltage signal (vehicle speed signal) VS corresponding to the vehicle speed output from the vehicle speed detector 43, a steering torque output from the steering torque detector 12, and a steering signal corresponding to the steering direction. A voltage signal (steering torque signal) TS and a voltage signal (motor current signal) IM corresponding to the motor current output from the current detector 26 are supplied. The CPU 21
Information for designating an A / D conversion target input to the D converter 27 is supplied via a bus (address bus, data bus, control bus) BUS connected to the bus input / output terminal group BIO of the CPU unit 21. Thus, A / D conversion of the designated input to be converted is performed, and the A / D conversion result is taken in via the bus BUS.

The abnormality storage unit 28 is constituted by a nonvolatile memory such as an EEPROM or a flash memory.
When an abnormality or the like occurs in the control device 20, the CPU unit 21 stores information indicating the content of the abnormality or the like in the abnormality storage unit 28 via the bus BUS. Further, the CPU unit 21 reads out the abnormality information and the like stored in the abnormality storage unit 28 via the bus BUS, changes the control content based on the read abnormality information and the like, and reads the read abnormality information and the like. The data can be transmitted to another device via a serial communication port (not shown).

A constant voltage circuit (REG) 29 supplies a stabilized circuit power supply VCC (for example, 5 volts) based on a DC power supply supplied from a battery power supply 50 via respective power supply diodes 38 and 39. Output. Circuit power supply V
CC indicates a CPU section 21, a CPU operation monitoring circuit 22, an abnormal output stop circuit 23, a current detector 26, an A / D converter 2
7, the abnormality storage unit 28, the power-on reset circuit 30, and the like.

Power-on reset circuit (POR) 30
Outputs a power-on reset signal 30a for a predetermined time from the time when the circuit power supply VCC is supplied.
The power-on reset signal 30a is supplied to a reset input terminal RS of the CPU 21. The CPU section 21 is reset (initialized) by the power-on reset signal 30a.

When the ignition switch 52 is turned on, the battery power supply 50 is supplied from the battery power supply 50 to the constant voltage circuit (REG) 29 via the fuse 51, the ignition switch 52, and one power supply diode 38. The circuit power supply VCC is output from the constant voltage circuit (REG) 29. Power-on reset signal 3
After the reset of the CPU unit 21 by 0a,
The control operation of the CPU section 21 is started. CPU unit 21
Performs an initial state setting process and an initial abnormality detection process described below first.

When the ignition switch 52 is turned on, the battery power supply 50 is supplied to the input terminal of the ignition switch operation state detection circuit 35 via the reverse voltage blocking diode 42. The ignition switch operation state detection circuit 35 outputs an L level signal to an output terminal when a voltage equal to or higher than a predetermined voltage is supplied to the input terminal, and outputs an L level signal when no voltage equal to or higher than the predetermined voltage is supplied to the input terminal. To output an H level (VCC) signal. The output of the ignition switch operation state detection circuit 35 is supplied to the input port I3 of the CPU 21. As a result, the port input I3 of the CPU unit 21 goes low when the ignition switch 52 is on, and goes high when the ignition switch 52 is off. The CPU unit 21 detects the operation state (ON or OFF) of the ignition switch 52 by checking the logical level of the port input I3.

When the CPU 21 detects that the ignition switch 52 is in the ON state, the output port O is set when a preset precharge time has elapsed.
It outputs a power supply relay drive signal 21b of 1 to H level. When the ignition switch 52 is turned on, the power supply stabilizing capacitor 4 is connected via one power supply diode 38 and the inrush current limiting resistor 40.
1 is charged. The precharge time is set to a time until the power stabilizing capacitor 41 in a completely discharged state is almost charged. Thus, after the power stabilizing capacitor 41 is almost charged,
The power supply relay drive signal 21b is output.

The power supply relay drive signal 21b is supplied to the power supply relay drive circuit 3 via a two-input AND circuit A1.
3. The power supply relay drive circuit 33 is configured so that an output transistor (not shown) in the power supply relay drive circuit 33 is turned on when its input terminal goes to H level. Therefore, an exciting current is supplied to the exciting winding 31a of the power supply relay 31 based on the power supply relay drive signal 21b, and the power supply relay 3
One contact 31b is turned on. After the power stabilizing capacitor 41 is almost charged, the contact 31b of the power supply relay 31 is turned on. Therefore, the power stabilizing capacitor 41 is charged via the contact 31b of the power supply relay 31. The current can be suppressed to a small value. The resistance value of the inrush current limiting resistor 40 is set so that the time required for the completely stabilized power supply stabilizing capacitor 41 to reach a charged state is several hundred milliseconds to several seconds.

Further, since the exciting current is supplied to the exciting winding 31a of the power supply relay 31 via the one power supply diode 38, even when the polarity of the battery power supply 50 is erroneously connected, the battery power supply 50 is connected in reverse. Thus, no reverse voltage is supplied to the output side of the power supply relay drive circuit 33. Similarly, no reverse voltage is supplied to the power stabilizing capacitor 41.

When the contact 31b of the power supply relay 31 is turned on, the battery power supply 50
4, and is supplied to the constant voltage circuit 29 via the other power supply diode 39. By providing the battery power supply 50 to the constant voltage circuit 29 via the other power supply diode 39, the contact 31b of the power supply relay 31 is turned on even if the ignition switch 52 is turned off. During this time, the circuit power supply VCC is supplied to each circuit unit via the constant voltage circuit 29 so that each circuit unit can operate.

When the power supply relay 31 is driven to the ON state, the battery power supply 50 is connected via the power supply diode 38 and the contact 31c of the power supply relay 31.
Is supplied to the input terminal of the power supply relay operating state detection circuit 36. Power supply relay operating state detection circuit 36
Outputs an L level signal to an output terminal when a voltage higher than a predetermined voltage is supplied to an input terminal, and outputs an H level (VCC) signal to an output terminal when a voltage higher than a predetermined voltage is not supplied to the input terminal. Output a signal. The output of the power supply relay operating state detection circuit 36 is input port I of the CPU section 21.
2. As a result, the port input I2 of the CPU unit 21 goes low when the power supply relay 31 is in the operating state, and goes high when the power supply relay 31 is in the inactive state. The CPU section 21 detects the operation / non-operation state of the power supply relay 31 by checking the logical level of the port input I2. CP
Although the U unit 21 outputs the H-level power supply relay drive signal 21b from the output port O1,
If it is not possible to detect that the power supply relay 31 is in the operating state, the abnormality storage unit 28 stores abnormality information indicating that the drive of the power supply relay 31 is abnormal.

When the CPU section 21 detects that the power supply relay 31 is operating, it sets the output port O3 to the H level for a predetermined time. This H-level output is supplied to the gate drive circuit 24 via the two-input AND circuit A3, and gate power is supplied from the gate drive circuit 24 to the gate of one field effect transistor Q1 constituting the upper arm. The CPU unit 21 outputs H to the output port O3.
While the level signal is being output, the A / D converter 27
, The detected current value of the current detector 25 is read. CP
If the read current value is not zero (or exceeds a predetermined value), the U unit 21 determines that one of the field effect transistors Q3 constituting the lower arm has a short circuit failure or the like, Information indicating that the field effect transistor Q3 is faulty is written to the abnormality storage unit 28.

Next, the CPU section 21 outputs an H-level signal from the output port O4 to supply gate power to the gate of the other field-effect transistor Q2 constituting the upper arm. By reading the detection current value of the detector 25, it is checked whether or not a short circuit fault has occurred in the other field effect transistor Q4 constituting the lower arm. Further, the CPU unit 21 includes an output port O
5 to output an H level signal, thereby supplying gate power to the gate of one field effect transistor Q3 constituting the lower arm, and reading the detected current value of the current detector 25 in that state, thereby outputting It is checked whether or not a short circuit fault has occurred in one of the field effect transistors Q1 constituting the arm. Further, the CPU unit 21 outputs an H-level signal from the output port O6 to supply gate power to the gate of the other field-effect transistor Q4 constituting the lower arm, and in this state, the current detector 25
By reading the detected current value, it is checked whether or not a short circuit fault has occurred in the other field effect transistor Q1 constituting the upper arm.

By outputting an H-level signal from the output port O3 of the CPU section 21, when the gate power is supplied to the gate of one of the field effect transistors Q1 constituting the upper arm, the field effect transistor Q1 is turned off. Controlled to ON state. In this state, the power supply relay 3
Battery power supply 4 supplied via one contact 31b
0 is supplied to the input terminal of the motor cut-off relay operating state detecting circuit 37 via the field effect transistor Q1 and the normally closed side of the contact 32b of the motor cut-off relay 32.
When the motor shutoff relay 32 is activated, the contact 32
Is in an open state (OFF state), the voltage from the battery power supply 40 is not supplied to the input terminal of the motor cutoff relay operating state detection circuit 37.

Motor operating relay operating state detecting circuit 37
Outputs an L level signal to an output terminal when a voltage higher than a predetermined voltage is supplied to an input terminal, and outputs an H level (VCC) signal to an output terminal when a voltage higher than a predetermined voltage is not supplied to the input terminal. Output a signal. The output of the motor operation relay operating state detection circuit 37 is supplied to the input port I1 of the CPU section 21. As a result, the port input I1 of the CPU section 21 is at the L level when the motor shutoff relay 32 is in the non-operation state, and is at the H level when the motor shutoff relay 32 is in the operation state. CPU unit 21
Detects the non-operation / operation state of the motor cut-off relay 31 by checking the logic level of the port input I1.

The CPU section 21 includes the respective field effect transistors Q 1 to Q 1 constituting the drive circuit (FET bridge circuit) 25.
When the abnormality check of Q4 is completed, an H-level signal is output from the output port O2 of the CPU unit 21 and the port input I
After confirming that the motor shutoff relay 32 is in a non-operating state (L level) based on the logical level of 1, the H level motor shutoff relay drive signal 2 is output to the output port O2.
1c is output. Note that when the CPU unit 21 detects that the motor shutoff relay 32 is operating in a state where the motor shutoff relay drive signal 21c is not output, the operation of the motor shutoff relay 32 is abnormal. Is written to the abnormality storage unit 28.

The motor drive relay drive signal 21c is 2
It is supplied to the motor drive relay drive circuit 34 via the input AND circuit A2. Motor drive relay drive circuit 34
Is configured such that an output transistor (not shown) in the electric motor cutoff relay drive circuit 34 is turned on when its input terminal becomes H level. Therefore, an exciting current is supplied to the exciting winding 32a of the motor cut-off relay 32 based on the motor cut-off relay drive signal 21c, and the contact 32b is switched between the normally closed side and the normally open side. Thereby, the driving circuit (FET bridge circuit) 2
The state in which current can be supplied to the electric motor 10 via the motor 5 will be provided.

When the CPU section 21 detects that the motor cut-off relay 32 has been activated by outputting the motor cut-off relay drive signal 21c from the output port O2, it starts the steering force assist processing described below. I do. If the CPU unit 21 detects that the motor shutoff relay 32 is in the inactive state despite outputting the motor shutoff relay drive signal 21c, the operation of the motor shutoff relay 32 is abnormal. Is written to the abnormality storage unit 28.

When the above-described initial state setting processing and initial abnormality detection processing are completed, the CPU section 21 starts the steering force assist processing. The CPU 21 captures steering torque data corresponding to the steering torque signal TS via the A / D converter 27 and captures vehicle speed data corresponding to the vehicle speed signal VS via the A / D converter 27. CPU
The unit 21 obtains a target motor current corresponding to the steering torque by referring to a steering torque-motor current conversion table provided in the CPU unit 21 and calculates a corrected motor current by correcting the target motor current according to the vehicle speed. I do. CPU unit 2
1 fetches motor current data corresponding to the motor current signal IM via the A / D converter 27, obtains a deviation between the corrected motor current and the motor current actually supplied to the motor 10, and calculates the deviation. The duty of the PWM signal is set based on the PWM signal, a PWM signal having a duty corresponding to the deviation is generated, and the generated PWM signal is output to each of the output ports O3 to O3.
6 to output.

P output from each of the output ports O3 to O6
The WM signal is supplied to the gate drive circuit 24 via each of the two-input AND circuits A3 to A6, and gate power is supplied from the gate drive circuit 24 to the gates of the field effect transistors Q1 to Q4. As a result, the current supplied to the motor 10 via the drive circuit (FET bridge circuit) 25 is switching-controlled, and the PWM operation of the motor 10 is performed.

The CPU section 21 determines that the ignition switch 5 has been turned on based on the change of the input port I3 to the H level.
When it is detected that the motor 2 has been turned off, the motor 1
A fade-out process for gradually reducing the current supplied to 0 is performed. If the steering assist torque is suddenly changed to zero while the steering assist torque is being supplied from the electric motor 10, the steering feeling suddenly changes or the steering wheel 2 is turned by the reaction force from the road surface. May be. Therefore, a state where the steering assist torque is supplied from the electric motor 10 (a state where electric current is supplied to the electric motor 10).
When the ignition switch 52 is turned off, the current supplied to the electric motor 10 is gradually reduced so that a sudden change in the steering feeling is prevented.

After performing the above-described fade-out processing, the CPU section 21 executes a CPU operation monitoring circuit (WDT) 22
Performs an operation test process of the CPU operation monitoring circuit to confirm that the CPU operates normally. The CPU section 21 stops outputting the operation confirmation signal 21a output from the output port O7 every predetermined cycle (for example, 1.5 milliseconds). Alternatively, the CPU unit 21 makes the cycle of the operation confirmation signal 21a output from the output port O7 longer than the upper limit value (for example, 2 milliseconds) of the allowable cycle range. For example, every time a series of processing is repeated, the operation confirmation signal 21a output every time is changed to one.
The operation confirmation signal 21a may be output at twice the predetermined period (for example, 3 milliseconds) by outputting every other time.

The CPU operation monitoring circuit (WDT) 22 does not supply the next operation confirmation signal 21a even if it exceeds the upper limit value (for example, 2 milliseconds) of the allowable cycle range from the time when the operation confirmation signal 21a is supplied first. In this case, an L-level operation abnormality detection signal 22a is output. By this L-level operation abnormality detection signal 22a, the abnormality-time output stop circuit 23
Each relay drive signal 21a, supplied from the U section 21,
21b is prevented from being supplied to each of the relay drive circuits 33, 34, so that each of the relays 31, 32 is inoperative. When the power supply relay 31 returns to the non-operating state, the power supply to the control device 20 is cut off.

Even if the CPU operation monitoring circuit (WDT) 22 does not operate normally and the operation confirmation signal 21a is not supplied for a predetermined time or more, the operation abnormality detection signal 22a
Is not output, the power supply to the control device 20 is continued. Therefore, the CPU unit 21 sets the operation check signal 2
Even if a preset time (for example, several tens of milliseconds to several hundreds of milliseconds) elapses from the time when the output of 1a is stopped or the time when an abnormal operation confirmation signal (test signal) is output, the power supply relay 31 remains When it is detected that the operation is in the operation state, after writing the abnormality information indicating that the operation of the CPU operation monitoring circuit (WDT) 22 is abnormal to the abnormality storage unit 28, the output of the motor supply relay drive signal 21b is output. Stop. As a result, the motor supply relay 31 is restored, and the power supply to the control device 20 is stopped.

The CPU operation monitoring circuit (WDT) 22 determines whether the period of the operation confirmation signal 21a exceeds a predetermined allowable period range (1-2 milliseconds) (exceeds 2 milliseconds), If it is shorter than the range (less than 1 millisecond), it outputs an operation abnormality detection signal 22a. Therefore, under each condition, the CPU operation monitoring circuit (WDT) 2
It is necessary to perform operation test 2 above.

Therefore, the CPU unit 21 writes the test conditions in the abnormality storage unit 28 when performing the operation test of the CPU operation monitoring circuit, and stores the test conditions in the abnormality storage unit 28 prior to the next operation test. The previous test condition is read, and a test condition different from the previous test condition is set. That is, the check of the abnormality detection function when the cycle of the operation check signal 21a becomes longer than the allowable cycle range and the check of the abnormality detection function when the cycle of the operation check signal 21a becomes shorter than the allowable cycle range. , Each time the electric power steering device 1 is used.

When checking the abnormality detection function when the period of the operation confirmation signal 21a is shorter than the allowable period range, the CPU 21 checks the operation confirmation signal for test (test signal) at a period shorter than 1 millisecond. ) Is output continuously. The CPU unit 21 outputs a preset operation time (a CP signal by the CPU operation monitoring circuit 22) from the time when the operation confirmation signal (test signal) having a cycle shorter than 1 millisecond is output.
Even if a time set in consideration of a time until an abnormal operation of the U is detected and a delay time until the relay is restored, for example, several tens to several hundreds of milliseconds, the power supply relay If it is detected that the operation of the CPU 31 is in an operating state, the abnormality information indicating that the operation of the CPU operation monitoring circuit (WDT) 22 is abnormal is written to the abnormality storage unit 28,
The output of the motor supply relay drive signal 21b is stopped. Thereby, the power supply relay 31 is restored, and the power supply to the control device 20 is stopped.

In the present embodiment, an example is shown in which the CPU section 21 constitutes a monitoring operation test means for supplying a test signal outside the allowable cycle range to the CPU operation monitoring circuit 22. A test signal generating circuit for generating a test signal is provided therein, and when the ignition switch 42 is turned off from an on state, the test signal generating circuit is activated to generate a test signal,
The test signal may be supplied to the CPU operation monitoring circuit 22. In this case, the operation confirmation signal 21a output from the CPU unit 21 is output from the CPU operation monitoring circuit 22.
A circuit configuration for preventing supply to the power supply is employed.

The CPU section 21 reads out the abnormality information stored in the abnormality storage section 28 at the time of the next operation state, so that various abnormal contents can be displayed on the driver via a display device or an alarm device (not shown). And so on. CPU unit 2
1 can stop all the functions of the electric power steering device 1 depending on the content of the abnormality.

As described above, the control device 2 shown in FIG.
0 indicates that when the ignition switch 52 is turned on, the power supply stabilizing capacitor 41 is charged via a precharge circuit including the power supply diode 38 and the rush current limiting resistor 40, and then the power supply Since the relay 31 is operated, the capacitor 41 for stabilizing the power supply through the contact 31b of the relay 31 for power supply is provided.
No charging current flows to the battery. Therefore, it is possible to prevent the contact 31b of the power supply relay 31 from being welded or damaged by the charging current (rush current) to the power supply stabilizing capacitor 41. If there is no precharge circuit, a large relay having a large contact current capacity is used and the control device 20 becomes large. However, by providing a precharge circuit, a relay having a small contact current capacity can be used. Thus, the control device 20 can be downsized.

FIG. 3 is a block diagram showing another configuration example of the control device. The control device 60 shown in FIG. 3 compares the voltage across the power supply stabilizing capacitor 41 with the voltage dividing resistors 61 and 62.
Is supplied to the A / D converter 27, and the CPU 21 detects the divided voltage VC via the A / D converter 27, so that the CPU 41 It monitors the state of charge. Power supply stabilizing capacitor 4 via inrush current limiting resistor 40
When 1 is charged, the voltage across the power supply stabilizing capacitor 41 rises exponentially toward the battery power supply voltage.
Therefore, the CPU unit 21 determines the divided voltage VC per unit time.
Of the power supply stabilizing capacitor 41 is determined to be almost charged based on the fact that the amount of change has become equal to or less than a preset value.
1b is output to operate the power supply relay 31. Since the amount of change of the divided voltage VC per unit time is obtained and the power stabilizing capacitor 41 is determined to be almost charged based on the fact that the amount of change is equal to or less than a preset value, The completion of charging can be accurately determined regardless of the power supply voltage of the battery power supply 50.

FIG. 4 is a block diagram showing another example of the configuration of the control device. The control device 60 shown in FIG. 4 includes a voltage dividing resistor 7 on the cathode side of the reverse voltage blocking diode 42.
A voltage dividing circuit composed of a voltage dividing circuit V1 and a voltage dividing voltage V7 obtained by dividing the power supply voltage of the battery power supply 50 by the voltage dividing resistors 71 and 72.
B to the A / D converter 27 and the CPU 2
1 detects a divided voltage VC related to a voltage across the power supply stabilizing capacitor 41 and a divided voltage VB related to the battery power supply voltage via the A / D converter 27, respectively. It is determined that the power supply stabilizing capacitor 41 is almost charged when the divided voltage VC related to the voltage between both ends reaches, for example, 90% of the divided voltage VB related to the battery power supply voltage, and the power supply relay drive signal 21 is determined.
b to output the power supply relay 31. The control device 60 shown in FIG.
The power supply stabilizing capacitor 41 is precharged via the precharge diode 73 and the inrush current limiting resistor 40.

[0059]

As described above, the motor drive circuit according to the present invention includes the precharge circuit for charging the power supply stabilizing capacitor, so that the power supply stabilizing capacitor is charged via the precharge circuit. can do. The inrush current (rush current) can be eliminated by closing the relay circuit after the power supply stabilizing capacitor is completely charged. Further, by closing the relay circuit in a state where the power stabilizing capacitor is almost charged, the inrush current (rush current) can be suppressed to a small value. Therefore, welding and damage of the contacts of the relay can be prevented.

The electric power steering apparatus according to the present invention is provided with a bypass circuit for connecting between the battery and the power supply stabilizing capacitor without using a relay circuit. Therefore, the power supply stabilizing capacitor is provided via this bypass circuit. Can be charged. The inrush current (rush current) can be eliminated by closing the relay circuit after the power supply stabilizing capacitor is completely charged. Further, by closing the relay circuit in a state where the power stabilizing capacitor is almost charged, the inrush current (rush current) can be suppressed to a small value. Therefore, welding and damage of the contacts of the relay can be prevented.

[Brief description of the drawings]

FIG. 1 is a schematic structural view showing an example of an electric power steering device.

FIG. 2 is a block diagram showing a specific example of a control device.

FIG. 3 is a block diagram showing another configuration example of the control device.

FIG. 4 is a block diagram showing still another configuration example of the control device.

FIG. 5 is a block diagram of a conventional electric power steering device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Electric power steering device, 10 ... Electric motor, 2
0, 60, 70: Control device, 21: CPU unit, 25: Drive circuit (FET bridge circuit), 31: Power supply relay, 38: Power supply diode, 40: Inrush current limiting resistor, 41: Power supply stability 50, a battery power supply, 52, an ignition switch, 73, a precharge diode.

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[Procedure amendment]

[Submission date] April 24, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

[Title of the Invention] Electric motor driving device and electric power steering device

Claims (3)

[Claims] 1. An electric motor driving apparatus comprising: an electric motor, a driving circuit for driving the electric motor, a capacitor for stabilizing a power supply connected to both ends of the driving circuit, and a relay circuit provided between a power supply and the driving circuit. 3. The motor drive circuit according to claim 1, further comprising a precharge circuit for charging the power stabilizing capacitor before closing the relay circuit. 2. An electric motor for applying an auxiliary torque to a steering system, a FET bridge circuit for driving the electric motor, a power supply stabilizing capacitor connected to both ends of the FET bridge circuit, a vehicle-mounted battery and the FET bridge A relay circuit provided between the FET and the FET;
An electric power steering apparatus comprising: a control unit that controls a bridge circuit. A bypass circuit that connects the battery and the power stabilizing capacitor without passing through the relay circuit is provided, and the control unit includes the relay unit. An electric power steering apparatus, wherein electric charge is charged to the power stabilizing capacitor via the bypass circuit before closing the circuit. 3. The electric power steering apparatus according to claim 2, wherein a resistor is provided in the bypass circuit.