JPH11243346A - Digital demodulating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a flow error even if a time when a receiving signal level drops is long and signal is lost in a burst manner due to fading and shadowing occurring on a transmission line by interleaving an orthogonal code series that is divided into plural parts to transmit. SOLUTION: A code diving part 50 outputs a series that divides an orthogonal code produced by an orthogonal code generating part 40 into four. An interleaver B60 interleaves with an orthogonal code undergoing four divisions as one unit. A modulating and diffusing part 80 first operates exclusive-OR of both series of a diffusion code series that corresponds to a PN series proper to a base station and a mobile station and an orthogonal code series that is a known series for frame detection and transmission information after four division. Next, it multiplies an output that is acquired by performing data conversion of an exclusive-OR output by a carrier outputted from a local oscillator, converts a diffusion signal of a baseband into a diffusion signal of a high frequency and outputs it to a transmission line 100.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum digital modulator / demodulator in the field of wireless communication systems.

[0002]

2. Description of the Related Art A conventional spread-spectrum modulation / demodulation device is described in, for example, a document "Japanese Patent Laid-Open No. 6-252879M-Array code division multiple access modulation / demodulation device". Hereinafter, the related art will be described with reference to the drawings.

A configuration of a conventional spread spectrum type modulation / demodulation apparatus will be described with reference to FIG. Here, as an example of the spread spectrum signal, binary PSK (B
The configuration in the case of PSK) will be described. In FIG. 18, reference numeral 210 denotes a convolutional coding unit, and 220 denotes a symbol interleaver, which interleaves the output of the convolutional coding unit for each orthogonal code symbol. An orthogonal code generator 230 generates one orthogonal code symbol corresponding to the symbol interleaver output data. Reference numeral 240 denotes a modulation / spreading unit, which generates a modulated signal by spectrally spreading the orthogonal code and converts the orthogonal code into a high-frequency signal. 250 is a transmitting antenna, 260 is a transmission path, 270 is a receiving antenna, 280 is a despreading unit, which converts a received signal from a high frequency to a baseband signal and performs spectrum despreading. A reception timing detection unit 290 generates a reception timing pulse necessary for performing symbol deinterleaving on the reception side. Reference numeral 300 denotes a symbol deinterleaver, which returns the decoding result of the orthogonal code to the time series before interleaving based on the reception timing pulse output from the reception timing detection unit 290. An error correction decoding unit 310 obtains demodulated data after error correction from the output of the symbol deinterleaver 300.

A convolutional encoder 210 has a coding rate R = 1 /
3 (1 input bit number, 3 output bit number), and the generator polynomial is represented by the following equation. ^{g1 = 1 + D 2 + D} 3 + D 5 + D 6 + D 7 + D 8 g2 = 1 + D + D 3 + D 4 + D 7 + D 8 g3 = 1 + D + D 2 + D 5 + D 8 (1)

Here, transmission information I (u) (where u is a time and u = k · T (T is a transmission information one symbol time length and k is an integer) is transmitted to convolutional encoder 210. G1 (u), g2 (u), and g3 (u) are output as generated codes based on the generator polynomial of Equation (1). The 3-bit codes g1 (u), g2 (u), and g3 (u) generated for each time length T are grouped as a set of 6-bit codes obtained for each time length 2T, and the symbol interleaver Output to 220. This grouping is performed, for example, at successive times u1 = 2mT, u2 = (2m + 1) T
(Where m is an integer), the generated codes g1 (u1), g2 (u1), g3 (u1) and g1 (u) for transmission information I (u1) and I (u2), respectively.
2), 6 bits of g2 (u2) and g3 (u2) are converted to 1 symbol SY (t1)
(T1 indicates an arbitrary time, for example, t1 = n · 2T,
Here, n is an integer. The symbol interleaver 220 performs interleaving for each set of data (one symbol SY (t1)).

FIG. 19 explains a symbol interleaving method. Here, an interleave matrix having a symbol interleave size of 8 symbols × 12 is used. In the memory 221 constituting the interleave matrix, data is written in the column direction of the matrix, and the data read direction is set in the row direction. Done in the direction.
Therefore, IL (1,1), IL (2,1),..., IL
(8,1), IL (1,2), IL (2,2), ..., IL (8,2), IL (1,
Input symbol SY in the order of 3), IL (2,3), ..., IL (8,12)
(t) is written, and IL (1,1), IL (1,2), ..., IL (1,1
2), IL (2,1), IL (2,2), ..., IL (2,12), IL (3,1),
The interleaved symbols are read out in the order of IL (3,2),..., IL (8,12) and input to the orthogonal code generator 230. The orthogonal code generation unit 230 selects one of Walsh orthogonal codes representing 64-values corresponding to the input symbols after symbol interleaving (coding 6 bits corresponds to one symbol), and converts the orthogonal code sequence. Output to modulation and spreading section 240.

[0007] Referring to FIG.
Will be described. The orthogonal code sequence generated by orthogonal code generating section 230 and the output of spreading code generator 241 for generating a 256-bit spreading code sequence corresponding to a pseudo noise sequence (PN sequence) unique to the base station and the mobile station are: Multiplier 2
42. The multiplier 242 multiplies a sequence of Walsh orthogonal codes by a spreading code sequence corresponding to a 256-bit PN sequence, and converts the PN sequence to a speed four times the period per bit of the Walsh orthogonal code sequence. To obtain a 256-bit sequence after spreading. The spread sequence is modulated by a multiplier 244 based on the output of a local oscillator 243 that generates a high-frequency carrier wave, and the bandpass filter (BPF) 2
After passing through 45, it is output to transmitting antenna 250.

[0008] The transmission signal output from the transmission antenna 250 is affected by fading, shadowing, noise and the like when passing through the transmission path 260. Next, the demodulation operation on the receiving side will be described using the part after the transmission path 260 in FIG. 270 shown here is a receiving antenna, 28
0 is a despreading unit. The 280 despreading unit will be described with reference to FIG. After passing through the band-pass filter 281, the received signal input to the despreading unit 280 is converted into a baseband signal by the frequency conversion circuit 283 based on the high-frequency signal output from the frequency synthesizer 282.
Further, the spreading code generator 284 outputs the same sequence as the spreading code sequence corresponding to the PN sequence used on the transmitting side. The multiplier 285 multiplies the output of the spreading code generator by the signal converted to the baseband signal, and outputs the multiplication result as a 256-bit despread Walsh orthogonal code sequence (reception side) as a symbol data. Output to interleaver 300.

[0009] A reception timing detector 290 (FIG. 1)
8), in order to detect the head position of the frame, the position of the frame to be received is searched for by correlation detection or the like. Specifically, the transmitting side transmits a known Walsh orthogonal code at the beginning of the frame, and by detecting the correlation of this signal, if the known Walsh orthogonal code is detected, the head of the frame to be received is detected. As a result, a reception timing pulse is generated.

[0010] The reception timing pulse output from reception timing detection section 290 is transmitted to symbol deinterleaver 30.
0, and data is read / written by symbol deinterleaving based on this pulse. In the symbol deinterleaver 300, similarly to the transmitting side, a Walsh orthogonal code consisting of 256 bits, which is oversampled by 4 times, using the memory 301 constituting the deinterleaving matrix shown in FIG. Conversely, data is written in the row direction of the matrix, and data is read in the column direction. Therefore, DIL (1,1), DIL (1,2),..., DIL (1,12), DIL (1,1)
IL (2,1), DIL (2,2), ..., DIL (2,12), DIL (3,1), DI
Input symbols SY (t) are written in the order of L (3,2),..., DIL (8,12), and DIL (1,1), DIL (2,1),. 8,1),
DIL (1,2), DIL (2,2), ..., DIL (8,2), DIL (1,3), DI
The symbols after deinterleaving are read out in the order of L (2,3),..., DIL (8,12), and the error correction decoding unit 310 (FIG.
8).

The error correction decoding unit 310 calculates, for example, the inner product of both code sequences in order to calculate the distance between the received Walsh orthogonal code and the Walsh code to be referred according to a trellis diagram prepared in advance, and calculates each product at each time. The sum of the inner product values in the state is calculated, the path having the largest inner product sum is left as a surviving path, and the other paths are deleted.
Similarly, the calculation of the path is repeated for the received Walsh orthogonal code that is input one after another, and the last surviving path is taken as the maximum likelihood path, the path is traced in reverse, and the decoded data is output from the error correction decoding unit. You.

[0012]

In the case of mobile communication, radio waves are reflected, diffracted, or scattered depending on the surrounding buildings or terrain, and waves (multipath waves) passing through a plurality of transmission paths are transmitted to the mobile station. Rayleigh fading occurs in which the amplitude and phase of the received waves fluctuate randomly because they arrive and interfere with each other. In order to reduce burst errors caused by a decrease in signal level due to this fading, usually,
A transmitter / receiver encodes transmission data, interleaves the encoded data, and performs deinterleaving on the reception side, thereby randomizing burst errors and then performing error correction decoding. Many have been proposed.

However, if the time during which the signal level is reduced due to shadowing or the like is relatively long with respect to the size of the interleaver, the signal transmitted during that time is lost in a burst. ,no longer,
Errors cannot be sufficiently randomized. In particular, when multi-level transmission is performed using orthogonal codes in order to increase the transmission speed, transmission symbols of multi-level symbols are lost in a burst manner, and a subsequent stage has an error correction function. However, there is a problem that a floor error occurs.

In a system using the above interleaver, it is necessary to perform frame synchronization. When using a method of detecting a known sequence existing for each frame by correlation detection in order to know the position of the frame, the known sequence is a sequence having excellent correlation characteristics and does not reduce the transmission efficiency. As described above, there is a problem that a short sequence is required.

Further, for the correlation detector used for the above-described correlation detection, since the transmission symbol is an orthogonal code using a Walsh code, it is necessary to perform correlation reception of the Walsh code in consideration of hardware scale. There is a problem that the use of a correlator is premised, and that a device mounted on a mobile station must be a correlation detector whose circuit scale can be kept small.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. The present invention has been made to solve the above-mentioned problems by using a fading and shadowing method for the interleaver size of the above-mentioned modem apparatus for performing multi-level transmission using orthogonal codes. It is an object of the present invention to provide a modulation / demodulation device in which a floor error is less likely to occur even in a situation where the time during which the level is lowered is relatively long and transmission symbols that are multi-level symbols are lost in a burst.

Further, in the system using the above interleaver, it is necessary to perform frame synchronization, and when a known sequence existing for each frame is detected for correlation in order to know the position of the frame, a sequence having excellent correlation characteristics is obtained. An object of the present invention is to obtain a correlation detector that can use a PN sequence such as an M sequence and that can use a correlator used when performing despreading in consideration of hardware.

[0018]

According to a first aspect of the present invention, there is provided a digital modulation / demodulation apparatus, comprising: a convolutional encoding means for convolutionally encoding input data to generate convolutionally encoded data on a transmission side; Bit interleaving means for interleaving data according to a predetermined rule; and serially / convolutionally coding the convolutionally encoded data interleaved by the bit interleaving means.
Serial / parallel conversion means for performing parallel conversion, orthogonal code generation means for generating orthogonal codes based on the parallel data converted by the serial / parallel conversion means, and a plurality of orthogonal code sequences generated by the orthogonal code generation means. Code division means for dividing, orthogonal code sequences divided by the code division means as one block, interleave means for interleaving block by block, and orthogonal code sequences after code division interleaved by the interleave means, And a modulating and spreading means for transmitting the transmission frame generated by the known sequence adding means by spectrum spreading with a predetermined spreading sequence, and Side, despread the transmitted spread spectrum output. Despreading means, a divided code correlation value generation means for calculating a correlation value for the orthogonal code sequence before code division despread by the despreading means, and a correlation value calculated by the divided code correlation value generation means. A frame detection means for detecting a known sequence and generating a frame timing, and a code on a transmission side using a correlation value calculated by the divided code correlation value generation means and a frame timing generated by the frame detection means. Deinterleaving means for returning the code-divided orthogonal codes after division to a time-sequential order, based on the orthogonal code string returned to the time-sequential order by the deinterleaving means and a frame timing generated by the frame detecting means. , A correlation value for an orthogonal code sequence before code division and a correlation value for decoding an orthogonal code Synthesizing and decoding means, parallel / serial converting means for converting parallel data decoded by the correlation value synthesizing and decoding means into serial data, and convolutional coding based on the serial data converted by the parallel / serial converting means. Bit deinterleaving means for returning the subsequent data in chronological order; and error correction decoding means for decoding the convolutional code based on the serial data returned in chronological order of the data after convolutional encoding by the bit deinterleaving means. It is.

In a digital modulation / demodulation apparatus according to a second aspect of the present invention, the code division means divides an orthogonal code by a Walsh function into 2k (k is an integer), and the correlation value synthesizing and decoding means includes a deinterleave means. Based on the orthogonal code sequence returned to the time series order and the frame timing generated by the frame detecting means, a correlation value for an orthogonal code sequence according to a Walsh function before code division is generated, and decoding of the orthogonal code is performed. Is what you do.

In the digital modulation / demodulation apparatus according to a third aspect of the present invention, the known sequence adding means adds a pseudo noise sequence as a known sequence to the code-separated orthogonal code sequence interleaved by the interleaving unit to form a transmission frame. The frame detecting means generates a known timing of a pseudo noise sequence based on the correlation value calculated by the divided code correlation value generating means, and generates a frame timing.

According to a fourth aspect of the present invention, in the digital modulation / demodulation apparatus, the correlation value synthesizing / decoding means includes an orthogonal code string returned in time-series order by the deinterleaving means and a frame timing generated by the frame detecting means. , A correlation value for an orthogonal code sequence before code division is weighted in proportion to a received signal level, and then combined, and an orthogonal code is decoded based on the obtained correlation value.

A digital modulation / demodulation device according to a fifth aspect of the present invention extracts a maximum correlation value among correlation values of an orthogonal code sequence obtained by the correlation value combining and decoding means,
A soft-decision information generating means for generating soft-decision information for Viterbi decoding in accordance with an output of the deinterleaving means performed after orthogonal code decoding based on an absolute value calculation result of the correlation value; Obtains serial data returned by the bit deinterleaving means in chronological order of the data after convolutional coding based on the soft decision information from the soft decision information generating means, and decodes the convolutional code based on the serial data. Is what you do.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 In this embodiment,
This is a digital modulation / demodulation device that transmits and receives data using the M-ary SS communication system using orthogonal codes.

This embodiment will be described with reference to FIG. Here, as an example of the spread spectrum signal, 2
A configuration in the case where the next modulation is binary PSK (BPSK) will be described. In FIG. 1, reference numeral 10 denotes a convolutional coding unit;
Is an interleaver A, which interleaves the output of the convolutional encoder for each bit. A serial / parallel conversion unit 30 parallelizes data output from the interleaver A for each bit number corresponding to one symbol of the orthogonal code. Reference numeral 40 denotes an orthogonal code generation unit for generating one symbol of a 64-valued orthogonal code from the parallelized data, and reference numeral 50 denotes a code division unit, which divides the generated orthogonal code into four and outputs it. Reference numeral 60 denotes an interleaver B for interleaving the code-divided orthogonal codes. A known sequence adding unit 70 adds a known sequence having excellent correlation characteristics to the head of information to be transmitted. Reference numeral 80 denotes a modulation / spreading unit, which spreads the spectrum of the data output from the interleaver B to generate a modulated signal and converts it into a high-frequency signal.

Reference numeral 90 denotes a transmitting antenna, 100 denotes a transmission line, 1
Reference numeral 10 denotes a receiving antenna, and 120 denotes a despreading unit that converts a high-frequency received signal into a baseband received signal and performs spectrum despreading. Reference numeral 130 denotes a division code correlation value generation unit that temporarily decodes code-divided orthogonal codes obtained after despreading. Reference numeral 140 denotes a frame detection unit which detects a frame position of a received frame and outputs a frame timing pulse. Reference numeral 150 denotes a deinterleaver B, which deinterleaves a code-divided orthogonal code temporarily decoded based on a frame pulse output from the frame detection unit. Reference numeral 160 denotes a correlation value combining and decoding unit, based on the correlation value calculation result after deinterleaving, for generating orthogonal codes before division, and after combining and decoding correlation values of code-divided orthogonal codes, The decoding result is output as parallel data. 170 is a parallel / serial converter,
The parallel data, which is the result of orthogonal code decoding obtained by the correlation value combining and decoding unit 160, is converted into serial data. Reference numeral 180 denotes a deinterleaver A, which restores the chronological order before the interleaving performed by the interleaver A. Reference numeral 190 denotes a Viterbi decoding unit which performs error correction using the output of the deinterleaver A and outputs demodulated data.

The convolutional encoder 10 has a coding rate R = 1/3.
This is a convolutional code having (number of input bits 1, number of output bits 3), and a generator polynomial is represented by, for example, the following equation. ^{g1 = 1 + D 2 + D} 3 + D 5 + D 6 + D 7 + D 8 g2 = 1 + D + D 3 + D 4 + D 7 + D 8 g3 = 1 + D + D 2 + D 5 + D 8 (2)

Here, the transmission information I (u) (where u is the time and u = k · T (T is the transmission information one symbol time length, k is an integer)) is sent to the convolutional encoder 10. G1 (u), g2 (u), and g3 (u) are output as generated codes based on the generator polynomial of Equation (1). The 3-bit encoded data g1 (u), g2 (u), and g3 (u) generated for each time length T are sequentially input to the interleaver A20 at intervals of T / 3.

FIG. 2 illustrates the method of interleaver A20. Here, an interleave matrix having an interleaver size of 30 bits × 30 bits is used. Memory 2 that constitutes this interleave matrix
In 1, the data write (input) direction is performed in the column direction of the matrix, and the data read direction is performed in the row direction. Therefore, ILA (1,1), ILA (2,
1), ..., ILA (30,1), ILA (1,2), ILA (2,2), ...
・, ILA (30, 2), ILA (1, 3), ILA (2, 3), ..., ILA (30,
30) Input bits (encoded data) are written in the order of
LA (1,1), ILA (1,2), ..., ILA (1,30), ILA (2,1), IL
A (2,2), ..., ILA (2,30), ILA (3,1), ILA (3,2), ...
.., Bit data after interleaving is read out in the order of ILA (30, 30) and input to the serial / parallel converter 30.

The serial / parallel converter 30 converts 1-bit data input serially into 6-bit parallel data by grouping the data into groups of 6 bits. The 6-bit parallel data is output to the orthogonal code generation unit 40 at intervals of 2T.

The orthogonal code generator 40 generates a 64-ary orthogonal code using 6-bit parallel data as one symbol. Specifically, an operation is performed in which one of orthogonal codes representing 64 values is selected in accordance with the input parallel data, and the selected orthogonal code sequence is output to the code division unit 50. .

In the code division section 50, the orthogonal code generation section 40
(The number of elements of one codeword n: 2 ⁶
= 64) is output. 3 and 4 show examples of code division. Here, for simplicity of description, first, a description will be given using a 16-level orthogonal code as an example. In FIG.
H ₄ is one in which the number of one codeword elements showed all 16 values orthogonal code element 16 (= 2 ⁴⁾ a matrix of 16 × 16.

This orthogonal matrix (for example, an orthogonal matrix based on the Walsh function) has 16 types of codes C _{1 to} C ₁₆ ,
Due to the nature of this matrix, H ₃ (= 2 ³
× 2 ³ ). Similarly, this matrix H ₃ is a matrix of the next lower dimension, H ₂ (= 2 ² × 2
² ) can be used. For the matrix H ₄ having properties as described above, as a chain line in FIG. 3, the vertical (1) to (4) in the split line elements were respectively a collection, can be performed divided into four of the code . 4 divided orthogonal code, respectively, can be expressed as an element of the matrix of H _2.

Next, considering the 64-ary orthogonal code used in the present embodiment, as shown in FIG. 4, the matrix of H ₆ (= 2 ⁶ × 2 ⁶ ) is represented by H ₄ (= 2 ⁴ × 2 ⁴ ). Since it is possible to write, as shown by a chain line in FIG. 4, reference numeral 4 represents a group of elements of a row vertically divided into (1) to (4).
Division can be performed. The quadrature codes divided into four are respectively
It may be represented as an element of the matrix of H ₄ (16-bit sequence), and outputs a sequence of orthogonal codes after 4 divided interleaver B60.

In the interleaver B60, the interleaving is performed using the orthogonal code (16-bit sequence) after the division into four as one unit (block). FIG. 5 illustrates the interleaving method. Here, an interleave matrix having an interleaver size of 4 × 225 blocks is used. One block contains 16 bits of the orthogonal code divided into four. In the memory 61 forming this interleaving matrix, it is assumed that data is written (input) in the column direction of the matrix and data is read in the row direction. Therefore, ILB (1,1), ILB (1,2),..., ILB (1,4), ILB
B (2,1), ILB (2,2), ..., ILB (224,1), ILB (224,2),
Input bits (encoded data) are written in the order of ILB (224,3),..., ILB (225,4), and ILB (1,1), ILB (2,1),.
・ 、 ILB (3,1) 、 ・ ・ ・ 、 ILB (224,1) 、 ILB (225,1) 、 ・ ・
・ 、 ILB (1,2) 、 ILB (2,2) 、 ・ ・ ・ 、 ILB (225,2) 、 ・ ・
A sequence of interleaved quadrant orthogonal codes (16-bit sequence) is read out in the order of ILB (224,4) and ILB (225,4), and output to the known sequence adding unit 70.

The known sequence adding section 70 adds, for example, a 16-bit PN sequence as a known sequence having excellent correlation characteristics to the head of information to be transmitted. This series is
It is obtained by adding “0” to the longest part of the sequence of “0” in the 15th longest linear sequence (M sequence) represented by “1” and “0”. FIG. 6 shows a frame format. The time length of one bit period of the known sequence is T /
2 (where T is the transmission information one symbol time length).
This corresponds to 1/4 of the time of one symbol of the orthogonal code before division into four.

The modulation and spreading section 80 will be described with reference to FIG. 81 is an exclusive OR (EXOR), 8
2 is the PN sequence generator, 83 is the EXOR output from “0” →
A data converter for converting "+1" into "1" → "-1"; 84, a local oscillator; 85, a multiplier for converting a baseband spread signal into a high-frequency spread signal by a carrier of the local oscillator 84; , 86 are band pass filters (BP
F).

Next, the operation of the modulation and spreading section 80 will be described. A spread code sequence (256-bit sequence) corresponding to a PN sequence unique to the base station and the mobile station, and a quadrature code sequence after division into four (4 symbols) each of which is a known sequence for frame detection and transmission information. ) Is input to the exclusive OR 81, and the exclusive OR of both the series is calculated. The exclusive OR 81 spreads 1 bit of the known sequence for frame detection at a period of 1/256 of a 1-bit period. By spreading at a period of 1/16 of one bit period, a sequence of 256 bits after spreading is obtained. In the data conversion unit 83, the exclusive OR 81 output “0”,
The data of "1" is converted into data of "+1" and "-1", respectively. The multiplier 85 multiplies the output of the data conversion unit 83 by the carrier output from the local oscillator 84 to convert the baseband spread signal into a high-frequency spread signal. The band pass filter 86 limits the band of the high-frequency spread signal.

The transmitting antenna 90 outputs the output of the modulation and spreading section 80 to the transmission line 100.

When passing through the transmission path 100, the transmission signal transmitted from the transmission antenna 90 is affected by fading, shadowing, noise, and the like.

Next, the demodulation operation on the receiving side will be described with reference to the part after the transmission line 100 in FIG. 110 is a receiving antenna for receiving a signal on the transmission path, and 120 is a despreading unit. Hereinafter, the despreading unit 120 will be described with reference to FIG. In FIG. 8, reference numeral 121 denotes a band-pass filter;
2 is a frequency synthesizer, 123 is a frequency conversion circuit, 1
24 is a PN sequence generator, and 125 is a multiplier. Here, the operation of the despreading unit 120 will be described. The band-pass filter 121 limits the band of the received signal. The frequency synthesizer 122 generates a high-frequency signal for converting a high-frequency received signal into a baseband signal. The frequency conversion circuit 123 uses a frequency synthesizer output,
Convert the received signal to a baseband signal. The PN sequence generator 124 generates the same 256-bit sequence as the spreading code sequence corresponding to the unique PN sequence used on the transmission side. However, the PN sequence generated on the receiving side is output as “0” and “1” on the transmitting side due to signal processing.
Output as a series of +1 and -1. Multiplier 1
At 25, the PN sequence is multiplied by the baseband received signal, and the despread signal is output. The output of the multiplication result is a received code sequence (in-phase and quadrature components) after despreading of 256 bits each, and the divided code correlation value generation unit 1
30 is input.

The division code correlation value generation section 130 uses the in-phase component (Ich) and the quadrature component (Qch) of the despread received signal output from the despreading section 120, and divides the quadrature signal into four by the receiving side. Among the codes, a correlation value corresponding to all transmission candidate sequences is calculated. In this case, four divided orthogonal codes themselves, as in the matrix of the orthogonal code sequence H ₄ shown in FIG. 3, to become a sequence of 16 symbols, the 16 required as the number of correlators . In the quadrature code divided into four, the correlation value itself has a positive or negative value.
It is necessary to prepare (= 16 × 2) kinds of correlation values.

Referring to FIG. 9, 32 types of correlation value generation methods will be described. In FIG. 9, 131, 132, 1
33 are the in-phase components (Ic
h) a correlator 134, 135, 136 for calculating a correlation value of the quadrature code divided into four using the quadrature component (Qch).
Are orthogonal code generators 137, 138, and 139 that output respective orthogonal code sequences, respectively, are sign inverters that invert the sign of the output of each correlator.

Next, the operation of FIG. 9 will be described. 16 in the figure
In the type of correlator, the in-phase component (Ich) and the quadrature component (Qch) of the despread received signal output from the despreading unit 120 are used to calculate the correlation value of the quadrature code divided into four on the receiving side. I do. Corresponding to all transmission sequence candidates of quadrant orthogonal code,
In order to obtain 32 types of correlation value outputs having positive and negative values, for 16 correlator outputs, those corresponding to positive correlation values use the 16 correlator outputs as they are. . On the other hand, the sign inverting unit inverts the signs of the outputs of the 16 correlators. The value corresponding to the negative correlation value is calculated by inverting the sign of the 16 correlator outputs in the sign inverter. 32 types of correlation values obtained for each period (1 symbol) of the quadrature orthogonal code divided into 4
These correlation values are grouped and input to the deinterleaver B150 having 32 inputs per block.

In a system using the above interleaver, it is necessary to perform frame synchronization. In order to detect the head position of the frame, the frame detection unit 140 performs correlation detection of a known sequence using the received signal (received code sequence) despread by the despreading unit.

FIG. 10 shows the structure of the frame detecting section. 1
Reference numeral 41 denotes a code determiner that determines the code of the correlator, and 142 denotes a known sequence detector that outputs a frame timing pulse. Next, the operation will be described. First, using a division code correlation value generation unit 130 outputs, among the correlator outputs for orthogonal decoding which is divided into four, a reference to the C ₁ in the matrix of the orthogonal code sequence H ₄ as shown in FIG. 3 (That is,
The output of the correlator (corresponding to all "0") is used. The sign determiner 141 determines “0” if the sign of the correlator output corresponding to the code sequence C ₁ is positive, and “1” if the sign is negative, and sends the determination result to the known sequence detector 142. Output.

In the known sequence detector 142, the known sequence added to the head of the frame on the transmitting side, 16
Correlation detection is performed using the same sequence as the PN sequence of bits, and when the correlation output exceeds a predetermined threshold value, a frame timing pulse is generated assuming that the head of the frame to be received has been detected. The obtained frame timing pulse is used as a pulse of a reference timing when performing deinterleaving, and is used as a deinterleaver B15.
Output to 0. This pulse is also output to correlation value synthesizing and decoding section 160 which synthesizes and decodes the correlation values.

The deinterleaver B150 performs deinterleaving by using the correlation values of the 32 types of quadrature codes divided by 32 input from the divided code correlation value generator 130 as one block. FIG. 11 illustrates the deinterleaving method. Here, a matrix of 4 × 225 blocks is used as the size of the deinterleaver.
In the memory 151 constituting this deinterleave matrix, the data write (input) direction is performed in the row direction of the matrix and the data read direction is performed in the column direction, contrary to the interleaver B on the transmission side. It is. Therefore,
In the above memory, DILB (1,1), DILB (2,1), DILB (3,1),
.., DILB (225,1), DILB (1,2), DILB (2,2), ..., D
ILB (225,2), DILB (1,3), DILB (2,3), ..., DILB (22
Input bits (encoded data) are written in the order of 5, 3, 3), DILB (1, 4), DILB (2, 4), ..., DILB (225, 4).
(1,1), DILB (1,2), ..., DILB (1,4), DILB (2,1), DI
LB (2,2), ..., DILB (2,4) ..., DILB (225,1), DIL
B (225,2),..., DILB (225,4) in order, the correlation values of the deinterleaved 32 quadrant divided quadrature codes are set to 1
Reading is performed for each block and output to correlation value synthesis and decoding section 160.

The correlation value synthesizing and decoding section 160 synthesizes the correlation values of the quadrature code divided by four on the basis of the frame timing pulse obtained from the frame detection section 140 for every four, and divides them by four on the receiving side. Generate a correlation value for the orthogonal code sequence before The combining method will be described with reference to FIG. The output of one block deinterleaver B150 is contains 32 kinds of correlation value, the correlation value of the 32 types, 16 types of orthogonal code sequences and correlation value H _4, orthogonal code sequence Baar H ₄ which also 16 types of In order to generate an orthogonal code sequence corresponding to H ₆ before being divided, 32 types of correlation values obtained for these H ₄ and Baer H ₄ sequences are shown in FIG. By combining according to the form of the matrix, 64 types of correlation values are calculated. Then, of the 64 calculated correlation values, the parallel / serial conversion unit 1 decodes 6-bit parallel data corresponding to the orthogonal code sequence having the maximum correlation value as a decoding result.
70 is output.

In parallel / serial conversion section 170, 6
Bit parallel data is converted to serial data,
Output to the deinterleaver A180.

FIG. 12 illustrates the method of the deinterleaver A180. Since the interleaving matrix of 30 bits × 30 bits is used as the size of interleaver A on the transmitting side, the size of the deinterleaving matrix on the receiving side is 30 bits × 30 bits as in the transmitting side.
Use a 30-bit matrix. In the memory 181 constituting this deinterleaving matrix, unlike the interleaver A on the transmitting side, the data writing (input) direction is performed in the row direction of the matrix, and the data reading direction is performed in the column direction. is there. Therefore, in the above memory, DILA
(1,1), DILA (1,2), ..., DILA (1,30), DILA (2,1), D
ILA (2,2), ..., DILA (2,30), DILA (3,1), DILA (3,
2),..., DILA (3, 30),..., DILA (30, 30), input bits (encoded data) are written in this order, and DILA (1,
1), DILA (2,1), ..., DILA (30,1), DILA (1,2), DILA
(2,2), ..., DILA (30,2), DILA (1,3), DILA (2,3), D
The bit data after deinterleaving is read out in the order of ILA (30, 3),..., DILA (30, 30), and the Viterbi decoder 190
Is output to

The Viterbi decoding section 190 performs Viterbi decoding based on hard decision. Specifically, an exclusive OR of the input bit data after deinterleaving and the bit data to be referred to is calculated, and this is set as a branch metric, and a path metric is calculated according to a trellis prepared in advance. , Leaving the smallest path as the surviving path and deleting the other paths. Similarly, it repeatedly calculates a path for bit data input one after another, and takes the path that has survived last as the maximum likelihood path, reverses the path, and outputs decoded data.

As described above, in the present embodiment, since the orthogonal code sequence is divided into four parts and the divided orthogonal code sequences are interleaved and transmitted, the received signal level is reduced by fading and shadowing received on the transmission path. The modulation and demodulation device in which a floor error hardly occurs can be obtained even when the signal is relatively long and the signal is lost in a burst manner.

Further, in the above-mentioned modem, when decoding the orthogonal code, the correlation value of the quadrature code sequence divided into four is calculated and synthesized according to the obtained 32 kinds of orthogonal code matrices. The number of correlators for calculating the correlation value is 3
It can be reduced to two, and the hardware scale can be reduced.

Further, when a known sequence existing for each frame is detected for correlation in order to detect the position of the frame, a PN sequence such as an M sequence can be used as a sequence having excellent correlation characteristics. Correlation detectors that can utilize the correlators used can be used. In the above example, the same effect can be obtained by using a Walsh orthogonal code as the orthogonal code.

Embodiment 2 FIG. 13 shows a configuration example of a digital modulation / demodulation device for transmitting and receiving data using the M-ary SS communication system according to the present embodiment.
In the first embodiment, a predetermined method is used in correlation value combining and decoding section 160 in order to obtain a correlation value of an orthogonal code before division into four from a correlation value of an orthogonal code divided into four (for example, a Walsh orthogonal code). , The correlation values after the four divisions are combined as they are, but the correlation value combining and decoding unit 160A in the present embodiment uses 4
After weighting the correlation values after division in proportion to the received signal level, synthesis is performed. Therefore, the present embodiment has the same configuration as FIG. 1 of Embodiment 1 except for the correlation value combining and decoding section 160A, and the description of the same configuration will be omitted.

Next, the operation of the correlation value synthesizing and decoding section 160A will be described with reference to FIG.

In FIG. 14, reference numeral 161A denotes an absolute value circuit for calculating an absolute value for generating a weighting coefficient by removing a sign portion from 32 types of correlation values.
162A is a multiplier that multiplies the correlation coefficient by the weighting coefficient obtained in 161A and weights the correlation value.

Here, the weighting method will be described. One output block of the deinterleaver B150 includes:
There are 32 types of correlation values, and the one having the largest correlation value is considered to be a sub-optimal estimation result for the quadrature code sequence divided into four. In particular, when the carrier phase synchronization is perfect, it can be expected that the absolute value of the maximum correlation value is proportional to the received signal level.
Therefore, 32 weighting portions shown in FIG. 14 are prepared, and for each of the correlation values of the 32 types of quadrature code sequences divided into 32 types, a value proportional to the absolute value of the correlation value is weighted to each correlation value, The correlation values for estimating the orthogonal code sequence before division are calculated using the correlation values of the 32 types of quadrature orthogonal code sequences after weighting according to the same code composition rule as in the first embodiment. Further, the maximum orthogonal code sequence is selected from the 64 types of correlation values obtained after the code synthesis, and predetermined parallel bit data corresponding to the code sequence is converted into data obtained by decoding the orthogonal code. Output as

As described above, in this embodiment, 4
Weighting is performed according to the absolute value of the correlation result obtained for each correlator of the orthogonal code sequence after division, and since there is a synthesizing means for synthesizing these weighting results, the influence of received signal level fluctuation such as fading and shadowing is provided. It is possible to reduce errors at the time of orthogonal code decoding due to the reception, and to obtain good bit error rate characteristics.

Embodiment 3 FIG. 15 shows a configuration example of a digital modulation / demodulation device that transmits and receives data using the M-ary SS communication method according to the present embodiment.
In the first embodiment, Viterbi decoding based on hard decision is performed in Viterbi decoding section 190, but in the present embodiment, Viterbi decoding is performed using soft decision information in order to further reduce bit errors. Since the configuration of the part before the correlation value combining and decoding unit 160A is the same as that of the first embodiment, the description is omitted.

Referring to FIG. 15, a description will be given centering on the configuration of this embodiment different from that of the first embodiment. Reference numeral 160A denotes a correlation value combining and decoding unit, which outputs the maximum correlation value obtained for each orthogonal code symbol after code combining and the data corresponding to the orthogonal code having the maximum correlation value as the decoding result of the orthogonal code. I do. Also, 170 and 180 are a parallel / serial converter and a deinterleaver A having the same configuration as in the first embodiment. Reference numeral 190A denotes a Viterbi decoding unit which performs Viterbi decoding using soft decision information in order to perform error correction. 200 is a soft decision information generation unit,
It generates soft decision information for the Viterbi decoding unit 190A that performs error correction.

Next, a method of generating soft decision information in soft decision information generating section 200 of the present embodiment will be described with reference to FIG. The absolute value circuit 201 calculates the absolute value of the maximum correlation value obtained for each orthogonal code symbol after code synthesis output from the correlation value synthesis and decoding unit 160A. The parallel / serial converter 202 converts the absolute value output into six parallel data and converts it into serial data. The deinterleaver C203 is a parallel / serial converter 2
02 is deinterleaved according to the same deinterleaving rule as deinterleaver A. Data converter 2
04 is a deinterleaver A output “0”, “1”
Data "+1", "-1"
Respectively. The delay unit 205 includes a data processing delay time from the maximum correlation value output in the correlation value combining and decoding unit 160A to the output of the deinterleaver C, and a processing from the orthogonal code decoded data output to the deinterleaver A in the correlation value combining and decoding unit 160A. The delay adjustment is performed so that the data processing delay time becomes the same. The multiplier 206
The soft decision information is generated by multiplying the output of the data conversion unit 204 by the output of the delay unit 205.

Here, the operation from the correlation value synthesizing and decoding section 160A to the Viterbi decoding section 190A, which is the difference between the present embodiment and the first embodiment, will be described. In addition, regarding the configuration before the correlation value synthesis and decoding unit 160A,
Since the configuration and operation are the same as those of the first embodiment, the description is omitted. Correlation value combining / decoding section 160A has 64 bits, similarly to correlation value combining / decoding section 160 of the first embodiment.
A type of correlation value is calculated, and among the calculated 64 types of correlation values, 6-bit parallel data corresponding to the orthogonal code sequence having the maximum correlation value is output to the parallel / serial conversion unit 170 as a decoding result. I do. Further, in addition to the above function, correlation value synthesizing / decoding section 160A outputs the largest correlation value to soft decision information generating section 200. Parallel / serial converter 170
Then, the decoding result, which is parallel data obtained by the correlation value synthesizing and decoding unit 160A, is converted into serial data.

In the deinterleaver A180, the parallel / interleaver
The data input from the serial conversion 170 is returned to the time-series order before the interleaving performed by the interleaver A. The soft decision information generation section 200 creates soft decision information using the maximum correlation value data input from the correlation value synthesis and decoding section 160A and the data output of the deinterleave A180. The Viterbi decoding 190A performs Viterbi decoding using the soft decision information output from the soft decision information generation unit 200, and outputs decoded data. Specifically, the inner product of the input soft decision information and the data to be referred to is obtained, and this is used as a branch metric,
The path metric is calculated according to a trellis prepared in advance, the path having the maximum path is left as a surviving path, and the other paths are deleted. Similarly, for the bit data input one after another, the path is repeatedly calculated, and the path that has survived last is taken as the maximum likelihood path, and the path is traced in reverse.
It outputs decoded data.

As described above, in this embodiment, since means for generating soft decision information is provided, errors during decoding due to the influence of received signal level fluctuations such as fading and shadowing and noise are reduced. And good bit error rate characteristics can be obtained.

Embodiment 4 FIG. 17 shows a configuration example of a digital modulation / demodulation device that transmits and receives data using the M-ary SS communication method according to the present embodiment. In the third embodiment, Viterbi decoding based on soft decision is performed in Viterbi decoding section 190A. However, in the present embodiment, in order to further reduce bit errors, the correlation value synthesizing and decoding section 160B uses the first embodiment. As in the case of the correlation value combining and decoding unit 160A in 2, the correlation value after division into four is weighted in proportion to the received signal level and then combined. Therefore, this embodiment is different from the third embodiment in FIG. 1 except for the correlation value combining and decoding section 160B.
5, and the description of the same components will be omitted.

Referring to FIG. 14, only the correlation value synthesizing and decoding section 160B according to the present embodiment different from the third embodiment will be described. As in the case of describing the method of weighting and combining in the second embodiment, in FIG. 14, 161A generates an absolute value for the 32 types of correlation values in order to generate a weighting coefficient by removing the sign part. Value circuit,
162A is a multiplier that multiplies the correlation coefficient by the weighting coefficient obtained in 161A and weights the correlation value.

Here, the weighting method will be described. One output block of the deinterleaver B150 includes:
There are 32 types of correlation values, and the one having the largest correlation value is considered to be a sub-optimal estimation result for the quadrature code sequence divided into four. In particular, when the carrier phase synchronization is perfect, it can be expected that the absolute value of the maximum correlation value is proportional to the received signal level.
Therefore, 32 weighting portions shown in FIG. 14 are prepared, and for each of the correlation values of the 32 types of quadrature code sequences divided into 32 types, a value proportional to the absolute value of the correlation value is weighted to each correlation value, A correlation value for estimating an orthogonal code sequence before division is calculated using the correlation values of the 32 types of quadrature orthogonal code sequences after weighting according to the same code composition rule as in the third embodiment. Further, the maximum orthogonal code sequence is selected from the 64 types of correlation values obtained after the code synthesis, and predetermined parallel bit data corresponding to the code sequence is converted into data obtained by decoding the orthogonal code. Output as Further, the correlation value synthesizing / decoding section 160B outputs, in addition to the function, the one having the maximum correlation value to the soft decision information generating section 200.

As described above, in the present embodiment, 4
Since weighting is performed in accordance with the absolute value of the correlation result obtained for each correlator of the orthogonal code sequence after division, and combining means for combining these weighting results and means for performing Viterbi decoding based on soft decision information, fading or It is possible to reduce errors during orthogonal code decoding due to the influence of received signal level fluctuations such as shadowing, and to obtain good bit error rate characteristics.

[0070]

According to the first aspect of the present invention, the orthogonal code sequence is divided into a plurality of segments, and the divided orthogonal code sequences are interleaved and transmitted. Therefore, the received signal level is reduced by fading and shadowing received on the transmission path. It is possible to obtain a modulation and demodulation device in which a floor error is unlikely to occur even when a signal is lost in a burst because the time during which the signal is dropped is relatively long.

According to the second aspect of the present invention, since the orthogonal code based on the Walsh function is divided by 2k (k is an integer) and the divided orthogonal code sequence is output as one block to the interleave means, the code division means is provided. Even when the received signal level is relatively long due to fading and shadowing on the road and the signal is lost in a burst, the floor error is not easily generated and the correlation value of the Walsh orthogonal code is used. Can be reduced in the total number of correlators for calculating.

According to the third aspect of the present invention, since a known sequence adding unit for adding a pseudo noise sequence having excellent correlation characteristics as a known sequence is provided, a known sequence having a short sequence length which does not reduce the transmission efficiency of a frame can be used.

In the fourth invention, in order to obtain the correlation value of the orthogonal code before code division, the correlation value after code division is weighted in proportion to the received signal level by a predetermined method, and then combined, Since it has a correlation value synthesis and decoding means for performing decoding based on the obtained correlation value, fading and shadowing received on the transmission path enable
Even when a signal is lost in a burst, a floor error can be made less likely to occur.

According to the fifth aspect of the present invention, the maximum correlation value among the correlation values of the orthogonal code sequence obtained by the correlation value combining and decoding means is extracted, and the orthogonal code is calculated based on the absolute value calculation result of the correlation value. Generates soft decision information for Viterbi decoding according to the output of the deinterleaving means performed after decoding, and further includes error correction decoding means for performing error correction based on the soft decision information, so that fading, shadowing, etc. It is possible to reduce errors during orthogonal code decoding due to the influence of received signal level fluctuation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a digital modulation / demodulation device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a bit interleaver according to Embodiment 1 of the present invention.

FIG. 3 is a diagram showing a matrix of 16-ary orthogonal codes based on a Walsh function in the first embodiment of the present invention.

FIG. 4 is a diagram showing a matrix of 64-ary orthogonal codes based on a Walsh function according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of an interleaver according to Embodiment 1 of the present invention.

FIG. 6 is a diagram illustrating a configuration of a transmission frame according to Embodiment 1 of the present invention.

FIG. 7 is a diagram illustrating a configuration of a modulation and spreading unit according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a despreading unit according to Embodiment 1 of the present invention.

FIG. 9 is a diagram illustrating a configuration of a divided code correlation value generation unit according to the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration of a frame detection unit according to the first embodiment of the present invention.

FIG. 11 is a diagram illustrating a configuration of a deinterleaver according to the first embodiment of the present invention.

FIG. 12 is a diagram illustrating a configuration of a bit deinterleaver according to the first embodiment of the present invention.

FIG. 13 is a diagram showing a configuration of a digital modulation / demodulation device according to a second embodiment of the present invention.

FIG. 14 is a diagram illustrating a correlation value combining and weighting generation method for a decoding unit according to the second embodiment of the present invention.

FIG. 15 is a diagram showing a configuration of a digital modulation / demodulation device according to a third embodiment of the present invention.

FIG. 16 is a diagram illustrating a configuration of a soft decision information generation unit according to Embodiment 3 of the present invention.

FIG. 17 is a diagram illustrating a configuration of a digital modulation / demodulation device according to a fourth embodiment of the present invention.

FIG. 18 is a diagram showing a configuration of a conventional digital modulation / demodulation device.

FIG. 19 is a diagram illustrating a configuration of a symbol interleaver in a conventional digital modem.

FIG. 20 is a diagram showing a configuration of a modulation and spreading unit in a conventional digital modulation / demodulation device.

FIG. 21 is a diagram illustrating a configuration of a despreading unit in a conventional digital modulation / demodulation device.

FIG. 22 is a diagram illustrating a configuration of a symbol deinterleaver in a conventional digital modem.

[Explanation of symbols]

 10, 210 Convolutional coding unit 20 Interleaver A 21 Memory of interleaver A 30 Serial / parallel conversion unit 40, 230 Orthogonal code generation unit 50 Code division unit 60 Interleaver B 61 Memory of interleaver B 70 Known sequence addition unit 71 Transmission Frame 80, 240 Modulation and spreading unit 81 Exclusive OR (EXOR) 82 PN sequence generator 83 Data conversion unit 84 Local oscillator 85 Multiplier 86 Bandpass filter (BPF) 90, 250 Transmission antenna 100, 260 Transmission path 110, 270 Receiving antenna 120, 280 Despreading unit 121 Band-pass filter (BPF) 122 Frequency synthesizer 123 Frequency conversion circuit 124 PN sequence generator 125 Multiplier 130 Division code correlation value generation unit 131, 132, 133 Correlator 134 135, 136 Orthogonal code generator 137, 138, 139 Sign inverter 140 Frame detector 141 Code determiner 142 Known sequence detector 150 Deinterleaver B 151 Deinterleaver B memory 160, 160A, 160B Correlation value synthesis and decoding Unit 161A absolute value circuit 162A multiplier 170 parallel / serial conversion unit 180 deinterleaver A 181 memory of deinterleaver A 190, 190A Viterbi decoding unit 200 soft decision information generation unit 201 absolute value circuit 202 parallel / serial converter 203 de Interleaver C 204 Data converter 205 Delayer 206 Multiplier 210 Convolutional encoder 220 Symbol interleaver 290 Receive timing detector 300 Symbol deinterleaver 310 Error correction decoder

Claims (5)

[Claims] 1. A convolutional encoding means for convolutionally encoding input data and generating convolutionally encoded data, a bit interleaving means for interleaving the convolutionally encoded data according to a predetermined rule, Serial / parallel conversion means for serial / parallel conversion of the convolutionally encoded data interleaved by the bit interleave means; orthogonal code generation means for generating an orthogonal code based on the parallel data converted by the serial / parallel conversion means; Code division means for dividing the orthogonal code sequence generated by the orthogonal code generation means into a plurality of pieces; interleave means for interleaving the orthogonal code sequences divided by the code division means as one block for each block; A known sequence adding unit for adding a known sequence to the orthogonal code sequence after code division interleaved by the stage to generate a transmission frame, and a transmission frame generated by the known sequence adding unit, using a predetermined spreading sequence. A modulation and spreading means for transmitting the spread spectrum, and a receiving side, a despreading means for despreading the transmitted spread spectrum output, and an orthogonal code before code division despread by the despreading means. Division code correlation value generation means for calculating a correlation value for a sequence; frame detection means for detecting a known sequence based on the correlation value calculated by the division code correlation value generation means and generating frame timing; Transmission is performed using the correlation value calculated by the correlation value generation means and the frame timing generated by the frame detection means. Deinterleaving means for returning the code-divided orthogonal codes after code division on the side to a time-sequential order; an orthogonal code string returned to the time-sequence order by the deinterleaving means; and a frame generated by the frame detecting means. Based on the timing, a correlation value for an orthogonal code sequence before code division is generated, and a correlation value synthesizing and decoding means for decoding an orthogonal code, and the parallel data decoded by the correlation value synthesizing and decoding means are converted into serial data. Parallel / serial conversion means for converting; bit deinterleaving means for returning the data after convolutional coding in time series based on the serial data converted by the parallel / serial conversion means; convolutional coding by the bit deinterleaving means The series returned in chronological order of later data Digital modulating and demodulating device characterized by having an error correction decoding means for decoding based convolutional codes Rudeta. 2. The code division means divides an orthogonal code by a Walsh function into 2k (k is an integer), and the correlation value synthesizing and decoding means is returned to a time series order by the deinterleaving means. 2. A method for generating a correlation value for an orthogonal code sequence according to a Walsh function before code division based on an orthogonal code sequence and a frame timing generated by the frame detection means, and decoding the orthogonal code. 3. The digital modulation / demodulation device according to claim 1. 3. The known sequence adding unit generates a transmission frame by adding a pseudo noise sequence as a known sequence to the code-separated orthogonal code sequence interleaved by the interleaving unit, and the frame detecting unit includes: 2. The digital modulation / demodulation device according to claim 1, wherein a known sequence of a pseudo-noise sequence is detected based on the correlation value calculated by the division code correlation value generation means, and a frame timing is generated. 4. An orthogonal code before code division based on an orthogonal code sequence returned by the deinterleaving means in a chronological order and a frame timing generated by the frame detecting means. 2. The digital modulation / demodulation device according to claim 1, wherein the correlation values for the series are weighted in proportion to the received signal level, then combined, and the orthogonal code is decoded based on the obtained correlation values. 5. A method for extracting a maximum correlation value among correlation values of an orthogonal code sequence obtained by the correlation value combining and decoding means, and performing the processing after orthogonal code decoding based on an absolute value calculation result of the correlation value. The soft-decision information generating means for generating soft-decision information for Viterbi decoding according to the output of the deinterleaving means, wherein the error-correction decoding means is configured based on the soft-decision information from the soft-decision information generating means. 2. The digital modulation / demodulation apparatus according to claim 1, wherein the serial data returned by the bit deinterleaving means in time series order of the data after the convolutional encoding is used, and decoding of the convolutional code is performed based on the serial data.