JPH11242893A - Non-volatile semiconductor storage device and its data write-in method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device which can reduce write-in time, and the data write-in method for the device. SOLUTION: The device is provided with a latch circuit Q22, Q21 and with the write control circuit 12 which writes by charging the corresponding bit line to the ground voltage, if latch data is the data '00' that makes the threshold voltage of a storage cell a value most separated from the threshold voltage in the initial erase state, and by charging to a voltage VB higher than the ground voltage, if the latch data is the data that makes other threshold voltage. Concretely, in the case of quarternary value, the device is so constituted that the write-in of the data '10', '01' and that of the data '00' are carried out parallelly, and that the electric field is raised relating to the tunnel oxide film of the cell in which the data '00' is written.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-level nonvolatile semiconductor memory device for recording at least three-level data in a memory cell and a method of writing the data.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory device such as a flash memory, a binary memory cell structure in which data having two values "0" and "1" are recorded in one memory cell transistor is usually used. It is. Further, in response to recent demands for increasing the capacity of a semiconductor memory device, data of at least three values or more is recorded in one memory cell transistor.
A so-called multi-level nonvolatile semiconductor memory device has been proposed (for example, "A Multi-Level 32M").
b Flash Memory "'95 ISSCC
p. 132-).

FIG. 8 is a diagram showing the relationship between the threshold voltage Vth level and the data contents when two-bit quaternary data is recorded in one memory transistor in a NAND flash memory. .

In FIG. 8, the vertical axis represents the threshold voltage Vth of the memory transistor, and the horizontal axis represents the distribution frequency of the memory transistor. The contents of 2-bit data constituting data to be recorded in one memory transistor are represented by [IO _{n + 1} , IO _n ] and [I _n
O _n + 1, IO _n] = [1,1], [1,0], [0,
1] and [0, 0]. That is, data “0”, data “1”, data “2”, data “3”
There are four states:

A NAND flash memory in which multi-level data is written in page units (word line units) has been proposed (for example, reference: 1996 IEEE Intern).
ational Solid-State Circuits Conference, ISSCC96 /
SESSION 2 / FLASH MEMORY / PAPER TP 2.1: A 3.3V 128Mb M
ulti-Level NAND Flash Memory For Mass Storage Appl
ication.pp32-33).

FIG. 9 is a circuit diagram showing a main configuration of a NAND flash memory which performs writing in page units disclosed in the above document. In FIG. 9, 1 indicates a memory cell array, 2 indicates a write / read control circuit, and BL2 and BL1 indicate bit lines, respectively.

The memory cell array 1 is composed of memory strings A0 and A1 whose memory cells are connected to common word lines WL0 to WL15. The memory string A0 is connected to the bit line BL1, and the memory string A1 is connected to the bit line BL2. The memory string A0 has a NAND string in which memory cell transistors MT0A to MT15A each composed of a nonvolatile semiconductor memory device having a floating gate are connected in series, and the drain of the memory cell transistor MT0A in this NAND string has a selection gate SG1A.
Is connected to the bit line BL1, and the source of the memory cell transistor MT15A is connected to the reference potential line VGL via the selection gate SG2A. The memory string A1 includes memory cell transistors MT0B to MT0B, each of which is a nonvolatile semiconductor memory device having a floating gate.
MT15B has a NAND string connected in series, and the memory cell transistor MT0B of this NAND string
Of the bit line BL via the select gate SG1B.
2 and the source of the memory cell transistor MT15B is connected to the reference potential line VGL via the selection gate SG2B.

Then, the gates of the selection gates SG1A and SG1B are commonly connected to the selection signal supply line SSL, and the gates of the selection gates SG2A and SG2B are connected to the selection signal supply line G.
It is commonly connected to SL.

The write / read control circuit 2 has an n-channel MO
S (NMOS) transistors NT1 to NT17, p-channel MOS (PMOS) transistor PT1, and latch circuit Q1,
Q2.

The NMOS transistor NT1 has a power supply voltage V
_The gate is connected between the supply line of _CC and the bit line BL1, and the gate is connected to the supply line of the inhibit signal IHB1. The NMOS transistor NT2 is connected between the supply line of the power supply voltage V _CC and the bit line BL2, and has a gate connected to the supply line of the inhibit signal IHB2. NMO
S transistor NT3 and NMOS transistor NT
1 and the memory string A0 and the bit line BL
1 is connected to a depletion-type NMOS transistor NT18. A depletion-type NMOS transistor NT18 is connected between a connection point between the NMOS transistors NT4 and NT2 and a connection point between the memory string A1 and the bit line BL2. NMOS transistor NT
19 are connected. The gates of the NMOS transistors NT18 and NT19 are connected to the decoupling signal supply line DCP.
L.

An NMOS transistor NT is provided between a connection point of the depletion type NMOS transistor NT18 and the NMOS transistor NT1 and the bus line IOi.
3, NT5 and NT16 are connected in series, and NMOS transistors NT4, NT7 and NT17 are connected in series between the connection point of the depletion type NMOS transistors NT19 and NT2 and the bus line IOi + 1. Also, the NMOS transistor N
The connection point between T3 and NT5 and the connection point between the NMOS transistors NT4 and NT7 are grounded via the NMOS transistor NT6, the drain of the PMOS transistor PT1, and the NMOS transistors NT8 and NT13.
Connected to the gate. The gate of the NMOS transistor NT6 is connected to the supply line of the reset signal RST, connected source of the PMOS transistor PT1 is the supply line of the power supply voltage V _CC, is connected to the supply line of the gate signal Vref of the PMOS transistor PT1 I have.

First storage node N1a of latch circuit Q1
Is connected to a connection point between the NMOS transistors NT5 and NT16, and the second storage node N1b is grounded via NMOS transistors NT8 to NT10 connected in series. The first storage node N2a of the latch circuit Q2 is connected to a connection point between the NMOS transistors NT7 and NT17, and the second storage node N2b is connected in series.
It is grounded via MOS transistors NT13 to NT15. Also, the NMOS transistors NT8 and NT9
NMOS transistor NT whose connection point is connected in series
11, grounded via NT12. The gate of the NMOS transistor NT9 is connected to the first storage node N2a of the latch circuit Q2.
0 is connected to the supply line of the signal φLAT2,
The gate of the NMOS transistor NT11 is connected to the second storage node N2b, and the NMOS transistor NT12
Is connected to the supply line of the signal φLAT1,
The gates of the MOS transistors NT14 and NT15 are connected to a supply line for the signal φLAT3. The gate of the NMOS transistor NT16 as a column gate is connected to the supply line of the signal Yi, and the gate of the NMOS transistor NT17 is connected to the supply line of the signal Yi + 1.

FIG. 10A shows a timing chart at the time of reading, and FIG. 10B shows a timing chart at the time of writing (program). FIG.
As can be seen from (b), the quaternary writing is performed in three steps, and the process proceeds to the next step when it is determined that all cells to be written in page units in each step are sufficiently written.

The read operation will be described. First, the reset signal RST and the signals PGM1 and PGM2 are set to a high level. As a result, the first storage nodes N1a and N2a of the latch circuits Q1 and Q2 are pulled to the ground level. As a result, the latch circuits Q1 and Q2 are cleared.
Next, reading is performed with the word line voltage set to 2.4V. If the threshold voltage Vth is higher than the word line voltage (2.4 V), the cell current does not flow, so that the bit line voltage holds the precharge voltage and high is sensed. On the other hand, if the threshold voltage Vth is lower than the word line voltage (2.4 V), the cell current flows to lower the bit line voltage and sense low. Next, the word line voltages 1.
Reading is performed at 2 V, and finally reading is performed at a word line voltage of 0 V.

Specifically, when the cell data is "00",
Since no current flows in all word lines, the bus IOi + 1,
(1, 1) is output to IOi. First, when reading with the word line voltage set to 2.4 V, the signal φLAT1 is set to a high level. At this time, since the cell current does not flow, the bit line is kept at a high level, so that the NMOS transistor NT8 is kept conductive, and the latch circuit Q2
Is kept high, the second storage node N2b of the latch circuit Q2 is kept at a high level.
Transistor NT11 is kept conductive. Therefore, the NMOS transistors NT8, NT11, NT12
Is held in a conductive state, the second storage node N1b of latch circuit Q1 is pulled to the ground level, and latch circuit Q1
Transitions to the high level. Next, when reading is performed by setting the word line voltage to 1.2 V, the signal φLA
Set T3 to high level. At this time, since the cell line does not flow, the bit line is kept at a high level,
MOS transistor NT13 is kept conductive, second storage node N2b of latch circuit Q2 is pulled to the ground level, and first storage node N2a of latch circuit Q2 transitions to the high level. Finally, when reading with the word line voltage set to 0 V, the signal φLAT1 is set to a high level.
At this time, since the cell current does not flow, the bit line is kept at a high level and the NMOS transistor NT8 is kept conductive, but the second storage node N2b of the latch circuit Q2 is at a low level and the NMOS transistor NT8
11 is turned off, and the first storage node N1a of the latch circuit Q1 holds the high level.

When the cell data is "01", a current flows only when the word line voltage is VWL00, and buses IOi + 1,
(0, 1) is output to IOi. First, when reading with the word line voltage set to 2.4 V, the signal φLAT1 is set to a high level. At this time, the bit line goes low due to the flow of the cell current, so that the NMOS transistor NT8 is kept in a non-conductive state, and the first storage node N1a of the latch circuit Q1 holds the low level. Next, when reading is performed with the word line voltage set to 1.2 V, the signal φLAT3
Is set to high level. At this time, since the cell line does not flow, the bit line is kept at a high level.
S transistor NT13 is kept conductive, second storage node N2b of latch circuit Q2 is pulled to the ground level, and first storage node N2a of latch circuit Q2 transitions to the high level. Finally, when reading with the word line voltage set to 0 V, the signal φLAT1 is set to a high level. At this time, since the cell current does not flow, the bit line is kept at a high level and the NMOS transistor NT8 is kept in a conductive state. However, the second storage node N of the latch circuit Q2 is kept
NMOS transistor NT11 because 2b is at low level
Is turned off, and the first storage node N1a of the latch circuit Q1 holds the low level. Cell data is "1"
Similarly, in the case of “0” and “11”, IOi + 1 and I
(0, 1) and (0, 0) are read out to Oi.

Next, the write operation will be described. In the circuit of FIG. 9, first, writing is performed by using data stored in the latch circuit Q1, then writing is performed by using the latch circuit Q2, and finally by using data of the latch circuit Q1. Here, the write data is (Q2, Q
When 1) = (1, 0), the latch circuit Q1 inverts from “0” to “1” when writing is sufficient, but (Q2, Q
If 1) = (0,0), the latch circuit Q1 must be used as write data in the third step, so even if the write is sufficient in the first step, the latch circuit Q1 changes from "0" to "1".
Does not flip (cannot).

In each step, the end of writing is determined when all the latched data (Q2 or Q1) of interest becomes "1". Since the inversion of the latch circuit Q1 in the first step does not occur in the cell where the write data (Q2, Q1) = (0, 0), the end determination by the wired OR is not performed.

[0019]

By the way, in the above-mentioned circuit, as shown in FIG. 11, first, writing of cells whose write data is "10" or "00" according to the data of the latch circuit Q1 (Step 1). Is performed, writing (Step 2) is performed on cells having write data “01” and “00” according to the data of the latch circuit Q2, and finally, the write data is “0”.
The write (Step 3) is performed on the cell of 0. That is, in the above-described conventional circuit, the write of the data "10" and "01" is performed only in Step 1 and Step 2, so that "10", " The write time of “01” corresponds to the write time of Step 1 and Step 2 as it is.
This is performed in all Steps ep1 to Step3, but between Step2 and Step3, I
The writing of Step 3 is performed after the SPP voltage is lowered.

From this, it is estimated that the write time of the cell whose write data is “00” is almost the same as the write time of Step 3. As a result, writing is performed serially, which contributes to an increase in the writing time of four values. Then, as can be seen from FIG.
The sum of the writing time of “0” and “01” and the writing time of data “00” take almost the same time.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of shortening a writing time and a data writing method thereof.

[0022]

In order to achieve the above object, according to the present invention, the amount of charge stored in a charge storage portion changes via a tunnel insulating film in accordance with a voltage applied to a word line and a bit line. A nonvolatile semiconductor memory device in which a threshold voltage changes in accordance with the change and has a memory cell for storing data of a value corresponding to the threshold voltage, and writes multi-bit data to the memory cell in page units. When the write data is data in which the threshold voltage of the memory cell to be written is the value farthest from the threshold voltage in the initial erase state, the electric field applied to the memory cell is higher than other write data. It has means for setting and writing.

According to the present invention, there is provided a verify read circuit for determining whether or not the write operation is sufficient for each write bit during the write operation.

Also, according to the present invention, the amount of charge stored in the charge storage portion changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. A nonvolatile semiconductor memory device having a memory cell for storing data of a value corresponding to a voltage and writing multi-bit data to the memory cell in page units, comprising a latch circuit, wherein the latch data is a threshold of the memory cell. In the case of data which makes the value voltage farthest from the threshold voltage in the initial erase state, the corresponding bit line is charged to the first voltage, and the latch data is the data having another threshold voltage. Has a write control circuit that charges to a second voltage higher than the first voltage to perform writing.

In the present invention, the write control circuit is provided with one bit of the latch circuit corresponding to each bit line.

Further, the present invention has a verify read circuit for determining whether or not the write operation is sufficient for each write bit during the write operation.

In the present invention, the first voltage is a ground voltage, and the second voltage is an intermediate voltage between a power supply voltage and a ground voltage.

Further, the present invention has an input buffer for rearranging multi-bit data input from the outside and transferring the rearranged data to the latch circuit of the write control circuit.

According to the present invention, the amount of charge stored in the charge storage portion changes via the tunnel insulating film according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. A memory cell for storing data of a value corresponding to a threshold voltage, and a method for writing multi-bit data to a memory cell in page units, wherein the write data is a write target. In the case of data in which the threshold voltage of the memory cell is the most distant from the threshold voltage in the initial erase state, writing is performed in parallel by setting the electric field applied to the memory cell higher than other write data. .

Also, according to the present invention, the amount of charge stored in the charge storage portion changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. A data writing method for a non-volatile semiconductor memory device having a memory cell for storing data of a value corresponding to a voltage and writing multi-bit data to the memory cell in page units, wherein the write data is a threshold voltage of the memory cell Is charged to the first voltage in the case of the data which makes the value farthest from the threshold voltage in the initial erase state, and in the case where the write data is the data having another threshold voltage, Writing is performed by charging to a second voltage higher than the first voltage.

According to the present invention, when the write data is data in which the threshold voltage of the memory cell to be written is the value farthest from the threshold voltage in the initial erase state, the electric field applied to the memory cell is changed. Writing is performed in parallel by setting higher than other writing data. Specifically, when the write data is data that sets the threshold voltage of the memory cell to a value farthest from the threshold voltage in the initial erase state, the corresponding bit line is set to the first voltage, for example, the ground voltage. When the data is charged and the write data is data having another threshold voltage, writing is performed by charging to a second voltage higher than the first voltage, for example, an intermediate voltage between a power supply voltage and a ground voltage. As a result, the writing of the slowest cell is faster, and as a result, the overall writing time is shorter.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of the nonvolatile semiconductor memory device according to the present invention. The nonvolatile semiconductor memory device 10 includes a memory array 11, a write / read control circuit 1
2 and a decision circuit 20.

The memory array 11, as shown in FIG.
Each memory cell has a common word line WL0-WL15
Are connected to memory strings A0 and A1. The memory string A0 is connected to the bit line B
L1 and the memory string A1 is connected to the bit line BL.
2 are connected. The memory string A0 is a NAND string in which memory cell transistors MT0A to MT15A each composed of a nonvolatile semiconductor memory device having a floating gate are connected in series.
The drain of the memory cell transistor MT0A of the D string is connected to the bit line BL1 via the selection gate SG1A, and the source of the memory cell transistor MT15A is connected to the reference potential line VGL via the selection gate SG2A. The memory string A1 is composed of a NAND string in which memory cell transistors MT0B to MT15B each composed of a nonvolatile semiconductor memory device having a floating gate are connected in series, and the drain of the memory cell transistor MT0B of this NAND string is connected via a selection gate SG1B. The memory cell transistor MT15B is connected to the bit line BL2, and the source of the memory cell transistor MT15B is connected to the reference potential line VGL via the selection gate SG2B.

The gates of the selection gates SG1A and SG1B are commonly connected to the selection signal supply line SSL, and the gates of the selection gates SG2A and SG2B are connected to the selection signal supply line G.
It is commonly connected to SL.

The write / read control circuit 12 includes NMOS transistors NT21 to NT45 and a PMOS transistor P
T21, PT22, inverter INV21, and latch circuit Q21,
Q22.

The NMOS transistor NT21 is connected between the supply line of the power supply voltage V _CC and the bit line BL1,
The gate electrode is connected to the supply line of the inhibit signal IHB1. The NMOS transistor NT22 is connected to the power supply voltage V _CC
, And the gate electrode is connected to the supply line of the inhibit signal IHB2. A depletion type NMOS transistor NT44 is connected between the source of the NMOS transistor NT21 and a connection point between the memory string A0 and the bit line BL1, and a connection point between the source of the NMOS transistor NT22 and the memory string A1 and the bit line BL2. Is a depletion type NMOS transistor NT
45 are connected. The gates of the NMOS transistors NT44 and NT45 are connected to the decoupling signal supply line D.
Connected to CPL.

NMOS transistors NT44 and NT21
The NMOS transistor NT23 is connected between the node SA21 and the node SA21.
Between the node between the node and NT22 and the node SA21
The transistor NT24 is connected. And NM
The signal Ai is supplied to the gate electrode of the OS transistor NT23, and the signal / Ai (/ indicates inversion) is supplied to the gate electrode of the NMOS transistor NT24.

An NMOS transistor NT26 is connected between the node SA21 and the ground line GND.
A PMOS transistor PT21 is connected between A21 and a supply line of the power supply voltage V _CC . Also, PMOS
The connection point between the drain of the transistor PT21 and the node SA21 is connected to the NMOS transistors NT30 and NT3.
5 gate electrodes. The signal DIS1 is supplied to the gate electrode of the NMOS transistor NT26.
The signal Vre is applied to the gate electrode of the MOS transistor PT21.
f is supplied.

The node SA21 and the latch circuit Q21
NMOS transistors NT25 and NT27 are connected in series between the first storage node N21a and the NMOS transistor NT25 and the NMOS transistor NT2.
PMOS transistor PT22 is connected between the supply line of the seventh connection point and the voltage _{VB (0 <VB <V CC} -Vth). The gate electrode of the NMOS transistor NT27 and the gate electrode of the PMOS transistor PT22 are connected to the first storage node N22a of the latch circuit Q22, and are operatively connected to the ground line GND via the NMOS transistor NT28. And
The signal PG is applied to the gate electrode of the NMOS transistor NT25.
M is supplied, and the signal DIS2 is supplied to the gate electrode of the NMOS transistor NT28.

First storage node N2 of latch circuit Q21
An NMOS transistor NT40 is connected between the first storage node N22a of the latch circuit Q22 and the bus line IOi + 1.
The transistor NT41 is connected. Latch circuit Q
21 and a gate electrode of the NMOS transistor NT36 are connected to the NMOS transistor N21.
It is operatively connected to a ground line via T29. The second storage node N21b of the latch circuit Q21 is N
Connected to the gate electrode of the MOS transistor NT38,
The signal DI is applied to the gate electrode of the NMOS transistor NT29.
S3 is supplied.

Further, NMOS transistors NT30, NT31 and NT32 are connected in series between the second storage node N21b of the latch circuit Q21 and the ground line GND, and are connected between the ground point and the connection point between the NMOS transistors NT30 and NT31. The NMOS transistor NT33,
NT34 is connected in series. The first storage node N22a of the latch circuit Q22 is connected to the gate electrode of the NMOS transistor NT31, and the second storage node N22b is connected to the gate electrode of the NMOS transistor NT33. The signal φLAT3 is supplied to the gate electrode of the NMOS transistor NT32, and the signal φLAT2 is supplied to the gate electrode of the NMOS transistor NT34.

Second storage node N2 of latch circuit Q22
NMOS transistors NT35, NT36, NT37 are connected in series between 2b and ground line GND.
NMOS transistors NT38 and NT39 are provided between the connection point between OS transistors NT35 and NT36 and the ground line.
Are connected in series. Then, the signal φLAT1 is supplied to the gate electrode of the NMOS transistor NT37,
The signal φL is applied to the gate electrode of the NMOS transistor NT39.
AT0 is supplied. In addition, NM as a column gate
The gate of the OS transistor NT40 is connected to the supply line of the signal Yi, and the gate of the NMOS transistor NT41 is connected to the supply line of the signal Yi + 1.

Further, the input terminal of the inverter INV 21 is grounded, and the output terminal is connected to the judgment circuit 20. The NMOS transistors NT42 and NT4 are connected between the output terminal of the inverter INV21 and the ground line.
3 are connected in parallel. The gate electrode of the NMOS transistor NT42 is connected to the second storage node N21b of the first latch circuit Q21, and the gate electrode of the NMOS transistor NT43 is connected to the second latch circuit Q22.
Is connected to the second storage node N22b.

At the time of the write operation, the determination circuit 20 determines whether or not the writing has been completed for all the memory cell transistors based on the potential of the output line of the inverter INV21. Specifically, when the writing is completed, the first storage nodes N21a, N21 of the respective latch circuits Q21, Q22
a attains the power supply voltage V _cc level, and the second storage node N2
1b and 22b become the ground level. As a result, NMOS
Transistors NT42, NT43 becomes potential supply voltage V _CC level of the output lines of being held in the nonconductive state inverter INV21, it determined thereby as the writing is completed. On the other hand, if there is a cell in which writing is not sufficient, one or all of the first storage nodes N21a and 22a of each of the latch circuits Q21 and Q22 are set to the ground level, and the second storage nodes N21b and 22b are connected to the power supply. It goes to the voltage V _CC level. As a result, the NMOS transistor NT42 or NT43 or both transistors are kept conductive, and the potential of the output line of the inverter INV21 becomes the ground level, thereby determining that there is a cell in which writing is insufficient.

Next, write, verify read, and read operations according to the above configuration will be described in order with reference to the drawings.

First, the write operation will be described. In the writing by the present apparatus, after externally input data is rearranged in an input buffer (not shown), the data is stored in each of the latch circuits Q21 and Q22, and writing is performed using the stored data. FIG. 2 shows the relationship between externally input data and data stored in the latch circuit. In this example, it is assumed that the threshold voltage Vth distribution and the write data have a correspondence relationship as shown in FIG. As shown in the figure, in the present embodiment, when the latch data of the latch circuit Q21 is "0" and the latch data of the latch circuit Q22 is "1", data "00" is written, and the latch circuit Q22 latches. When the data is "0", data "10" or "01" is written. When the write data is “00”, writing is performed at the bit line voltage and the channel voltage of 0 V. When the write data is “10” or “01”, the bit line voltage and the channel voltage are changed to a certain voltage “VB”. (For example, 1
V) and writing is performed. Further, when the write data is "11", the bit line voltage becomes Vcc-Vth, and the channel voltage becomes the prohibition voltage due to the self-boost, thereby preventing the writing.

Hereinafter, the write operation will be described in detail with reference to the timing charts of FIG. 2, FIG. 3, and FIG.

At the time of the write operation, first, as shown in FIG. 4D, the signal PGM is set to the high level. As a result, the NMOS transistor NT25 is kept conductive.

Here, the write data is "00", "1".
In the case of "1", the latch data of the latch circuits Q21 and Q22 are, as shown in FIG.
{H, L} and {H, H}. Since the latch data of the latch circuit Q22 is at a high level, the PMOS transistor PT22 is held in a non-conductive state,
Transistor NT27 is kept conductive. NMO
Since the S transistor NT27 is turned on, the output of the latch circuit Q21 (the first storage node N21
a), the NMOS transistors NT27 and NT2
Through 5, the bit line is charged. At this time, when the write data is "00", the output of the latch circuit Q21 is at a low level (0 V), and the bit line is charged to "0 V". When the write data is "11", since the output of the latch circuit Q21 is at a high level, the bit line is charged to a voltage (Vcc-Vth) that has dropped by the threshold voltage Vth of the NMOS transistors NT27 and NT25. You.

On the other hand, if the write data is "01", "1"
In the case of "0", the latch data of the latch circuits Q21 and Q22 are, as shown in FIG.
{L, L} and {L, H}. In this case, since the latch data of the latch circuit Q22 is at a low level,
PMOS transistor PT22 is kept conductive,
NMOS transistor NT27 is kept in a non-conductive state. Since the PMOS transistor PT22 is turned on, 0 <VB <V _CC as shown in FIG.
The bit line is charged to a value between -Vth, for example, the output "VB" of a certain power supply circuit set to 1V.

As shown in FIG. 4A, when the word line voltage WL is set to VWL, the write data becomes "0".
In the case of "0", the voltage between the word line WL and the channel is "V
WL ", the write data is" 01 ",
The voltage between the word line WL and the channel of the cell “10” becomes “VWL-VB”.

Considering the writing time, the threshold voltage Vth of writing becomes exponentially longer as the distance from the ultraviolet irradiation level (UV level) increases. ISPP
In writing, the relationship between the shift amount of the threshold voltage Vth and the writing time is made linear by increasing the word line voltage at the time of writing by ΔVWL for each writing step. However, when writing is started with the same word line voltage and the same channel voltage, writing at a level farthest from the UV level defines the entire writing time. In the present embodiment, the electric field applied to the tunnel oxide film at the time of writing in the cell where the write data (“00”) is farthest from the UV irradiation state is set higher than the other write data “01” and “10”. Therefore, the write time of the write data “00” is shortened, and as a result, the entire write time is shortened.

As described above, the write data is "00".
, The bit line voltage is 0 V and the channel voltage is 0
V; if the write data is "01", the bit line voltage is "VB"; the channel voltage is "VB"; if the write data is "10", the bit line voltage is "VB" and the channel voltage is "VB"; When the write data is "11", the bit line voltage becomes (Vcc-Vth), the channel voltage becomes the inhibit voltage, and all data is written at the same time, and the write data becomes "00". The writing speed of the cell "" is increased.

Next, regarding the verify read operation,
This will be described with reference to the timing charts of FIGS.

In the verify operation, a write check of "00", "01", and "10" is performed each time one write is completed. In the verify operation, the signal Vref is set to a certain voltage and the P
A constant value of charging current (Ir
At the same time as supplying ef) to the bit line, the word line is activated. At this time, the threshold voltage Vt of the memory cell
If h is higher than the word line voltage, no cell current flows, and the bit line voltage is charged at Iref · t / CBL and rises. On the other hand, if the threshold voltage Vth of the memory cell is lower than the word line voltage, the charging current Iref flows through the cell as it is, and the bit line voltage becomes the drain-source voltage VD when the charging current Iref flows through the memory cell.
It does not rise above S (about 0.4 V). After a lapse of a certain time, a determination is made as to whether the level of the node SA21 is high or low.

Specifically, first, when the word line voltage is VVF2
(See FIG. 3), and reading is performed. At this time, the threshold voltage Vth of the memory cell is
When the voltage is higher than VF2, no cell current flows. As a result, the node SA21 rises to a voltage close to the power supply voltage V _CC . On the other hand, when the threshold voltage Vth of the memory cell is lower than the word line voltage VVF2, the voltage becomes as low as the drain-source voltage VDS of the memory cell. Here, when the signal φLAT3 is set to a high level, the NMOS transistor NT32 is maintained in a conductive state. At this time, when the latch data of the latch circuit Q22 is at a high level, that is, when the write data is "00" and the threshold voltage Vth of the memory cell is higher than VVF2, N
Since MOS transistors NT30 and NT31 are kept conductive, second storage node N21b of latch circuit Q21 is pulled to the ground level. As a result, the latch data of the latch circuit Q21 (the first storage node N2
1a) is switched from a low level to a high level. That is, the latch data of the latch circuits Q22 and Q21 becomes {Q22, Q21} = {H, H}.

Thus, at the time of rewriting, the latch data of the latch circuit Q22 is at the high level (the level of the first storage node N22a is at the high level).
S transistor PT22 is held in a non-conductive state, and NM
OS transistor NT27 is kept conductive. Then, charged from the latch data of the latch circuit Q21 as described above (the level of the first storage node N21a) is switched from low level to high level, the bit line voltage (V _CC -Vth), Channel is self-
The boost causes a forbidden voltage and prevents writing.
On the other hand, when the threshold voltage Vth of the memory cell is lower than the word line voltage VVF2, the NMOS transistor NT3
Since 0 is held in the non-conductive state, the latch data of the latch circuit Q21 does not change, and writing is performed at the time of rewriting.

Next, when the word line voltage is VVF1 (see FIG. 3)
And the reading is performed. At this time, if the threshold voltage Vth of the memory cell is higher than the word line voltage VVF1, no cell current flows. Thereby, the node SA
The level of 21 _rises to a voltage close to the power supply voltage V _CC .
On the other hand, when the threshold voltage Vth of the memory cell is lower than the word line voltage VVF1, the voltage becomes as low as about the drain-source voltage VDS (about 0.4 V) of the memory cell.
Here, when the signal φLAT2 is set to a high level,
NMOS transistor NT34 is kept conductive.

At this time, the latch data of the latch circuit Q22 is at the low level, that is, the first storage node N22a is at the low level, the second storage node N22b is at the high level, and the threshold voltage Vth of the memory cell is VVF1. If it is higher, the NMOS transistors NT30 and NT33 are kept conductive, so that the second storage node N21b of the latch circuit Q21 is pulled to the ground level.
As a result, the latch data of the latch circuit Q21 (the level of the first storage node N21a) switches from the low level to the high level (when the write data is "01").
That is, in the latch data of the latch circuits Q22 and Q21, {Q22, Q21} changes from {L, L} to {L, H}.

Immediately after this, the signal φLAT1
Is set to a high level, the first
Of the storage node N21a is inverted from the low level to the high level.
T36 is kept conductive. At this time, since the NMOS transistors NT35 and NT37 are also kept in the conductive state, the second storage node N of the latch circuit Q22 is held.
22b is pulled to the ground level. As a result, the latch data of the latch circuit Q22 (the first storage node N22a
Is switched from a low level to a high level.
At this time, the latch data {Q22, Q21} of the latch circuits Q22, Q21 changes from {L, H} to {H, H}. Latch data of latch circuits Q22 and Q21 $ Q2
2, Q21} becomes {H, H}, so that writing is prevented during rewriting.

On the other hand, when the threshold voltage Vth of the memory cell is lower than the word line voltage VVF1, the potential of the node SA21 is low. Therefore, even if the signal φLAT2 is set to the high level, the signal φLAT1 is set to the high level. Even if this is done, since the NMOS transistors NT30 and NT35 whose gate electrodes are connected to the node SA21 are kept in a non-conductive state, the latch data does not change.

Here, the threshold voltage Vth of the memory cell
Is higher than the word line voltage VVF1, the latch data of the latch circuits Q22 and Q21 after the signal φLAT2 is set to the high level and the reading is performed is expressed by {Q22, Q2
1} = {L, H}. This is the same as the latch data when the write data is "10". Signal φ
At the stage where LAT1 is set to the high level and sensed, the original latch data is {Q22, Q21} = {L, H}
(= Write data is “10”), the original write data is “01”, the immediately preceding signal φLAT2 is set to a high level, verify reading is performed, and the latch data is {Q22, Q21} is {L, It cannot be determined whether the change has occurred from L｝ to {L, H}.

However, if the threshold voltage Vth is equal to or higher than the word line voltage VVF1 in the verification according to the present embodiment, it must be at least equal to or higher than the word line voltage VVF0 during the previous verification. In this case, it is determined that the write operation is sufficient at the time of verifying (described below) with the word line voltage set to VVF0, and the latch data {Q22, Q21} is inverted to {H, H}. Therefore, in this case, the latch circuits Q22 and Q2
1 latch data {Q22, Q21} = {L, H}, this means that the original write data is "01" and the signal φ
It may be considered that LAT2 is set to the high level and the latch data of the latch circuit Q21 is inverted by the verification.

Finally, the word line voltage is set to VVF0 (see FIG. 3) and reading is performed. At this time, if the threshold voltage Vth of the memory cell is higher than the word line voltage VVF0, no cell current flows. As a result, the node SA21 rises to a voltage close to the power supply voltage V _CC . On the other hand, the threshold voltage Vth of the memory cell is
When the voltage is lower than VF0, the voltage is as low as the drain-source voltage VDS of the memory cell. Here, the signal φLA
When T1 is set to the high level, the NMOS transistor NT37 is kept conductive. At this time, when the latch data of the latch circuit Q21 is at a high level, that is, when the write data is "10" and the threshold voltage Vth of the memory cell is higher than VVF0, the NMOS transistors NT35 and NT37 are kept conductive. Therefore, the second storage node N22b of the latch circuit Q22
Is pulled to the ground level. As a result, the latch circuit Q
22 latch data (the level of the first storage node N22a) switches from low level to high level. That is, the latch data of the latch circuits Q22 and Q21 is {Q
22, Q21} = {H, H}. This prevents writing during rewriting.

The write data is "01", that is, the latch data # Q22, Q2 of the latch circuits Q22, Q21.
1} = {L, L}, the first circuit of the latch circuit Q21
Is low, the signal φLAT1 is set to a high level, and even if the NMOS transistor NT37 is held in a conductive state, the NMOS transistor NT36 is held in a non-conductive state. Does not change (does not reverse). On the other hand, when the threshold voltage Vth of the memory cell is lower than the word line voltage VVF0, the NMOS transistor NT35 is kept in a non-conductive state, so that the latch data of the latch circuit Q22 does not change, and the write operation is performed at the time of rewriting. Done.

As described above, all the latch data of the memory cells determined to be "OK" in the verify read are converted to {Q22, Q21} = {H, H}. After the end of the verify read, if all the cells are sufficiently written, the second storage nodes N21b and N22b of the latch circuits Q22 and Q21 are set to the ground level. As a result, the NMOS transistors NT42 and NT4
3 is the potential of the output line of which is held in a non-conductive state inverter INV21 becomes the power supply voltage V _CC level, thereby it is determined that writing has been completed. On the other hand, if there is a cell for which writing is not sufficient, each latch circuit Q2
1, the first memory node N21a of Q22, 22a either, or all set to the ground level, the second memory node N21b, 22b becomes the power supply voltage V _CC level. As a result, the NMOS transistor NT42 or NT4
3, or both transistors are kept conductive, and the potential of the output line of the inverter INV21 becomes the ground level, whereby it is determined that there is a cell in which writing is insufficient.

Next, the read operation will be described with reference to the timing charts of FIGS.

At the time of standby, signals DIS1, DIS
2, DIS3 are set to the power supply voltage V _CC level, the bit line is reset to the ground level, and the latch data of the latch circuits Q22, Q21 is reset to the low level.

First, "00" is read. At this time, the signal Vref is set to “a certain voltage” and PM
The reference current Iref is supplied to the gate electrode of the OS transistor PT21, and the word line voltage is set to VRD2. At this time, the threshold voltage Vth of the memory cell
Is higher than the word line voltage VRD2 (distribution 3), the cell current does not flow, so the bit line voltage increases, and VRD
If it is 2 or less (distribution 2 to 0), the drain-source voltage VDS (about 0.4 V) is maintained.

Here, when signal φLAT2 is set to a high level, NMOS transistor NT34 is kept conductive, and since the latch data of latch circuit Q22 is at a low level, the second storage node N2
2b is at a high level. Therefore, the NMOS transistor NT33 is also kept conductive, and if the threshold voltage of the memory cell is in distribution 3, the NMOS transistor NT30 is also kept conductive. As a result, the second storage node N21b of latch circuit Q21 is pulled to the ground level. As a result, the latch data of the latch circuit Q21 (the level of the first storage node N21a) switches from a low level to a high level. When the threshold voltage of the memory cell has a distribution of 2 to 0, the node SA21 is at a low voltage, so that the NMOS transistor NT30 is kept in a non-conductive state. Therefore, the latch circuit Q21
Latch data (level of the first storage node N21a)
Remains low level. That is, the word line voltage V
The latch data after reading in RD2 is as follows. Distribution 3: {Q22, Q21} = {L, H} Distribution 2-0: {Q22, Q21} = {L, L}

Next, reading is performed with the word line voltage set to VRD1. At this time, the node SA21 has a voltage close to the power supply voltage V _cc because the cell current does not flow through the memory cells having the threshold voltage distributions 3 and 2, and the cell having the distribution 1 and 0 has the node SA flowing through the cell current.
Reference numeral 21 denotes a low voltage of about the drain-source voltage VDS of the memory cell.

Here, the signals φLAT0, φLAT1 are set to the high level, and the NMOS transistors NT39, NT39,
NT37 is kept conductive. At this time, in the memory cells whose threshold voltages are distributions 1 and 0, the latch data of the latch circuits Q21 and Q22 does not change because both the NMOS transistors NT30 and NT35 are kept in a non-conductive state. On the other hand, in the memory cell having the threshold voltage distribution 3, since the latch data of the latch circuit Q21 (the level of the first storage node N21a) is at a high level, the NMOS transistors NT35, NT36, and NT3
7 is kept conductive. As a result, the latch circuit Q2
2, the second storage node N22b is pulled to the ground level, and the latch data of the latch circuit Q22 (the level of the first storage node N22a) switches from the low level to the high level. Since the second storage node N21b of the latch circuit Q21 is at a high level also in the memory cell having the threshold voltage distribution 2, the NMOS transistors NT35 and NT35
38 and NT39 are kept conductive. As a result, the second storage node N22b of the latch circuit Q22 is pulled to the ground level, and the latch data (the level of the first storage node N22a) of the latch circuit Q22 switches from low level to high level. That is, the word line voltage VRD
The latch data after reading at 1 is as follows. Distribution 3: {Q22, Q21} = {H, H} Distribution 2: {Q22, Q21} = {H, L} Distributions 1-0: {Q22, Q21} = {L, L}

Finally, the word line voltage is set to VRD0 and reading is performed. At this time, the cells having the threshold voltage distributions 3 to 1 do not allow the cell current to flow, so that SA2
1 is a voltage close to the power supply voltage V _cc, and the memory cell having distribution 0 has no drain voltage so that the drain-source voltage V
The voltage is about DS.

Here, signal φLAT2 is set to the high level, and NMOS transistor NT34 is kept conductive. At this time, in the memory cells having the threshold voltage distributions 3 to 1, the NMOS transistors NT30 and NT35 are both kept conductive, and the latch circuit Q
In the second storage node N22b, only the distribution 1 is at the high level, so that only the distribution 1 holds the NMOS transistor NT33 in the conductive state. As a result, distribution 1
Only the second storage node N21b of the latch circuit Q21 is pulled to the ground level, and the latch data (the level of the first storage node N21a) of the latch circuit Q21 switches from a low level to a high level. Regarding the distribution 0, since the potential of the node SA21 is about the drain-source voltage VDS, the NMOS transistor NT30 is kept in a non-conductive state, and the latch data of the latch circuit Q21 does not change. That is, the latch data after reading with the word line voltage VRD0 is as follows. Distribution 3: {Q22, Q21} = {H, H} Distribution 2: {Q22, Q21} = {H, L} Distribution 1: {Q22, Q21} = {L, H} Distribution 0: {Q22, Q21} = {L, L} These inverted signals are output to the outside through an IO buffer (not shown).

As described above, according to the first embodiment, the writing of data "10" and "01" and the writing of data "00" proceed in parallel, and the cell to which data "00" is written is written. Since the configuration is such that the electric field applied to the tunnel oxide film is increased, there is an advantage that the writing time can be reduced.

As for the circuit scale, the write time is reduced by half with only a slight increase in the number of transistors as compared with the conventional circuit shown in FIG.

Second Embodiment FIG. 7 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device according to the present invention. In the second embodiment,
The NMOS transistor NT38 of the circuit shown in FIG. 1 is removed, and the drain and source of the NMOS transistor NT39 are connected to the drain and source of the NMOS transistor NT36. Other configurations are the same as those of the circuit of FIG. 1, and the operation is performed in the same manner.

According to the second embodiment, the first
In addition to the effects of the embodiment, there is an advantage that the circuit can be further simplified.

[0079]

As described above, according to the nonvolatile semiconductor memory device of the present invention, there is an advantage that the number of elements can be slightly increased and the writing can be reduced to about half as compared with the conventional circuit. In addition, in all writing steps, it becomes possible to detect insufficiently written cells at high speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing a relationship between externally input data and data stored in a latch circuit.

FIG. 3 is a diagram showing a correspondence relationship between a threshold voltage Vth distribution and write data.

FIG. 4 is a timing chart for explaining a write operation of the circuit of FIG. 1;

FIG. 5 is a timing chart for explaining a verify read operation of the circuit of FIG. 1;

FIG. 6 is a timing chart for explaining a read operation of the circuit of FIG. 1;

FIG. 7 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 8 is a diagram showing a relationship between a threshold voltage Vth level and data contents when data of two bits and having four values is recorded in one memory transistor in a NAND flash memory.

FIG. 9 is a circuit diagram showing a main configuration of a conventional NAND flash memory.

FIG. 10 is a timing chart for explaining the operation of the circuit of FIG. 9;

FIG. 11 is a diagram for explaining a conventional problem.

[Explanation of symbols]

10: nonvolatile semiconductor memory device, 11: memory array,
A0, A1 memory strings, WL0 to WL15 word lines, BL1, BL2 bit lines, 12 write / read control circuits, 20 determination circuits, NT21 to NT45 NM
OS transistor, PT21, PT22 ... PMOS transistor, INV21 ... inverter, Q21, Q22 ...
Latch circuit.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 H01L 29/78 371 29/792

Claims (10)

[Claims] An amount of charge stored in a charge storage portion changes via a tunnel insulating film in accordance with a voltage applied to a word line and a bit line, and a threshold voltage changes in accordance with the change. A nonvolatile semiconductor memory device having a memory cell for storing data of a value corresponding to a threshold voltage and writing multi-bit data to a memory cell in page units, wherein the write data is a threshold of a memory cell to be written. A nonvolatile semiconductor memory device having means for performing writing by setting an electric field applied to the memory cell higher than other write data when the value voltage is data having a value farthest from a threshold voltage in an initial erase state. 2. The non-volatile semiconductor memory device according to claim 1, further comprising a verify read circuit for determining whether or not writing is sufficient for each write bit at the time of said writing operation. 3. The amount of charge stored in the charge storage unit changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. A nonvolatile semiconductor memory device having a memory cell for storing value data and writing multi-bit data to the memory cell in page units, comprising a latch circuit, wherein the latch data initializes a threshold voltage of the memory cell. The corresponding bit line is charged to the first voltage in the case of data having a value farthest from the threshold voltage in the erased state, and the above-described data is stored in the case of latch data having another threshold voltage. A nonvolatile semiconductor memory device having a write control circuit for performing writing by charging to a second voltage higher than the first voltage. 4. The nonvolatile semiconductor memory device according to claim 3, wherein said write control circuit includes one bit of said latch circuit corresponding to each bit line. 5. The non-volatile semiconductor memory device according to claim 3, further comprising a verify read circuit for determining whether or not writing is sufficient for each write bit in said writing operation. 6. The nonvolatile semiconductor memory device according to claim 4, wherein said first voltage is a ground voltage, and said second voltage is an intermediate voltage between a power supply voltage and a ground voltage. 7. The nonvolatile semiconductor memory device according to claim 2, further comprising an input buffer for rearranging externally input multi-bit data and transferring the rearranged data to a latch circuit of said write control circuit. 8. The amount of charge stored in a charge storage portion changes via a tunnel insulating film according to a voltage applied to a word line and a bit line, and a threshold voltage changes according to the change. A data writing method for a non-volatile semiconductor memory device having a memory cell for storing data of a value corresponding to a threshold voltage and writing multi-bit data to a memory cell in page units, wherein the write data is a memory to be written. In the case of data in which the threshold voltage of the cell is the most distant from the threshold voltage in the initial erase state, the electric field applied to the memory cell is set higher than other write data, and non-volatile data is written in parallel. A data writing method for a semiconductor memory device. 9. A charge amount stored in a charge storage portion changes according to a voltage applied to a word line and a bit line, and a threshold voltage changes according to the change. What is claimed is: 1. A data writing method for a nonvolatile semiconductor memory device having a memory cell for storing value data and writing multi-bit data to the memory cell in page units, wherein the write data sets a threshold voltage of the memory cell in an initial erase state. In the case of data having a value farthest from the threshold voltage, the corresponding bit line is charged to the first voltage, and in the case where the write data is data having another threshold voltage, the first bit is charged. A data writing method for a nonvolatile semiconductor memory device in which writing is performed by charging to a second voltage higher than a voltage. 10. The nonvolatile semiconductor memory device according to claim 9, wherein said first voltage is a ground voltage, and said second voltage is an intermediate voltage between a power supply voltage and a ground voltage.