JPH11234356A - Timing generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the stationary phase error of generated timing pulses. SOLUTION: At the time of turning the period when both of a deviation detection window W1 for delaying the phase of symbol timing signals S when the rise of input signals becomes the high level period and the deviation detection window W2 for advancing the phase of the symbol timing signals S when the rise of the input signals becomes the high level period are at a low level to a non-follow-up width A, a phase change amount at the time of delaying or advancing the symbol timing signals S is also turned to Δ.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a timing generation circuit, and more particularly to a timing generation circuit suitable for generating a demodulation timing signal for a digital radio receiver or the like.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a schematic configuration of a radio paging receiver. The radio signal received by the antenna 1 is frequency-converted by the RF unit 2 and
The demodulation unit 3 demodulates the received data by using the symbol timing signal S generated in step (1). The received data is processed by the decoder unit 5 and the CUP 6, converted into a message, output using the speaker 7 or the like, and transmitted to the user.

[0003] The above-mentioned symbol timing signal S is taken out by the phase tracking unit 4 with the output of the RF unit 2 as an input.
This phase follower 4 is constituted by a timing generation circuit to which the present invention is applied. FIG. 3 is a block diagram showing the configuration of the phase follow-up unit 4, and includes a phase detection unit 8, a shift determination unit 9,
It comprises a symbol timing generator 10 and a shift detection window frame generator 11.

FIG. 4 is a time chart for explaining the operation of the conventional circuit of FIG. 3. FIG. 4A shows a case where the generated symbol timing signal S is ahead of the input signal P. (B) shows the operation when the symbol timing signal S is behind the input signal P. First, in FIGS. 4A and 4B, the generated symbol timing signal S is input to the shift detection window generator 11, where two shift detection windows W1 and W2 are generated. As a generation method, the shift detection window W1 falls and the shift detection window W2 rises at the time when the symbol timing signal S falls. Further, each of the shift detection windows W1 and W is set such that a time width (called an unfollowing width) from the fall of the shift detection window W2 to the rise of the shift detection window is 4T.
Generate 2. Here, T is the period of the basic clock CL which is the basis of the operation of the digital configuration receiver.

On the other hand, the phase detecting section 8 detects the rising of the input signal P and inputs it to the shift judging section 9. The shift determination unit 9 also takes in the shift detection windows W1 and W2 generated by the shift detection window generation unit 11, and outputs a symbol timing delay signal if the rising of the detected input signal P is during the high level period of the shift detection window W1. If the rise of the input signal P is in the high-level period of the shift detection window W2, a symbol timing advance signal is sent to the symbol timing generator 10. If the rise of the input signal P is not in any of the high-level periods of the shift detection windows W1, W2, If the signal is in the period of the non-following width, neither the delay signal nor the advance signal is output. The symbol timing generation unit 10 delays the symbol timing signal S output when the symbol timing delay signal is input by 2T (FIG. 4A), and converts the symbol timing signal S output when the symbol timing advance signal is input. Advance by 2T (FIG. 4B). According to the above operation, the output symbol timing signal S is controlled so that the untracked width 4T in which the shift detection windows W1 and W2 both generated at low level include the rising time of the input signal P, A symbol timing signal synchronized with the input signal P can be generated.

[0006]

FIG. 5 is a time chart for explaining a phase error occurring in the above-mentioned conventional circuit. The figure shows a state in which the rising of the input signal P is shifted with respect to the symbol timing. First, the rising time t0 of the input signal P detected by the phase detection unit 8 is determined by two shift detection windows W.
It is assumed that both W1 and W2 are near the center of the unfollowed width at the low level. When the time elapses from this point, the rising point of the input signal P shifts from t1, t2,..., And when reaching the point in time t4 shown in the figure with reference to the symbol timing signal S, the shift detection window W1 becomes high level, Here, the symbol timing is delayed by time 2T. Conversely, this is the same as the rise of the input signal P relatively advanced by 2T.

The above-described phase shift is caused by a relative frequency shift between the basic clocks on the transmission side and the reception side, and the change in the shift is very slow. Occur in the same direction for a long time. Therefore, when the operation as shown in FIG. 5 is repeated, the average value of the tracking phase is shifted from the rising edge of the symbol timing signal by a half of the tracking amount 2T. In other words, it is preferable to control so as to be positioned at the center of the unfollowed width on average, but when the phase of the input signal shifts in the direction in which the input signal advances, that is, the basic clock frequency on the transmitting side is larger than the basic clock frequency on the receiving side Time (FIG. 4B
Has a drawback that the position advanced by T from the preferred position becomes an average value in the opposite case.

It is an object of the present invention to provide a timing circuit in which the above-described steady phase shift does not occur.

[0009]

According to the present invention, there is provided a timing pulse generating means for generating a timing pulse by counting a predetermined number of basic clocks, and wherein the timing pulse falls at the falling point of the timing pulse. Of the first pulse train and the second pulse train rising at the time of the fall of the timing pulse, the pulse widths of the first and second pulse trains are the same, and the high-level periods of the first and second pulse trains are different from each other. A shift window detecting means for generating the input signal so as not to overlap, an input signal phase detecting means for detecting a rising time of the input signal, and a rising time of the input signal detected by the means is a high level of the first pulse train. If the signal is in the level period, a delay signal is output, and the input signal detected by the input signal phase detecting means is output. If the rising point is during the high level period of the second pulse train, the phase shift determining means for outputting an advance signal; and when the delay signal is output from the means, the output pulse phase of the timing pulse generating means is The first and second pulse trains are delayed by a time equal to the unfollowed width in which both of them are at the low level, and when the advance signal is output from the phase shift determining means, the output pulse phase of the timing pulse generating means is unfollowed. There is disclosed a timing generation circuit, comprising: a phase adjusting unit for controlling so as to advance by a time equal to the width.

Further, the present invention discloses a timing generation circuit, wherein the unfollowed width is set to two periods of the basic clock.

[0011]

Embodiments of the present invention will be described below. Although the overall configuration of the timing generation circuit of the present invention is the same as that of FIG. 3, only the configuration of the shift detection window generation unit is different. FIG. 1 shows the operation of the shift detection window generator in the circuit according to the present invention. Assuming that a symbol timing signal is generated at a period of nT (T is a receiving-side basic clock and n is an integer), shift detection is performed. Both windows W1 and W2 are pulses whose high level period (pulse width) is b and the unfollowed width is Δ

## EQU1 ## b = (nT-.DELTA.) / 2. Here, if the unfollowed width Δ is set to 4T, the conventional configuration is obtained.

## EQU2 ## It is assumed that Δ = 2T. Such a circuit configuration is almost the same as the conventional circuit,
It can be realized by only slightly changing the constant of the pulse circuit for generating the shift detection windows W1 and W2.

FIG. 6 shows the phase following operation when the unfollowed width Δ is 2T as described above. In this figure, it is assumed that the rising point t0 of the input signal P detected by the phase detector 8 is substantially at the center of the untracked width 2T, and that the basic clock on the transmitting side has a slightly lower frequency than that on the receiving side. It shows the case where it becomes. At this time, the rising time of the input signal P is relatively delayed, so when the input phase becomes as shown at time t2, the rising time is shifted and the detection window W is shifted.
1 and enters a high-level period, the shift determination unit 9 outputs a symbol timing delay signal. As a result, the symbol timing generation unit 10 delays the phase of the symbol timing by the following amount 2T as in the related art, so that the phase of the input signal P is relatively advanced by 2T in FIG. Since the following amount 2T is equal to the unfollowed width Δ in the present invention, the phase of the input signal P shifts to almost the left end of the unfollowed width, and gradually delays from here. Therefore, the rising point of the input signal P at this time is, on average, almost at the center of the unfollowed width. This operation is the same when the phase of the input signal P is relatively advanced with respect to the symbol timing signal, and the average following position is also substantially the center of the untracked width. In this manner, in the present invention, the phase of the input signal P is controlled so that the phase of the input signal P is approximately at the center position of the unfollowed width in which the two shift detection windows W1 and W2 are both at the low level. Obtainable.

[0013]

According to the present invention, the average error of the generated timing signal can be reduced to almost 0, and therefore, there is an effect that the false detection rate in the demodulation section can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a shift detection window generation method in a timing generation circuit according to the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of a wireless call receiver.

FIG. 3 is a block diagram illustrating a configuration of a conventional phase tracking unit.

FIG. 4 is a time chart for explaining the operation of the conventional circuit of FIG. 3;

FIG. 5 is a time chart for explaining a phase error generated in the conventional circuit of FIG. 3;

FIG. 6 is a time chart for explaining the operation of the timing generation circuit of the present invention.

[Description of Signs] 8 Phase detection unit 9 Shift determination unit 10 Symbol timing generation unit 11 Shift detection window generation unit

Claims (2)

[Claims] 1. A timing pulse generating means for generating a timing pulse by counting a predetermined number of basic clocks, a first pulse train falling at a falling point of the timing pulse, and the timing The second pulse train that rises at the time of the falling of the pulse is defined as the first and second pulse trains having the same pulse width and the first pulse train.
A shift window detecting means for generating the high-level periods of the second pulse train so as not to overlap with each other; an input signal phase detecting means for detecting a rising point of the input signal; When the rise time,
If it is in the high level period of the first pulse train, it outputs a delay signal, and if the rising point of the input signal detected by the input signal phase detecting means is in the high level period of the second pulse train, it outputs an advance signal. Means for determining a phase shift, wherein when the delay signal is output from the means, the output pulse phase of the timing pulse generating means is set to a time equal to the unfollowed width in which the first and second pulse trains are both at a low level. Phase adjusting means for controlling the output pulse phase of the timing pulse generating means to advance by a time equal to the untracked width when the advance signal is output from the phase shift determining means. A timing generation circuit. 2. The method according to claim 1, wherein the unfollowed width is equal to two times the basic clock.
The timing generation circuit according to claim 1, wherein the timing generation circuit has a period.