JPH11233653A - Deletion method for nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce threshold distribution after deletion, without deteriorating a gate insulating film, i.e., while maintaining the data holding characteristics at a high level, in an SAH deletion technique. SOLUTION: Source and drain impurity diffused regions are formed to be at a distance from each other on a semiconductor substrate or the like, and a gate insulating film and a floating gate are laminated on a semiconductor region interposed between both the impurity diffused regions. The withstanding voltage at least on the floating gate side end of the source impurity diffused region is small enough to cause an avalanche breakdown before tunneling occurs at the gate insulating film. This deletion method causes the threshold of a memory transistor to self-focus to a predetermined deleted state by a first-stage deletion, in which hot holes from hot carriers produced by the avalanche breakdown of the source impurity diffused region are charged into the floating gate and by a second-stage weak writing operation in which hot electrons are charged into the floating gate (as CHE or avalanche hot electrons).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of erasing a nonvolatile semiconductor memory device in which a threshold value is changed by injecting hot holes generated by avalanche breakdown into a floating gate in a flash EEPROM or the like. .

[0002]

2. Description of the Related Art At present, there is an increasing demand for an Embedded Flash type device in which a batch erasing type EEPROM (flash memory) is mounted on a microcomputer (microcomputer) or the like, and development is being actively carried out. This is the traditional OTP
(One Time Programmable ROM) In the microcomputer, after the program was developed, the program was embedded in the writing board with the ROM writer (ROM Writer), whereas the Embedded Flame
With sh microcomputers, data can be written and erased electrically after being mounted on the board, and programs can be developed while mounted on the board, so TAT (Turn Around Time) can be reduced in the development of microcomputers with memory. This is because there is an advantage.

As a result, when migrating from development to mass production, the microcomputer is changed from an OTP microcomputer at the time of program development and at the beginning of production to a mask ROM microcomputer at the time of mass production. At times, the form of a mask ROM microcomputer has been adopted. More recently, the cycle of changing the generation of microcomputers has become shorter,
There is no room to shift to a mask ROM version for mass production, and there is an increasing demand from the above-mentioned embodiment to perform all of the program development, initial production and mass production with a Flash microcomputer.

However, since the Flash microcomputer electrically performs writing and erasing, a booster circuit is incorporated, and the chip area is correspondingly large. In addition, since high voltage is used at the time of writing / erasing, it is necessary to form a high-voltage transistor separately from a transistor used in peripheral logic, and the process cost is high. Therefore, the chip cost is higher than that of a normal mask ROM. There is a disadvantage such as high. Therefore, in order to meet the demand for using the above-mentioned Flash microcomputer also in mass production, it is necessary to make the chip cost of the Flash microcomputer as close as possible to the mask ROM.

For the purpose of cost reduction, the voltage required for writing and erasing the memory transistor, which is responsible for data storage in the flash memory section, is all supplied by an external power supply, thereby eliminating the booster circuit.
Memory transistor writing is CHE (Channel Hot E
lectron) injection method, erasing is SAH (Source Avalanche Hot)
Hole) A flash microcomputer using the injection method has been proposed.

FIG. 10 is a conceptual diagram for explaining a writing method by CHE injection in this memory transistor, and FIG. 11 is a conceptual diagram for explaining an erasing method by SAH injection. In FIG. 10 and FIG.
Symbols D and D respectively indicate a source impurity diffusion region and a drain impurity diffusion region formed by introducing, for example, an n-type impurity at a high concentration in a semiconductor region such as a semiconductor substrate or a well (hereinafter simply referred to as a substrate). The symbols FG and CG are
A floating gate and a control gate are shown stacked on a semiconductor region between a source impurity diffusion region S and a drain impurity diffusion region D with an insulating film interposed between the semiconductor region and the gate.

In the writing method by CHE injection, FIG.
As shown in FIG. 0, a voltage of, for example, about 10 V is applied to the control gate CG that also serves as the normal word line, and a voltage of, for example, about 6 V is applied to the drain impurity diffusion region D connected to the normal bit line. And the source impurity diffusion region S at 0 V. As a result, after the channel is formed, hot electrons are generated at the drain end by carriers (electrons) accelerated by an electric field in the channel, and the hot electrons are injected into the floating gate FG over the gate insulating film barrier, thereby forming the memory. Writing is performed by increasing the threshold value of the transistor (generally, the gate threshold voltage Vth). In the erasing method using SAH injection, as shown in FIG. 11, a voltage of, for example, about 2.5 V is applied to the control gate (word line) and a voltage of, for example, about 10 V is applied to the source, and at this time, the drain (bit line) is opened. By holding the substrate at 0 V, avalanche breakdown occurs at the source end, and hot holes generated by the avalanche breakdown are injected into the floating gate FG beyond the gate insulating film barrier, thereby sufficiently increasing the Vth of the memory transistor. Lower to shift to the erased state.

In this method, the above-described injection method at the time of writing / erasing is adopted, and the power supply voltage used for writing and erasing can be as low as about 10 V at the maximum.

FIG. 12 shows a basic configuration example of a peripheral circuit.
FIG. 3 is a circuit diagram showing an inverter using a power supply voltage Vpp of about 10 V, for example. In this inverter, the PMOS side is connected in series with two pMOS transistors Mp1 and Mp2, and the NMOS side is similarly connected to two nMOS transistors Mp1 and Mp2.
As a series connection of n1 and Mn2, these four transistors are connected in series between the power supply voltage Vpp and the ground potential. The input terminal Tin is provided at the gate of the nMOS transistor Mn2 closest to the ground potential. The gates of the other three transistors are commonly connected, and this common connection point is held at a potential such as Vpp / 2 by dividing the resistance. . In such a configuration, for example, Vdd of about 3 to 5 V is applied to the input terminal Tin.
When an input voltage is applied with an amplitude of
pp can be extracted from the output terminal Tout. In addition, a voltage of about Vpp / 2 is applied between the source and the drain of each MOS transistor on average, and the gate and the
Since a voltage of only about Vpp / 2 is applied between the source and the drain at the maximum, a transistor having the same structure as the logic unit and having a normal breakdown voltage can be used.

As exemplified by this inverter configuration, the peripheral circuit of the flash memory unit can be composed of a very simple basic circuit because the power supply voltage is only required to be about 10 V. For this reason, it is not necessary to separately form a high-voltage transistor in the peripheral circuit portion of the memory section. With this type of Flash microcomputer, the memory using the normal-voltage transistor used in the logic section other than the memory section is used. A peripheral circuit (for example, a decoder, a sense amplifier, etc.) of the memory section is configured, and there is an advantage that the processes of the memory peripheral circuit and the logic section can be easily shared for the purpose of reducing the chip cost.

[0011]

However, in the above-described erasing method in which hot holes are injected, holes are trapped in the gate oxide film. Has the disadvantage that the data retention characteristic of the memory transistor deteriorates.

Originally, in this SAH erasing method,
As shown schematically in FIG. 13, in the initial stage, among the hot holes and the hot electrons generated by the avalanche breakdown at the source end, some of the hot holes that escape to the substrate still have a relatively low potential. It is injected into the floating gate FG. As a result, the injection current value | Ifg | is initially large and decreases as the FG potential increases. Also, when the FG potential increases,
Some of the hot electrons that have been attracted to that potential and have escaped to the source until now are injected into the floating gate FG. Since the electron injection works in the direction of lowering the potential, the injection of hot holes and the injection of hot electrons are eventually balanced where Ifg = 0, and at this time, the potential of the floating gate FG is self-converging.

In general, memory cells constituting a memory array always have a bit that can be erased quickly and a bit that has a small amount of data, depending on the variation in materials and processes such as characteristics of the substrate on which the transistor is formed. I do. That is, as shown in FIG. 14, since the speed of the potential convergence of the floating gate FG varies within the memory array, all bits in the memory array or in the erase unit block are converged to a Vth distribution of, for example, about 0.6. It is possible to do this, but that takes a considerable amount of time. The prolonged hot hole injection time in one erase operation may increase the erase cycle. However, the data retention characteristic is further deteriorated due to the trap generation due to the hole injection stress of the gate insulating film described above. With the great disadvantage of doing so.

In the current Flash microcomputer, several bits of defects occur in megabits (Mb) due to deterioration of data retention characteristics, and this is a fatal defect in which the entire chip becomes defective. Therefore, in order to avoid the occurrence of this failure, the Vth distribution at the time of erasing can be converged to about 0.6 V in actuality, but this distribution width is set to 2 in an actual device.
We compromise and use it when it is about V.

However, since the distribution cannot be narrowed due to the restriction on the data holding characteristic, the gate voltage at the time of reading cannot be reduced in a state where the distribution of the gate threshold voltage Vth is large, which is a problem that the operating voltage is low. This is a disadvantageous restriction for increasing the voltage and multi-value. As shown in FIG. 15, when the Vth distribution in the erased state varies, the target Vth of writing is set higher in a relatively large Vth distribution of about 2 V than when the Vth distribution can be narrowed. When the same read gate voltage is applied to read the erased state and the erased state, the read current decreases when reading the cell at one end of the variation, and a general current sense type sense amplifier is used. When such a method is used, there is a problem that high-speed reading cannot be performed. That is, the sense amplifier capacity design and read cycle setting must be performed in consideration of the slow read cell.

The present invention has been made in view of such circumstances, and has been made to reduce the threshold distribution after erasing without deteriorating the gate insulating film in the SAH erasing method, that is, while maintaining the data retention characteristics at a high level. It is an object of the present invention to provide a method of erasing a nonvolatile semiconductor memory device that can be achieved.

[0017]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art and achieve the above object, a method for erasing a nonvolatile semiconductor memory device according to the present invention employs a semiconductor substrate or a semiconductor device supported by the substrate. A source impurity diffusion region and a drain impurity diffusion region are formed apart from each other in the layer,
A gate insulating film, a floating gate, an inter-gate insulating film, and a control gate are sequentially stacked on the semiconductor region interposed between the impurity regions, and the withstand voltage of at least the floating gate side end of the source impurity diffusion region is reduced by the gate insulating film. A method for erasing a non-volatile semiconductor memory device having a memory transistor small enough to cause avalanche breakdown before tunneling occurs in a film, wherein hot holes generated by avalanche breakdown of the source impurity diffusion region are removed. The threshold of the memory transistor is self-converged to a predetermined erased state by a first-stage erasure injecting the floating gate and a second stage of weak writing injecting hot electrons into the floating gate.

The weak writing in the second stage may be either CHE injection or SAH injection. That is, in the case of the former CHE injection, in a channel formed between the source impurity diffusion region and the drain impurity diffusion region, electron hot field acceleration is performed to generate channel hot electrons near the end of the drain impurity diffusion region, The channel hot electrons are injected into the floating gate from the side of the drain impurity diffusion region.
In the case of the latter SAH injection, of the hot carriers generated by avalanche breakdown, hot hot electrons are injected into the floating gate.

A preferred configuration for causing avalanche breakdown is provided at least at the drain-facing end of the source impurity diffusion region and, unlike the source impurity diffusion region, has the same conductivity type as the semiconductor substrate or semiconductor layer. And a low breakdown voltage region having a higher concentration than the semiconductor substrate or the semiconductor layer may be provided, and avalanche breakdown may be generated in the low breakdown voltage region.

According to such an erasing method for a nonvolatile semiconductor memory device, the threshold value is reduced to a low voltage value at once in a short time in a first step, and a weak write adjustment is performed in a second step to obtain a desired erase. The potential of the floating gate from which the threshold value of the state is obtained is self-converged with a relatively small distribution width. In this method, the time required for holes to pass through the gate insulating film can be reduced.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a method for erasing a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing a schematic configuration of a memory transistor in a nonvolatile semiconductor memory device in which the erasing method of the present invention can be suitably performed. In FIG. 1, reference numeral 1 denotes a memory transistor, 2 denotes a semiconductor region (hereinafter simply referred to as a substrate) such as a p-type silicon wafer or a p-type well, and 4 and 6 denote source impurity diffusion regions in which n-type impurities are introduced at a high concentration. And a drain impurity diffusion region, 8 is a gate insulating film made of, for example, thermal silicon oxide, 10 is an inter-gate insulating film made of, for example, an ONO (Oxide-Nitride-Oxide) film, etc., and FG is made conductive by introducing n-type impurities. A floating gate made of doped polysilicon (doped Poly-Si), and CG shows a control gate made of doped Poly-Si or polycide and also serving as a word line. These configurations are the same as those of a general FG type memory transistor.

In the memory transistor 1 of the present embodiment,
As the “low breakdown voltage region” in the present invention, a p ⁻ pocket region is provided at least on the source side. In this example,
In contact with the drain-facing end of the source impurity diffusion region 4, p
^- pocket region 4a is, the drain diffusion region 6
P ^- pocket region 6a is provided in contact with the source-facing end. The concentration of these p-type impurity regions 4a and 6a is set to be higher than the concentration of the substrate 2, and the withstand voltage with the substrate 2 is set to be small at this portion. Therefore, the memory transistor 1 of this example has a configuration in which avalanche breakdown easily occurs in the p ⁻ pocket regions 4 a and 6 a in accordance with the applied voltage between the source impurity diffusion region 4 or the drain impurity diffusion region 6 and the substrate 2. Has become.

First Embodiment In the present embodiment, the first-stage rapid erase is performed by SAH injection, and the second-stage weak writing is performed by CHE injection. 2 and 3 are a conceptual diagram and a characteristic change diagram of the first-stage SAH injection, FIGS. 4 and 6 are a conceptual diagram and a characteristic change diagram of the second-stage CHE injection, and FIG. 5 is an erasing method according to the present embodiment. FIG. 4 is a diagram for explaining a process of self-convergence of a control gate potential due to the following. Hereinafter, the erasing method of this embodiment will be described with reference to a specific example of setting a bias voltage. Note that the bias voltage values shown here are only specific examples, and the present invention is not limited to these.

In this embodiment, the control gate voltage Vg and the substrate voltage Vsub are set to the ground potential (0 V), the drain terminal is opened, and the source voltage Vs is set to, for example, 10 V.
Set to about V. P ^- pocket region 4 shown in FIG.
The concentration of a is set such that avalanche breakdown occurs between the substrate 2 and the source due to the difference between the source voltage Vs and the substrate potential (0 V). Since the substrate 2 and the control gate CG of the carriers generated by the avalanche breakdown are grounded, a part of the hot hole (SAH) escaping to the substrate is first injected into the floating gate FG through the gate insulating film barrier. You.
At this time, since the applied voltage between the source and the gate is relatively high at 10 V, as shown in FIG. 3, the SAH injection is performed more rapidly than in the past, and the desired threshold value at which the slowest bit wants to self-converge (see FIG. 3). When the voltage falls sufficiently below the gate threshold voltage Vtho), the erasing in the first stage ends.

Next, as a second stage, in the present embodiment, C
Weak writing by HE injection is performed. The bias conditions at this time are as shown in FIG. 4, for example, with the drain and the substrate at the ground potential, applying a positive voltage sufficient to generate CHE to the source, for example, about 6 V, To the floating gate FG
Is applied, for example, about 5V. In this example, a positive voltage is applied to the source in order to align the positive voltage application point to the source side in relation to the first stage, but, of course, a positive voltage is applied to the drain side as in the normal case. You may. Under such a bias condition, majority carriers (electrons) are accelerated by an electric field in the formation channel, and Si-SiO ₂ is formed in a pinch-off region at the drain end.
It has energy higher than the potential barrier at the interface, and channel hot electrons (CHE) are generated. This CHE is injected into the floating gate FG in such a manner that the potential of the floating gate FG after the hole injection is somewhat high and is attracted to the positive applied voltage applied to the control gate. Then, the FG potential Vfg decreases (FIG. 5), and the gate threshold voltage Vth increases (FIG. 6).

FIG. 5 summarizes such a two-stage erase operation. In the first stage, SAH is rapidly injected at the initial stage, and avalanche hot electrons (SAE) are generated as the FG potential Vfg increases. The FG potential Vfg works toward self-convergence. However, the first stage ends when the gate threshold voltage Vth falls below a desired value, so that the convergence at that time is not yet achieved. Not very good. In the second stage immediately following, electrons are rapidly injected into the floating gate FG by the above-described CHE injection, and the injection amount is changed to FG
Since the saturation occurs when the potential Vfg decreases, the FG potential at the end of the first stage and the desired Vth determined by the control gate voltage at the second stage and the like increase. The amount of CHE implanted in each cell is determined by the initial value of the FG potential of each cell. In the cell erased quickly in the first stage, more CHE is implanted. CHEs are not implanted into cells that have been erased late. As a result, the gate threshold voltage Vth converges to a desired value Vtho by the weak writing in the second stage. Here, in order to obtain a target gate threshold voltage Vtho, each of the voltages in the first and second stages and the voltage application time are set in advance so as to finally reach the FG potential corresponding thereto.

In the erasing method according to the first embodiment, hot hole injection in the first stage, which leads to deterioration of the gate insulating film, is rapidly performed in a short time, and in the second stage, the gate insulating film is formed by utilizing CHE injection. Narrowing the gate threshold voltage distribution without causing or advancing degradation (eg,
(To a distribution width of about 0.6 V).

Second Embodiment In this embodiment, in the first stage, rapid erasing is performed by SAH injection as in the first embodiment, and weak writing in the second stage is not performed by CHE injection but by avalanche hot electrons (SAE). ). Therefore, FIGS. 2 and 3
Is applied as is even in the first stage of the present embodiment. 7 and 9 are a conceptual diagram and a characteristic change diagram of the second stage SHE injection in the present embodiment, and FIG. 8 is a diagram for explaining a process of self-convergence of the control gate potential by the erasing method of the present embodiment.

In the second stage of this embodiment, weak writing by SAE injection is performed. The bias condition at this time is
The applied voltage between the source, the gate and the substrate is
Relax at the stage. That is, for example, as shown in FIG.
Setting s to, for example, about 10 V is the same as in the first step, but here, the control gate voltage Vg and the substrate voltage Vsub are set to a higher positive voltage than in the first step,
For example, it is set to about 2.5V. The concentration and the like of the p ^- pocket regions 4a and 6a are set so that avalanche breakdown occurs even under this condition. Also in this case, SAH and SAE (Source Avalanche hot Electron) are used.
Occurs. At the start of the second avalanche breakdown, unlike the case of the first stage, sufficient hot holes are injected into the floating gate FG to increase the potential Vfg, and the voltage applied to the control gate CG also decreases. Since it is higher than the above, hot electrons of the hot carriers generated by the avalanche breakdown are injected into the floating gate FG. Thereby, similarly to the CHE of the first embodiment, the FG potential Vf
g decreases (FIG. 8), and the gate threshold voltage Vth increases to a desired value Vtho while improving convergence (FIG. 9). Here, in order to obtain a target gate threshold voltage Vtho, the voltages in the first and second stages and the voltage application time are set in advance so as to finally reach the FG potential corresponding thereto.

In the erasing method according to the second embodiment, the same effect as that of the first embodiment, that is, the first-stage hot hole injection leading to the deterioration of the gate insulating film is rapidly performed in a short time, and the second method is performed. At the stage, the gate threshold voltage distribution can be narrowed (for example, to a distribution width of about 0.6 V) without using or causing deterioration of the gate insulating film by using SAE implantation.

[0031]

According to the method for erasing a nonvolatile semiconductor memory device according to the present invention, erasing can be performed without deteriorating the gate insulating film, that is, while maintaining the data retention characteristics at a high level even in the SAH erasing method. The subsequent threshold distribution can be reduced. Thereby, high-speed reading can be performed at a low voltage. Further, since the amount of holes trapped in the gate insulating film can be reduced, the repetition characteristics of writing and erasing (endurance characteristics) can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a schematic configuration of a memory transistor in a nonvolatile semiconductor memory device according to an embodiment of the present invention, in which an erasing method of the present invention can be suitably performed.

FIG. 2 is a diagram showing a concept of SAH implantation at a first stage in an element cross section in the erasing method according to the first embodiment of the present invention.

FIG. 3 is an erase characteristic diagram showing the erase time dependency of the gate threshold voltage by the first-stage SAH implantation in FIG. 2;

FIG. 4 is a view showing a concept of CHE injection in a second stage in an element cross section in the erasing method according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a process of self-convergence of a control gate potential by the erasing method according to the first embodiment.

FIG. 6 is an erase characteristic diagram showing an erase time dependency of a gate threshold voltage in first and second stages of the first embodiment.

FIG. 7 is a diagram showing a concept of SAE implantation in a second stage in an element cross section in the erasing method according to the second embodiment of the present invention.

FIG. 8 is a diagram illustrating a process of self-convergence of a control gate potential by an erasing method according to a second embodiment.

FIG. 9 is an erasing characteristic diagram showing the erasing time dependency of the gate threshold voltage in the first and second stages of the second embodiment.

FIG. 10 is a diagram showing a concept of a writing method by CHE injection in a cross section of a memory transistor.

FIG. 11 is a diagram showing a concept of an erasing method using a conventional SAH injection in a cross section of an element.

FIG. 12 shows an example of a basic configuration of a memory peripheral circuit that can be applied to a conventional nonvolatile semiconductor memory device of the present invention.
FIG. 3 is a circuit diagram showing an inverter using a power supply voltage Vpp of about 10 V, for example.

FIG. 13 is a diagram schematically showing an erasing process of a conventional SAH erasing method.

FIG. 14 is an erasing characteristic diagram showing an erasing time dependency of a gate threshold voltage in a conventional SAH erasing method.

FIG. 15 is a diagram showing a Vth distribution in an erased state in comparison with an ideal Vth distribution having good convergence in the conventional method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory transistor, 2 ... Semiconductor substrate or well etc. (semiconductor substrate or a semiconductor layer supported by the substrate), 4 ... Source impurity diffusion region, 4a, 6a ... p ^- pocket region (low breakdown voltage region), 8 ... Gate insulation Film, 10 gate insulating film, FG: control gate, CG: control gate.

Claims (6)

[Claims] 1. A semiconductor substrate or a semiconductor layer supported by the substrate, a source impurity diffusion region and a drain impurity diffusion region are formed apart from each other, and a gate insulating layer is formed on the semiconductor region sandwiched between the impurity diffusion regions. A memory in which a film, a floating gate, an inter-gate insulating film, and a control gate are sequentially stacked, and the breakdown voltage of at least the floating gate side end of the source impurity diffusion region is so small that avalanche breakdown occurs before tunneling occurs in the gate insulating film. A method for erasing a nonvolatile semiconductor memory device having a transistor, comprising: a first step of injecting a hot hole into the floating gate among hot carriers generated by avalanche breakdown of the source impurity diffusion region; In the second step of injecting A method of erasing a nonvolatile semiconductor memory device in which a threshold value of the memory transistor is self-converged to a predetermined erased state by writing. 2. The weak writing in the second step, wherein electrons are accelerated by an electric field in a channel formed between the source impurity diffusion region and the drain impurity diffusion region, thereby causing a channel hot near the end of the drain impurity diffusion region. 2. The method according to claim 1, wherein electrons are generated, and the channel hot electrons are injected into the floating gate from a drain impurity diffusion region side. 3. The erasing method according to claim 1, wherein in the weak writing in the second step, hot electrons of hot carriers generated by avalanche breakdown are injected into the floating gate. 4. The semiconductor substrate, wherein the avalanche breakdown is provided at least at a drain-facing end of the source impurity diffusion region and has the same conductivity type as the semiconductor substrate or the semiconductor layer, unlike the source impurity diffusion region. 2. The erasing method for a nonvolatile semiconductor memory device according to claim 1, wherein the generation occurs in a low breakdown voltage region having a higher concentration than the semiconductor layer. 5. In the erasing in the first step, a positive voltage is applied to the source impurity diffusion region while the control gate is grounded and the drain impurity diffusion region is electrically open. 3. The two-stage weak writing, wherein one of the source impurity diffusion region and the drain impurity diffusion region is grounded and a positive voltage is applied to the other impurity diffusion region and the control gate. A method for erasing a nonvolatile semiconductor memory device. 6. In the erasing in the first step, a positive voltage is applied to the source impurity diffusion region with the control gate grounded and the drain impurity diffusion region electrically open, 3. The voltage value of the control gate or the source impurity diffusion region in the two-stage weak writing is changed so that the applied voltage between the source impurity diffusion region and the control gate is smaller than that in the erasing in the first stage. 3. The method for erasing a nonvolatile semiconductor memory device according to item 1.