JPH11229953A - Engine control device - Google Patents

Abstract

(57) [Problem] To provide an engine control device capable of easily rewriting ROM contents without replacing the engine control device main body when a trouble occurs in a market. SOLUTION: An electrically erasable and writable ROM is used for a ROM built in a CPU, and a program and data in the ROM can be rewritten by communication from an external device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an engine control device, and more particularly to an engine control device capable of rewriting ROM data with a built-in CPU mounted on a device after the device is brought into a market.

[0002]

2. Description of the Related Art In recent years, an engine control device for controlling an engine includes a CPU that operates according to a predetermined program, and a ROM that is a nonvolatile memory for storing the program. The ROM stores a program and data for determining a fuel injection amount, an ignition timing, and the like to be supplied to the engine. By the way, CP
As a method of writing a program or data into a ROM built in U, or mounting a CPU on a board and then writing into a built-in ROM, for example, Japanese Patent Laid-Open No. 3-22995
No. 5 is known.

[0003]

However, in the above-mentioned conventional engine control device, although the CPU can be mounted on the board and then written into the built-in ROM, erasing and rewriting of data is not considered. That is, there is a problem that after the engine control device is supplied to the market, the data in the ROM cannot be rewritten even if it is desired to change the data, and the contents of the data cannot be changed unless the CPU itself is replaced. The present invention has been made in view of such a problem, and has as its object to replace the engine control device without replacing the engine control device body when a problem occurs in the market.
An object of the present invention is to provide an engine control device capable of easily rewriting OM contents.

[0004]

In order to achieve the above object, an engine control device according to the present invention basically comprises:
A nonvolatile memory for reading and writing which can erase and write data and erase the data for each predetermined block, and a volatile memory for writing and reading data, In an engine control device provided with an arithmetic unit that operates according to a program written in the non-volatile memory, the arithmetic unit is electrically connected to an external device other than the engine control device, and the nonvolatile memory according to information from the external device. It is characterized in that means for enabling data writing after erasing the contents of the memory block by block are provided.

For an electrically erasable nonvolatile memory, an arithmetic unit having means for performing an erase operation is used, and an erase operation of the contents of the nonvolatile memory is started in accordance with an erase command from an external device. Thereafter, data is written according to a rewrite command from the external device, and data can be rewritten in the nonvolatile memory.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an engine control device according to one embodiment of the present invention. FIG.
In, the engine control device 1 controls the engine 2. Various sensors (not shown) indicating the operating state are attached to the engine 2, and signals from these sensors are input to the engine control device 1. The engine control device 1 includes an input processing circuit 4 that performs waveform processing on a signal from the sensor, a CPU 3 that receives the sensor signal to calculate an optimal operation state of the engine 2, and outputs a result calculated by the CPU 3 to a control signal. And an output circuit 5 for driving an actuator (both not shown) such as a fuel injection device or an ignition device attached to the engine 2.

The CPU 3 has a microprocessor unit (hereinafter referred to as an MPU) 7 which operates according to a control program, a ROM 8 which stores a program for operating the MPU 7, and an RA which stores the operation result of the MPU 7.
M9, an I / O 6 that receives a signal from the input processing circuit 4 and outputs a control signal to an output circuit 5, and a communication circuit 10 for data communication with a memory rewriter 11 as an external device. I have. As the ROM 8, a flash ROM that can erase all data once written and that can be rewritten is used.

Further, the engine control device 1 is electrically connectable to the memory writer 11 and the memory writer 1
The data from 1 is transmitted to the communication circuit 10 in the CPU 3 by the serial communication function. The data of the received command and the like can be erased and rewritten in the ROM 8 under special conditions.

FIG. 2 shows a memory map of the CPU.
FIG. 2A is a memory map of the entire CPU 3 and FIG.
Is the area of ROM 8, 3b is the external memory space, 3c is RA
The area of M9, 3d is an internal register area of MPU7. FIG. 2B shows a block configuration in the ROM 8. The ROM 8 is divided into several blocks.
For example, in the case of FIG. 2B, it is divided into 16 blocks A to P, and the contents in the ROM 8 can be erased for each block. The configuration in the ROM 8 used in the engine control device 1 is roughly divided into a program area in which a control program is stored and a data area in which control data is stored. In this embodiment, blocks A to K are program areas, and blocks LP are data areas. FIG. 3 shows the configuration of a dedicated register for erasing data in the ROM.

In FIG. 3, an erase register is arranged in an internal register area 3d and is composed of 2 bytes. Each bit of the erase registers 1 and 2 corresponds to each of the blocks A to P in the ROM 8, and when this bit is set to 1, for example, the contents of the corresponding block are erased. Therefore, for example, when it is desired to rewrite only the data of the block M which is the data area, first, the bit 4 of the erase register 2
Is set to 1 to erase the data of the block M, and then an operation of writing data to the block M may be performed.

FIG. 4 shows a CP used to rewrite the memory contents in the CPU through communication with a memory rewriter as an external device.
FIG. 9 is a state transition diagram showing an internal state of U. In FIG.
Before the communication with the memory rewriter 11 is started, it is in a state of waiting for communication from the memory rewriter 11 in S1. Here, when a command “INIT” is input from the memory rewriting device 11, a command “<INIT>” is transmitted from the engine control device 1 to the memory rewriting device 11, and “INIT” is transmitted.
T ”command is received and S2
You are now waiting for a configuration command. "INIT" in S1
If any other command is input, an <error> command is transmitted, and the process returns to the original state S1.

Similarly, when a command corresponding to a state is input in each state, the command corresponding to the state is transmitted and the state transits to the next state. In other cases, an <error> command is transmitted, and the process returns to S1, which is the initial state. In this way, after the "INIT" command is input from the initial state S1, the state transits to the setting command waiting state in S2 and waits for the next command. If a "PROG" command for entering the program change mode is received in S2, the process transits to S3; if a "DATA" command for entering the data change mode is received, the process transits to S7; . When a transition is made to S3, a program change mode is entered, and when a transition is made to S7, a data change mode is entered.

Next, when the "GO" command is received in S3, the process proceeds to S4, and when the change data is input, the process proceeds to S5.
Then, the data is changed. When this process is completed, the process returns to S4 after transmitting a <data> command in order to wait for the next data to be input. When a predetermined number of data has been input, the process proceeds from S5 to S6 in a wait state for an end command. In S6, when the "EXIT" command is received, an <EXIT> command is transmitted, and the process returns to S1 to end the program change mode.

On the other hand, when the "DATA" command is received in S2, the mode is changed to the data change mode, and the R to be changed is changed in S7.
“ADDR” data, which is a designation of a block in the OM 8, is received, and the process proceeds to S 8. After receiving the "GO" command which is the process start command in S8, the data change process is performed in S9 and S10. In S9, when the data to be changed is received, the process proceeds to S10, and the change process is executed. After the processing is completed, <data> is transmitted, the process returns to the state of S9, and waits for the next data. Then, when a predetermined number of data is input, the flow shifts to the state of S6, and enters an "EXIT" command waiting state. Hereinafter, similarly to the program change mode, “EX”
When an "IT" command is input, an <EXIT> command is transmitted to return to the state of S1 and end the data change mode.

FIG. 5 is a flowchart showing the operation of the program in the engine control device when the communication of FIG. 4 is performed. In this embodiment, the communication with the memory rewriter uses the serial communication function. FIG. 5 shows the processing of a serial communication function (SCI) interrupt that occurs when data is transmitted from the memory rewriter 11. When an SCI interrupt occurs, first, at S20, the INIT flat
g, PROG flag in S21, DATAf in S22
Check if lag is 1.

If the INIT flag is 0 in S20, it indicates that the communication is in the communication waiting state shown in S1 (FIG. 4). Then, in S28, the data input this time is the "INIT" command. Check whether or not. S2
8 is NO, that is, when it is determined that the command is not the “INIT” command, the process proceeds to S25, an <error> command is output, and each of INIT, PROG, and DATA f
The flag is set to 0 to return to the initial state of communication, and the SCI interrupt processing ends. Then S28
If the result of step (1) is YES, that is, if it is confirmed that the command is an "INIT" command, the flow advances to step S29.
ag is set to 1 and the process is terminated.

On the other hand, if the INIT flag is 1 in S20, it indicates that the state is after S2 in FIG. 4, and it will be confirmed below which state. First, in S21, it is confirmed by the PROG flag that the mode is the program change mode.
If the flag is 1, the process proceeds to S31, and the program is changed. If the result in S21 is NO, the process proceeds to S22, where it is confirmed whether or not the mode is the data change mode. S22
Is YES, that is, if DATAflag is 1 and the mode is the data change mode, the flow advances to S30 to perform data change processing.

If the flag is 0 in S30, the process proceeds to S30 in FIG.
2, the data entered this time is "PRO
"G" or "DATA" command in S23, S
Confirm at 24. First, if the result in S23 is YES, that is, if it is determined that the "PROG" command has been
27, and outputs a <PROG> command.
Set ROGflag to 1 and enter the program change mode.

On the other hand, if the result in S23 is NO, the process proceeds to S24, and if the result in this case is YES, that is, if it is determined that the "DATA" command has been input, the process proceeds to S24.
26, output the <DATA> command and
The flag is set to 1 to enter the data change mode. Also,
If no command is confirmed in both steps S23 and S24, it is determined that a data communication error has occurred, and the process proceeds to S25, where an <error> command is output, and INIT, PROG, and DATA are output.
Are set to 0, and the process returns to the initial state of S1 in FIG.

FIG. 6 is a flowchart for explaining the processing of S31 when the program change mode is entered in the processing of FIG. Since the CPU 3 normally operates with a program stored in the built-in ROM 8, if the contents of the ROM 8 are erased when rewriting the program, the CPU 3 will operate. To prevent this, when changing the program, the program rewriting program must be executed on the RAM 9 instead of operating on the ROM 8. The processing of FIG.
This is performed on AM9. The program for rewriting the program is originally stored in the ROM 8, and is executed after the program is once transferred to the RAM 9.

In FIG. 6, it is checked whether or not the command is a "GO" command in S40. If the command is not a "GO" command (NO), the transmitted command is abnormal,
Proceed to Step 3 and output the <Error> command.
, And each flag of PROG is set to 0 to return to the initial state.
On the other hand, if the result in S40 is YES, that is, if the command is a "GO" command, the flow proceeds to S41, where processing for transferring a program for rewriting the program from the ROM 8 to the RAM 9 is performed.
After the transfer process is completed, the process jumps to the program transferred to the RAM 9 in S42, and executes the program on the RAM 9.

FIG. 7 is a flowchart showing the processing of the program rewriting program transferred to the RAM 9 in the above processing. After jumping to the RAM 9 in S42 of FIG. 6, the process proceeds to S50, and the contents of the blocks A to K, which are the program areas of the ROM 8, are erased. Here, the memory rewriter 11
When data is transmitted by serial communication from the
An interrupt is generated in the CPU 3, but a vector address is required to jump to the processing program at that time. The vector address contains the start address of the interrupt processing program. In the case of the present embodiment, the vector address is located on the block A of the ROM 8, and when executing a program for rewriting the program, it is necessary to set the vector address to jump to the RAM 9. After the rewriting of the program is completed, when an SCI interrupt occurs, the program on the ROM 8 needs to be executed, so that the vector address must be rewritten again. Therefore, in S51, R
In order to execute the program on the AM 9, a process of writing the head address of the program on the RAM 9 to the vector address in the block A on the ROM 8 is performed. By ending this processing, the program can be written.

Thereafter, in step S52, a <GO> command is output, and GO flag is set to 1 to store that the program is being rewritten. Next, in S53, at the time of rewriting the program, the MADR indicating the address where the sequentially transmitted data is to be written is initialized, the processing is temporarily ended, and the data waiting state of S4 in FIG. 4 is entered. When data is transmitted in this state, an SCI interrupt occurs again, and the process proceeds to S54 in FIG.

In S54, it is confirmed whether or not the program is being written by the GO flag. If the result is YES, that is, if it is determined that the program is being written, the process proceeds to S55, where it is checked whether or not the address to be written is the block A. . If the result in S55 is YES, that is, block A
If it is determined that the input data is temporarily stored in the RAM 9
It is stored in the upper area called MPRG (S57).

The MPRG has the same memory size as the block A, and sequentially stores transmitted data in the order of addresses. This is, as described above, a block A
Has an SCI vector address, so
This is a measure to prevent the contents of the vector address from being destroyed if the above is written. on the other hand,
If the result in S55 is NO, that is, if it does not correspond to the block A, the transferred data is written to the address on the ROM 8 in the MADR in S56.

Next, at S58, M indicating the write address
Increment the contents of ADR. Thus, the transmitted data has been written to the predetermined address.
Then, in S59, a <data> command is output to temporarily end the processing until the next data is input. Subsequently, in S60, the value of MADR is equal to or more than a predetermined value, that is,
Check that all data has been written to the program area.
If the result in S60 is NO, that is, if MADR is equal to or less than the predetermined value, it means that the program is still being changed, and the interrupt processing is terminated until the next data is input. However,
If the result in S60 is YES, that is, if it is confirmed that MADR is smaller than the predetermined value, it is determined that all program area changes have been completed, and GO flag is set to 0 to store that the program change processing has been completed.

Thereafter, when an SCI interrupt occurs,
Since GO flag is 0 in S54, whether or not the transmitted data is an “EXIT” command is determined in S6.
Confirm with 2. If the result in S62 is NO, that is, "EXI
If it is not a "T" command, the process is temporarily terminated to wait until the command is input. On the other hand, if the result in S62 is YES, that is, if the "EXIT" command is confirmed, the process proceeds to S63 and thereafter, and the block A is stored in the RAM 9 in the
The following processing to be transferred from the PRG is performed.

First, the contents of block A are erased in S63, and the contents of MPRG are written in block A in S64. Next, when this writing process is completed, an <EXIT> command is output in S65, and INT, P
Each flag of the ROG is set to 0, and the process ends. With the above operation, the program in the ROM 8 can be changed. Next, the data change processing will be described in detail.

FIG. 8 is a flowchart showing a process for changing the control data of the engine. Unlike the above-described program change process, the data change process does not require the change program to operate on the RAM 9. If it is determined in the process of FIG. 5 that the mode is the data change mode and the process proceeds to S30, the process of S70 of FIG. 8 is executed. RO to be changed in S70
It is checked whether the ADDR flag indicating that the data indicating the block on M8 has been input is 1. If the result is NO, that is, if the ADDR flag is 0, since the data input this time is the data representing the block to be changed, the data is stored in M1 on the RAM 9 in S71. Next, it is confirmed in S72 that the block is a rewritable block, that is, that the designated block is a block in the data area and not a block in the program area. If the result in S72 is NO, that is, if it is not the data area, the flow proceeds to S74, in which an <error> command is output and
Each flag of NIT and DATA is set to 0 to return to the initial state.

If the result in S72 is YES, that is, if it is confirmed that the block is a data area, the flow advances to S73, where the DC number storing the number of times the block has been rewritten is stored.
It is confirmed whether the value of CNTi is equal to or more than a predetermined value.
This is performed in the case of a rewritable nonvolatile memory because of its structure, there is a specific limitation on the number of times of writing. Therefore, when writing is performed beyond this limit, there is a possibility that the element will be destroyed. In the embodiment of the present invention, in order to prevent this, the number of times of writing is stored for each block, and when the number of times exceeds the limit, writing is prohibited.

If the result in S73 is YES, that is, if it is determined that the number of times of writing exceeds a predetermined number of times, the process proceeds to S74 as an error. Conversely, if the predetermined number of times of writing has not been reached in S73, the count value of the number of times of writing is incremented in S75, and the process proceeds to S76. In S76, <A
DDR> command and ADDR fl
Set ag to 1 and wait for the next command.

When an SCI interrupt occurs again,
Since ADDR flag = 1 at 0, the process proceeds to S77.
Here, GO flag indicating that data is being changed
Check the status of. If the result in S70 is NO, that is, if the data is not being changed, the process proceeds to S84, where it is confirmed that the data transmitted this time is a "GO" command. If the result in S84 is YES, that is, if the command is a "GO" command, the contents of the block indicated by M1 are erased in S85, and then the MADR indicating the address at the time of writing is initialized in S86. Further, in S87, <G
O> command and output GO flag to 1
To

If GO flag is 1 in S77, that is, it is determined that the data is being changed, the data transmitted thereafter is data for change, and is sequentially written to the designated address. In S78, the transmitted data is written to the address indicated by MADR, and in S79, the address (MADR) is incremented. And S80
Then, a <data> command is output to notify the memory writer 11 that the data writing has been completed.

Next, in S82, it is determined whether or not the value of MADR has reached a predetermined value, that is, whether or not all the data of the designated block has been rewritten. If the result in S82 is YES, that is, if all data has been rewritten, the flow proceeds to S83, where GO flag is set to 0 to indicate the end of the data change processing, and the interrupt processing is ended.

Next, when the data is transmitted, S84
Since the GO flag is 0, the process proceeds to S84. Here, since the “GO” command has already been input, S8
Proceed to 8. Here, the transmitted data is "EXI
Check if it is a "T" command. The result at S88 is Y
ES, that is, “EXIT” command, <EXI
T> command is output (S89). If NO, an <error> command is output (S90), and the process proceeds to S91. In S91, since a series of processes is completed, each fl of INIT, DATA, and ADDR is used to return to the initial state.
ag is cleared and the data change process ends. As described above, the program or data on the ROM can be changed by communication from the external device.

Although the embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various design changes can be made without departing from the present invention described in the appended claims. It is possible to do. For example, the control device disclosed by the present invention is not limited to only engine control, and it goes without saying that a device that performs control using a CPU such as a transmission, a brake, and a suspension has versatility.

In the above-described embodiment, the control data of the engine stored in the nonvolatile memory is erased and written while the engine is stopped. However, this can be performed even while the engine is operating. When erasing and writing control data during engine operation,
The data at the address is temporarily stored in the volatile memory, and when the data is read by the program that controls the engine, the data is first read from the volatile memory, and the data is erased and written from the nonvolatile memory when the data is erased and written. The reading may be switched to the nonvolatile memory.

[0038]

According to the present invention, the contents of the ROM can be easily rewritten without replacing the engine control unit when a trouble occurs in the market.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a memory map showing a configuration of a ROM built in a CPU.

FIG. 3 is a configuration diagram illustrating a configuration of a register that is erased for each block in a ROM.

FIG. 4 is a state transition diagram showing states in a CPU when communication with a memory rewriter is performed.

FIG. 5 is a flowchart showing an operation when shifting to a program change mode or a data change mode.

FIG. 6 shows a program stored in RAM in a program change mode.
9 is a flowchart showing an operation of transferring data upward.

FIG. 7 is a flowchart showing the contents of a program for changing a program operating on the RAM.

FIG. 8 is a flowchart showing the contents of a program when data is changed.

[Explanation of symbols]

1 ... engine control device, 2 ... engine, 3 ...
· CPU, 4 ··· input processing circuit, 5 ··· output circuit,
6 I / O, 7 MPU, 8 Flash ROM, 9 RAM, 10 Communication circuit, 11
..Memory writer, 3a ... ROM area, 3b ...
External memory space, 3c RAM area, 3d Internal register area

Claims (2)

[Claims] 1. A nonvolatile memory capable of writing data and erasing the data for each block, and a volatile memory capable of writing and reading data, and having a built-in nonvolatile memory. In an engine control device including an operation unit that operates according to a program, the operation unit is electrically connected to an external device other than the engine control device, and stores the content of the nonvolatile memory according to information from the external device. An engine control device comprising means for enabling data writing after erasure for each block. Means for enabling data writing after erasing the contents of the nonvolatile memory block by block;
2. The engine control device according to claim 1, wherein erasing and writing of a program for operating the arithmetic device are prohibited.