JPH11220226A - Hybrid module - Google Patents
Hybrid moduleInfo
- Publication number
- JPH11220226A JPH11220226A JP1934298A JP1934298A JPH11220226A JP H11220226 A JPH11220226 A JP H11220226A JP 1934298 A JP1934298 A JP 1934298A JP 1934298 A JP1934298 A JP 1934298A JP H11220226 A JPH11220226 A JP H11220226A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- board
- heat
- hybrid module
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010030 laminating Methods 0.000 claims abstract description 5
- 239000010949 copper Substances 0.000 claims description 7
- 230000020169 heat generation Effects 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 abstract description 8
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 239000011347 resin Substances 0.000 description 17
- 229920005989 resin Polymers 0.000 description 17
- 239000004020 conductor Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 230000005855 radiation Effects 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、回路パターンが形
成された回路基板に、積層コンデンサや積層インダクタ
などのチップ部品や半導体部品を搭載して回路を構成し
たハイブリッドモジュールに関し、特に回路基板上に電
界効果型トランジスタやパワー半導体等の発熱性を有す
る回路部品を搭載したハイブリッドモジュールに関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid module in which chip components such as multilayer capacitors and multilayer inductors and semiconductor components are mounted on a circuit board on which a circuit pattern is formed to form a circuit. The present invention relates to a hybrid module mounted with a heat-generating circuit component such as a field-effect transistor or a power semiconductor.
【0002】[0002]
【従来の技術】従来、回路基板上に電界効果型トランジ
スタやパワー半導体等の発熱性を有する回路部品を搭載
したハイブリッドモジュールでは、回路部品から放熱を
図るため、特殊な放熱手段を設けたものがある。例え
ば、特開平5−13627号公報に示されたハイブリッ
ドモジュールでは、図2に示すように、回路基板21に
放熱フィン22を設け、回路基板21上に搭載された発
熱性を有する回路部品23を、板バネ状の熱伝導部材2
4を介して放熱フィン22と接続したものである。この
ハイブリッドモジュール20では、回路部品23で発生
した熱が、放熱フィン22を介して大気中に放出され
る。2. Description of the Related Art Conventionally, in a hybrid module in which a heat-generating circuit component such as a field-effect transistor or a power semiconductor is mounted on a circuit board, a special heat radiating means is provided in order to radiate heat from the circuit component. is there. For example, in a hybrid module disclosed in Japanese Patent Application Laid-Open No. Hei 5-13627, a heat radiation fin 22 is provided on a circuit board 21 and a heat-generating circuit component 23 mounted on the circuit board 21 is mounted as shown in FIG. , Leaf spring-shaped heat conducting member 2
4 are connected to the heat radiation fins 22. In this hybrid module 20, the heat generated by the circuit components 23 is released to the atmosphere via the heat radiation fins 22.
【0003】また、回路基板上に発熱性を有する回路部
品を搭載したハイブリッドモジュールの他の従来例とし
て、図3に示すようなものもある。このハイブリッドモ
ジュール20’では、回路基板25として窒化アルミニ
ウム系のセラミックが使用され、この回路基板25上の
ランド電極26上にチップ状電子部品27が実装される
と共に、ランド電極26上に半田バンプ28を介して発
熱性を有する半導体素子等の回路部品29が搭載されて
いる。FIG. 3 shows another conventional hybrid module having a circuit board having heat-generating circuit components mounted thereon. In this hybrid module 20 ′, an aluminum nitride ceramic is used as the circuit board 25, the chip-shaped electronic component 27 is mounted on the land electrode 26 on the circuit board 25, and the solder bumps 28 are mounted on the land electrode 26. A circuit component 29 such as a semiconductor element having a heat generating property is mounted via the device.
【0004】また、回路基板25は親回路基板30上に
搭載されると共に、回路基板25の端子電極25aが、
親回路基板30上に形成されたランド電極31に半田で
接続されている。The circuit board 25 is mounted on the parent circuit board 30, and the terminal electrodes 25a of the circuit board 25 are
It is connected to a land electrode 31 formed on the parent circuit board 30 by solder.
【0005】さらに、回路基板25と親回路基板30と
の対向した面は、親回路基板30の上に形成された熱伝
導性の良好な導体膜32を介して接合されている。[0005] Further, the opposing surfaces of the circuit board 25 and the parent circuit board 30 are joined via a conductor film 32 having good thermal conductivity formed on the parent circuit board 30.
【0006】窒化アルミニウム系セラミックは、熱伝導
性が良い絶縁材料として注目されている。前述したハイ
ブリッドモジュールでは、回路基板25上に搭載された
回路部品29から発生する熱が、窒化アルミニウム系セ
ラミックからなる熱伝導性良好な回路基板25と導体膜
32を介して親回路基板30へと伝導され、放熱され
る。[0006] Aluminum nitride-based ceramics have attracted attention as insulating materials having good thermal conductivity. In the above-described hybrid module, heat generated from the circuit components 29 mounted on the circuit board 25 is transferred to the parent circuit board 30 via the circuit board 25 made of aluminum nitride ceramic and having good thermal conductivity and the conductor film 32. Conducted and dissipated.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、前述し
た従来例における前者のハイブリッドモジュール20
は、放熱フィン22を介して回路部品23で発生した熱
を大気中に放出するものであり、放熱効率を高めるため
には、必然的に放熱フィン22の表面積を広げることが
必要となる。このため、ハイブリッドモジュール20に
おいて放熱フィン22の占める容積が大きくなり、小型
化し難くなるという問題点があった。However, the former hybrid module 20 in the above-mentioned conventional example is required.
Is for releasing the heat generated in the circuit component 23 to the atmosphere via the radiating fins 22. In order to enhance the heat radiation efficiency, it is necessary to increase the surface area of the radiating fins 22 inevitably. For this reason, there is a problem that the volume occupied by the radiation fins 22 in the hybrid module 20 is large, and it is difficult to reduce the size.
【0008】また、前述した従来例における後者のハイ
ブリッドモジュール20’では、回路部品29で発生し
た熱が回路基板25を介して親回路基板30へと放熱さ
れるため、放熱フィンは不要であり、回路基板25が放
熱手段を兼ねるため、容積の増大はないが、窒化アルミ
ニウム系セラミックは、熱伝導性が良いものの、現在で
はアルミナ等の一般的な基板材料に比べて極めて高価で
あり、材料のコスト高を招くという問題点があった。Further, in the latter hybrid module 20 'in the above-described conventional example, since the heat generated in the circuit components 29 is radiated to the parent circuit board 30 via the circuit board 25, no radiating fin is required. Since the circuit board 25 also serves as a heat radiating means, there is no increase in volume.Although aluminum nitride-based ceramics have good thermal conductivity, they are extremely expensive at present compared to general board materials such as alumina. There was a problem that the cost was increased.
【0009】本発明の目的は上記の問題点に鑑み、小型
で且つ放熱性の良好なハイブリッドモジュールを提供す
ることにある。An object of the present invention is to provide a compact hybrid module with good heat dissipation in view of the above problems.
【0010】[0010]
【課題を解決するための手段】本発明は上記の目的を達
成するために請求項1では、回路基板と、該回路基板上
に実装された発熱性を有する回路部品とを備え、親回路
基板上に実装して使用されるハイブリッドモジュールに
おいて、前記回路基板は、所定厚さのシートを複数積層
した多層基板からなると共に開口部を有するシートを積
層して前記親回路基板と対向する主面に前記凹部が形成
され、該凹部内に前記回路部品が実装され、前記回路部
品から前記親回路基板に熱伝導されるハイブリッドモジ
ュールを提案する。In order to achieve the above object, according to the present invention, there is provided a circuit board comprising: a circuit board; and a heat-generating circuit component mounted on the circuit board. In the hybrid module mounted and used on the above, the circuit board is formed of a multi-layer board in which a plurality of sheets of a predetermined thickness are stacked, and a sheet having an opening is stacked on a main surface facing the parent circuit board. The present invention proposes a hybrid module in which the concave portion is formed, the circuit component is mounted in the concave portion, and heat conduction is performed from the circuit component to the parent circuit board.
【0011】該ハイブリッドモジュールによれば、回路
基板が多層基板によって構成され、該回路基板には、親
回路基板に実装する際に親回路基板に対向する主面に凹
部が形成され、該凹部内に回路部品が実装される。これ
により、前記回路基板を親回路基板に実装したときに、
前記回路部品は親回路基板に直接或いは放熱部材を介し
て当接され、前記回路部品からの発熱は親回路基板に熱
伝導されて放熱されるので、小型にして高密度実装が可
能となり且つ効率よく放熱を行うことができる。According to the hybrid module, the circuit board is constituted by a multilayer board, and when the circuit board is mounted on the master circuit board, a recess is formed on the main surface facing the master circuit board, and the inside of the recess is formed. The circuit components are mounted on. Thereby, when the circuit board is mounted on the parent circuit board,
The circuit component is in direct contact with the parent circuit board or via a heat radiating member, and the heat generated from the circuit component is conducted to the parent circuit board and radiated. Heat can be dissipated well.
【0012】また、請求項2では、請求項1記載のハイ
ブリッドモジュールにおいて、前記回路基板の密度は、
回路基板全体においてほぼ均一に設定されているハイブ
リッドモジュールを提案する。According to a second aspect, in the hybrid module according to the first aspect, the density of the circuit board is:
We propose a hybrid module that is set almost uniformly over the entire circuit board.
【0013】該ハイブリッドモジュールによれば、前記
回路基板の密度が回路基板全体においてほぼ均一に設定
されているので、周囲温度や湿度の変化による回路基板
の反りの発生が防止される。According to the hybrid module, since the density of the circuit board is set substantially uniformly over the entire circuit board, the occurrence of warpage of the circuit board due to a change in ambient temperature or humidity is prevented.
【0014】また、請求項3では、請求項1又は2記載
のハイブリッドモジュールにおいて、前記回路基板に形
成されている内部電極及び表層電極は、銀又は銅からな
るハイブリッドモジュールを提案する。According to a third aspect of the present invention, there is provided the hybrid module according to the first or second aspect, wherein the internal electrode and the surface electrode formed on the circuit board are made of silver or copper.
【0015】該ハイブリッドモジュールによれば、回路
パターン、スルーホール、ランド電極、端子電極等を構
成する内部電極及び表層電極が銀又は銅からなるので、
放熱性及び高周波特性の優れたものとなる。According to the hybrid module, since the internal electrodes and the surface electrodes constituting the circuit patterns, through holes, land electrodes, terminal electrodes and the like are made of silver or copper,
Excellent heat dissipation and high frequency characteristics are obtained.
【0016】[0016]
【発明の実施の形態】以下、図面に基づいて本発明の一
実施形態を説明する。図1は、本発明の一実施形態のハ
イブリッドモジュールを示す側面断面図である。図にお
いて、10はハイブリッドモジュールで、回路パターン
が形成された回路基板11に複数のチップ状電子部品1
2と発熱性を有する半導体素子等の回路部品13が搭載
されて構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a side sectional view showing a hybrid module according to one embodiment of the present invention. In the figure, reference numeral 10 denotes a hybrid module, and a plurality of chip-shaped electronic components 1 are mounted on a circuit board 11 on which a circuit pattern is formed.
2, and a circuit component 13 such as a semiconductor element having heat generation is mounted.
【0017】回路基板11は、直方体形状のアルミナを
主体としたセラミック多層基板からなり、その底面、即
ち親回路基板30への実装時に親回路基板に対向する主
面11aには、発熱性の回路部品13を搭載するための
凹部14が形成されている。The circuit board 11 is made of a rectangular parallelepiped ceramic multilayer board mainly composed of alumina, and has a bottom surface, that is, a main surface 11a facing the parent circuit board when mounted on the parent circuit board 30, and a heat-generating circuit. A concave portion 14 for mounting the component 13 is formed.
【0018】凹部14は、2段階に形成され、主面11
a側に第1の凹部14Aが形成され、さらに第1の凹部
14A内にやや小さい第2の凹部14Bが形成されてい
る。The recess 14 is formed in two stages,
A first recess 14A is formed on the side a, and a slightly smaller second recess 14B is formed in the first recess 14A.
【0019】第2の凹部14Bは、その中に実装される
回路部品13の形状に合わせて、その縦横厚み寸法より
やや大きく形成される。さらに、この第2の凹部14B
の底面には、前記回路部品13の端子電極を接続するラ
ンド電極15が形成されている。The second concave portion 14B is formed to be slightly larger than the vertical and horizontal thickness dimensions in accordance with the shape of the circuit component 13 mounted therein. Further, the second concave portion 14B
A land electrode 15 for connecting the terminal electrode of the circuit component 13 is formed on the bottom surface of the substrate.
【0020】第2の凹部14Bの中には発熱性を有する
半導体素子,FET等の回路部品13が収納されると共
に、回路部品13の端子電極は凹部14Bの底面に形成
されたランド電極15に接続され、隣り合うランド電極
15間には絶縁性の封止樹脂が充填されている。この状
態で、回路部品13の裏面は、第1の凹部14Aの底面
とほぼ同じ面となる。In the second recess 14B, a circuit component 13 such as a semiconductor element and an FET having heat generation is housed, and the terminal electrode of the circuit component 13 is connected to a land electrode 15 formed on the bottom surface of the recess 14B. The adjacent land electrodes 15 are connected and filled with an insulating sealing resin. In this state, the back surface of the circuit component 13 is substantially the same as the bottom surface of the first recess 14A.
【0021】ここで、回路部品13の端子電極とランド
電極15との接続は、半田付けしても良いし、導電性樹
脂用いた接続、異方導電性樹脂(ACF)用いた接続、
或いはランド電極15上に金(Au)を用いたボールバ
ンプを形成し超音波併用熱圧着する等して行う。Here, the connection between the terminal electrode of the circuit component 13 and the land electrode 15 may be performed by soldering, connection using a conductive resin, connection using an anisotropic conductive resin (ACF),
Alternatively, it is performed by forming a ball bump using gold (Au) on the land electrode 15 and performing thermocompression bonding with ultrasonic wave.
【0022】上記導電性樹脂を用いた接続では、安価で
あり、導電性樹脂によって応力を吸収できるため高信頼
性が得られるという効果があり、さらに、導電性樹脂を
通しての放熱は少ないため目的とする放熱効果に悪影響
を与えることが無い。さらに、異方導電性樹脂を用いれ
ば、ランド電極15間を絶縁する封止樹脂が不要とな
り、コストの低減を図ることができる。The connection using the above-mentioned conductive resin is inexpensive, has the effect of being able to absorb stress by the conductive resin, and has the effect of obtaining high reliability. It does not adversely affect the heat radiation effect. Further, if an anisotropic conductive resin is used, a sealing resin for insulating the land electrodes 15 from each other becomes unnecessary, and cost can be reduced.
【0023】また、上記ランド電極15上にボールバン
プを形成し超音波併用熱圧着する方法によれば、ドライ
プロセスであるためメッキ液による回路部品13へのダ
メージが少なく、設備コストを低減できると共に、回路
基板11への回路部品13の実装作業時間を短縮でき、
実装コストを低減できる。さらに、Au-Au接合なので接
触抵抗が少なく高信頼性を得られる。Further, according to the method of forming a ball bump on the land electrode 15 and thermocompression combined with ultrasonic waves, since the process is a dry process, damage to the circuit component 13 by the plating solution is small, and the equipment cost can be reduced. In addition, the work time for mounting the circuit component 13 on the circuit board 11 can be reduced,
The mounting cost can be reduced. Furthermore, since it is an Au-Au junction, contact resistance is small and high reliability can be obtained.
【0024】また、上記半田を用いた方法では、セルフ
アラインメントにより位置補正されるため、実装精度を
必要としない、また、実装時に低荷重で実装できるため
回路部品13へのダメージが少なく、さらに、半田バン
プにより応力吸収できるため高信頼性を得られる。In the method using solder, the position is corrected by self-alignment, so that mounting accuracy is not required. In addition, since mounting can be performed with a low load at the time of mounting, damage to the circuit component 13 is small, and furthermore, High reliability can be obtained because stress can be absorbed by the solder bumps.
【0025】一方、第1の凹部14A内には、第1の凹
部14Aに嵌合する大きさの放熱板16が装着され、放
熱板16と第1の凹部14Aの底側面及び回路部品13
の裏面との間は熱伝導性樹脂17によって接着され、凹
部14は放熱板16によって封止されている。この状態
で、放熱板16の表面は回路基板11の主面11aとほ
ぼ同じ面となる。On the other hand, a heat sink 16 having a size to be fitted into the first recess 14A is mounted in the first recess 14A, and the heat sink 16 and the bottom side surface of the first recess 14A and the circuit component 13 are provided.
Is bonded by a heat conductive resin 17, and the concave portion 14 is sealed by a heat radiating plate 16. In this state, the surface of the heat sink 16 is substantially the same as the main surface 11a of the circuit board 11.
【0026】また、回路基板11の主面11aと対向す
る面、即ち図示における回路基板11の上面にはランド
電極15が形成され、このランド電極15にチップ状電
子部品12が半田付けされ、これらのチップ状電子部品
12は、回路基板11の上面に嵌合する金属ケース18
によって覆われている。さらに、回路基板11の側面に
は回路パターンに接続された複数の端子電極19が形成
されている。A land electrode 15 is formed on a surface facing the main surface 11a of the circuit board 11, that is, on the upper surface of the circuit board 11 in the drawing, and the chip-shaped electronic component 12 is soldered to the land electrode 15. The chip-shaped electronic component 12 is a metal case 18 fitted on the upper surface of the circuit board 11.
Covered by Further, a plurality of terminal electrodes 19 connected to the circuit pattern are formed on the side surface of the circuit board 11.
【0027】一方、前述したように、回路基板11は多
層構造になっており、その内部に回路パターンが形成さ
れ、各ランド電極15はこの回路パターンに接続されて
いる。これにより、回路基板の体積を有効に利用して、
モジュールの小型化を図っている。On the other hand, as described above, the circuit board 11 has a multilayer structure, in which a circuit pattern is formed, and each land electrode 15 is connected to this circuit pattern. This effectively utilizes the volume of the circuit board,
The module is being miniaturized.
【0028】ここで、回路基板11は、図4に示すよう
に、アルミナを主体としたセラミックグリーンシート
(以下、グリーンシートと称する)101〜107を積
層・圧着した後、焼成することにより形成される。Here, as shown in FIG. 4, the circuit board 11 is formed by laminating and compressing ceramic green sheets (hereinafter referred to as green sheets) 101 to 107 mainly composed of alumina, followed by firing. You.
【0029】それぞれのグリーンシート101〜107
には、図示していないがスルーホールが形成されると共
に銀(Ag)又は銅(Cu)を用いて回路導体パターン
及びランド電極等の内部電極及び表層電極が印刷形成さ
れている。このように電極に銀又は銅を用いることによ
り、放熱性及び高周波特性の向上が図れる。Each of the green sheets 101 to 107
Although not shown, through holes are formed and internal electrodes such as circuit conductor patterns and land electrodes and surface electrodes are printed and formed using silver (Ag) or copper (Cu). By using silver or copper for the electrodes as described above, heat dissipation and high-frequency characteristics can be improved.
【0030】また、最下層のグリーンシート107には
第1の凹部14Aに対応する形状の開口部108aが所
定位置に形成され、さらにグリーンシート107の上に
積層される2つのグリーンシート105,106のそれ
ぞれには第2の凹部14Bに対応する形状の開口部10
5a,106aが所定位置に形成されている。An opening 108a having a shape corresponding to the first concave portion 14A is formed at a predetermined position in the lowermost green sheet 107, and two green sheets 105, 106 laminated on the green sheet 107 are further formed. Have openings 10 each having a shape corresponding to the second recess 14B.
5a and 106a are formed at predetermined positions.
【0031】このように、回路基板11を複数のグリー
ンシート101〜107を積層して形成した多層基板と
し、さらに開口部105a,106a,107aを有す
るグリーンシート105〜107を積層することにより
凹部14を形成すれば、回路基板11の全域に亙って密
度を均一に設定することができる。例えば、開口部を形
成してないグリーンシートを積層して、プレス加工等に
よって凹部14を形成すると、回路基板の内部において
部分的に密度が異なったものとなり、周囲の温度や湿度
変化によって回路基板に反りが生じてしまい、回路パタ
ーンの切断等が生じると共に回路部品13の実装性が極
めて低下してしまう。As described above, the circuit board 11 is a multilayer board formed by laminating a plurality of green sheets 101 to 107, and the green sheets 105 to 107 having openings 105a, 106a, and 107a are further laminated to form the recess 14 Is formed, the density can be set uniformly over the entire area of the circuit board 11. For example, when green sheets having no opening are laminated and the recess 14 is formed by press working or the like, the density of the circuit board is partially different inside the circuit board, and the circuit board is changed due to a change in ambient temperature or humidity. Of the circuit component 13 and the cutability of the circuit pattern occurs, and the mountability of the circuit component 13 is extremely deteriorated.
【0032】前述のように、開口部を有するグリーンシ
ートを積層した多層基板によって回路基板11を構成す
ることにより、凹部14を有する反りの生じない回路基
板11を簡単に製造することができる。As described above, by forming the circuit board 11 from a multilayer board in which green sheets having openings are laminated, the circuit board 11 having the concave portions 14 and having no warp can be easily manufactured.
【0033】また、グリーンシート101〜107を積
層した後に圧着する際には、図5に示すように凹部14
に嵌入する形状のプレス機40を用いる。これにより、
回路基板11の凹部14の内面の表面粗さを10μ以下
程度まで低減でき、凹部14内部へのランド電極15や
バンプの形成を容易に行えるようになる。When pressing the green sheets 101 to 107 after laminating them, as shown in FIG.
Is used. This allows
The surface roughness of the inner surface of the concave portion 14 of the circuit board 11 can be reduced to about 10 μ or less, and the formation of the land electrode 15 and the bump inside the concave portion 14 can be easily performed.
【0034】一方、前述の構成よりなるハイブリッドモ
ジュール10を親回路基板に実装するときは、図6に示
すように、回路基板11の回路部品13が搭載された凹
部14側を下側に向け、主面11aを親回路基板30に
対向させて実装し、回路基板11の側面の端子電極19
を親回路基板30のランド電極31に半田付けする。On the other hand, when the hybrid module 10 having the above-described configuration is mounted on the parent circuit board, as shown in FIG. 6, the concave portion 14 of the circuit board 11 on which the circuit components 13 are mounted faces downward. The main surface 11a is mounted to face the parent circuit board 30, and the terminal electrodes 19 on the side surfaces of the circuit board 11 are mounted.
Is soldered to the land electrode 31 of the parent circuit board 30.
【0035】この親回路基板30の表面において、ハイ
ブリッドモジュール10の放熱板16と対向する位置に
は、ランド電極31と共に、熱伝導性の導体膜32(例
えばグランドパターン等)が予め形成されており、回路
基板11の端子電極19がランド電極31に半田付けさ
れるのと同時に、この導体膜32に放熱板16の表面が
半田付けされる。On the surface of the mother circuit board 30, a heat conductive conductor film 32 (eg, a ground pattern) is formed in advance together with the land electrode 31 at a position facing the heat radiating plate 16 of the hybrid module 10. At the same time that the terminal electrodes 19 of the circuit board 11 are soldered to the land electrodes 31, the surface of the heat sink 16 is soldered to the conductor film 32.
【0036】尚、放熱板16と導体膜32とは半田付け
でなくても、単に当接させるのみ、或いは熱伝導性樹脂
を介して当接させても良いし、導体膜32を介すること
なく放熱板16を直接親回路基板30の表面に当接して
も良い。The heat radiating plate 16 and the conductive film 32 need not be soldered, but may be simply brought into contact with each other, or may be brought into contact with each other via a heat conductive resin. The heat sink 16 may directly contact the surface of the parent circuit board 30.
【0037】このハイブリッドモジュールでは、発熱性
を有する半導体素子等の回路部品13から生じる熱が放
熱板16、熱伝導性樹脂17及び導体膜32を介して親
回路基板30に伝導され或いはグランド等の広い導体膜
に伝導されて放熱される。In this hybrid module, heat generated from the circuit component 13 such as a semiconductor element having heat generation is transmitted to the parent circuit board 30 via the heat radiating plate 16, the heat conductive resin 17 and the conductive film 32, or the ground or the like. Conducted by the wide conductor film and dissipated.
【0038】従って、小型にして効率よく放熱を行うこ
とができるハイブリッドモジュールを安価にて製造する
ことができる。Therefore, it is possible to manufacture a hybrid module which is small in size and can efficiently dissipate heat at a low cost.
【0039】尚、前述した実施形態においては、放熱板
16を介して回路部品13からの発熱を親回路基板30
に熱伝導するようにしたが、図7に示すハイブリッドモ
ジュール50のように放熱板16を設けず、回路部品1
3の裏面を導体膜32に直接当接或いは半田付け等する
ようにしても良い。In the above-described embodiment, the heat generated from the circuit components 13 via the heat radiating plate 16 is not changed.
However, as in the hybrid module 50 shown in FIG.
The back surface of 3 may be directly in contact with the conductor film 32 or may be soldered.
【0040】また、回路部品13としては、GaAsM
ES型FET、GaAsPHEMT型FET、或いはI
nP系FETを用いることが望ましい。The circuit component 13 is made of GaAsM
ES type FET, GaAs PHEMT type FET, or I
It is desirable to use an nP-based FET.
【0041】即ち、回路部品13としてGaAsMES
型FETを用いた場合、素子内部での電子の移動が早い
ため素子からの発熱が少ない、GaAsの線膨張係数が
6ppm/℃とシリコン(Si)よりも大きく、回路基
板11、放熱板16、及び熱伝導性樹脂17等の線膨張
係数と近くなるため、温度変化によって発生する応力が
小さくなり高信頼性を得られる。That is, GaAs MES is used as the circuit component 13.
When the type FET is used, heat generation from the element is small because electrons move quickly inside the element, the linear expansion coefficient of GaAs is 6 ppm / ° C., which is larger than that of silicon (Si), and the circuit board 11, the heat radiating plate 16, In addition, since the coefficient of thermal expansion is close to the linear expansion coefficient of the heat conductive resin 17 and the like, the stress generated by the temperature change is reduced, and high reliability can be obtained.
【0042】また、回路部品13としてGaAsPHE
MT型FETを用いた場合には、素子内部での電子の移
動速度がMES型FETよりも速いため、素子からの発
熱をさらに小さくできると共に、同様に線膨張係数がシ
リコン(Si)よりも大きく、回路基板11、放熱板1
6、及び熱伝導性樹脂17等の線膨張係数と近くなるた
め、温度変化によって発生する応力が小さくなり高信頼
性を得られる。Further, GaAsPHE is used as the circuit component 13.
When the MT-type FET is used, since the electron movement speed inside the element is faster than that of the MES-type FET, heat generation from the element can be further reduced, and the linear expansion coefficient is also larger than that of silicon (Si). , Circuit board 11, heat sink 1
6, and the coefficient of thermal expansion of the thermal conductive resin 17 and the like are close to each other, so that the stress generated by the temperature change is small, and high reliability can be obtained.
【0043】さらに、回路部品13としてInP系FE
Tを用いた場合には、素子内部での電子の移動速度がG
aAsよりも速いため、素子からの発熱をさらに小さく
できると共に、線膨張係数が5ppm/℃とシリコン
(Si)よりも大きく、回路基板11、放熱板16、及
び熱伝導性樹脂17等の線膨張係数と近くなるため、温
度変化によって発生する応力が小さくなり高信頼性を得
られる。Further, as the circuit component 13, an InP-based FE
When T is used, the moving speed of electrons inside the device is G
Since it is faster than aAs, the heat generation from the element can be further reduced, and the linear expansion coefficient is 5 ppm / ° C., which is larger than that of silicon (Si). Since the coefficient is close to the coefficient, the stress generated by the temperature change is reduced, and high reliability can be obtained.
【0044】また、上記回路部品13の端子電極間の絶
縁(パシベーション)にSiN又はSiO2 或いはこれ
らの複合膜を用いることが好ましい。これらを用いるこ
とにより、上記封止樹脂の防湿性が不十分であっても素
子の特性を劣化させることが無く、封止樹脂にボイドが
生じて水分の進入があっても素子の信頼性を劣化させな
い。さらに、上記封止樹脂の残留イオンが多くても素子
の信頼性が劣化しないため、安価な封止樹脂を用いるこ
とができる。Further, it is preferable to use SiN or SiO 2 or a composite film thereof for insulation (passivation) between the terminal electrodes of the circuit component 13. By using these, even if the moisture resistance of the sealing resin is insufficient, the characteristics of the element are not degraded, and the reliability of the element is improved even if a void is generated in the sealing resin and moisture enters. Do not deteriorate. Furthermore, since the reliability of the element is not deteriorated even if the residual ions of the sealing resin are large, an inexpensive sealing resin can be used.
【0045】また、上記実施形態では、発熱性の回路部
品13を1個実装したモジュールを構成したが、複数の
発熱性回路部品を実装したモジュールであっても良く、
この場合のも同様の効果を得ることができる。Further, in the above embodiment, the module in which one heat-generating circuit component 13 is mounted is configured, but a module in which a plurality of heat-generating circuit components are mounted may be used.
In this case, the same effect can be obtained.
【0046】ここで、複数の発熱性FETを用いる場合
には、これら複数のFETを1つのGaAs上に形成し
た回路部品13を用いることが好ましい。これにより、
複数のFETを個別に実装するよりも実装エリアを縮小
できると共に、一度の実装作業で済むため実装コストを
低減することができる。さらに、複数のFETを個別に
実装した場合に比べて、放熱板16或いは親回路基板3
0と容易に接触させることができ、放熱性を安定化させ
ることができる。When a plurality of heat-generating FETs are used, it is preferable to use a circuit component 13 in which the plurality of FETs are formed on one GaAs. This allows
The mounting area can be reduced as compared with the case where a plurality of FETs are individually mounted, and the mounting cost can be reduced since only one mounting operation is required. Furthermore, compared to the case where a plurality of FETs are individually mounted, the heat sink 16 or the parent circuit board 3
0 can be easily contacted, and heat radiation can be stabilized.
【0047】[0047]
【発明の効果】以上説明したように本発明の請求項1記
載のハイブリッドモジュールによれば、回路基板を多層
基板とし、親回路基板に対向する主面に形成された凹部
内に回路部品が実装され、前記回路基板を親回路基板に
実装したときに、前記回路部品は親回路基板に直接或い
は放熱部材を介して当接され、前記回路部品からの発熱
は親回路基板に熱伝導されて放熱されるので、小型にし
て高密度実装が可能となり且つ効率よく放熱を行うこと
ができる。As described above, according to the hybrid module of the first aspect of the present invention, the circuit board is a multilayer board, and the circuit components are mounted in the recesses formed on the main surface facing the parent circuit board. When the circuit board is mounted on the parent circuit board, the circuit component is in direct contact with the parent circuit board or via a heat radiating member, and the heat generated from the circuit component is conducted to the parent circuit board to radiate heat. Therefore, it is possible to reduce the size and achieve high-density mounting, and efficiently radiate heat.
【0048】また、請求項2によれば、上記の効果に加
えて、前記回路基板の密度が回路基板全体においてほぼ
均一に設定されているので、周囲温度や湿度の変化によ
る回路基板の反りの発生が防止されるため、回路基板の
反りによって生じる回路パターンの切断を防止すること
ができると共に、回路基板への回路部品の実装性を向上
できる。According to the second aspect of the present invention, in addition to the above effects, the density of the circuit board is set to be substantially uniform over the entire circuit board, so that the warpage of the circuit board due to a change in ambient temperature or humidity can be prevented. Since the occurrence is prevented, the cutting of the circuit pattern caused by the warpage of the circuit board can be prevented, and the mountability of the circuit component on the circuit board can be improved.
【0049】また、請求項3によれば、上記の効果に加
えて、内部電極及び表層電極が銀又は銅からなるので、
放熱性及び高周波特性の優れたものとなる。According to the third aspect, in addition to the above effects, since the internal electrode and the surface electrode are made of silver or copper,
Excellent heat dissipation and high frequency characteristics are obtained.
【図1】本発明の一実施形態のハイブリッドモジュール
を示す側面断面図FIG. 1 is a side sectional view showing a hybrid module according to an embodiment of the present invention.
【図2】従来例のハイブリッドモジュールを示す側面断
面図FIG. 2 is a side sectional view showing a conventional hybrid module.
【図3】従来例の他のハイブリッドモジュールを示す側
面断面図FIG. 3 is a side sectional view showing another conventional hybrid module.
【図4】本発明の一実施形態における回路基板の構成を
説明する図FIG. 4 is a diagram illustrating a configuration of a circuit board according to an embodiment of the present invention.
【図5】本発明の一実施形態における積層シートの圧着
方法を説明する図FIG. 5 is a view for explaining a method for crimping a laminated sheet according to an embodiment of the present invention.
【図6】本発明の一実施形態のハイブリッドモジュール
の親回路基板搭載例を示す図FIG. 6 is a diagram showing an example of mounting a parent circuit board on a hybrid module according to an embodiment of the present invention.
【図7】本発明のハイブリッドモジュールの他の実施形
態を示す側面断面図FIG. 7 is a side sectional view showing another embodiment of the hybrid module of the present invention.
10,50…ハイブリッドモジュール、11…回路基
板、11a…主面、12…チップ状電子部品、13…発
熱性の回路部品、14…凹部、14A…第1の凹部、1
4B…第2の凹部、15…ランド電極、16…放熱板、
17…熱伝導性樹脂、18…金属ケース、19…端子電
極、30…親回路基板、31…ランド電極、32…熱伝
導性の導体膜、40…プレス機、101〜107…セラ
ミックグリーンシート、105a,106a,107a
…開口部。10, 50: hybrid module, 11: circuit board, 11a: main surface, 12: chip-like electronic component, 13: heat-generating circuit component, 14: concave portion, 14A: first concave portion, 1
4B: second concave portion, 15: land electrode, 16: heat sink,
17: heat conductive resin, 18: metal case, 19: terminal electrode, 30: parent circuit board, 31: land electrode, 32: heat conductive conductor film, 40: press machine, 101 to 107: ceramic green sheet, 105a, 106a, 107a
…Aperture.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 八木 一樹 東京都台東区上野6丁目16番20号 太陽誘 電株式会社内 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kazuki Yagi Taiyo Electric Co., Ltd. 6-16-20 Ueno, Taito-ku, Tokyo
Claims (3)
発熱性を有する回路部品とを備え、親回路基板上に実装
して使用されるハイブリッドモジュールにおいて、 前記回路基板は、所定厚さのシートを複数積層した多層
基板からなると共に開口部を有するシートを積層して前
記親回路基板と対向する主面に前記凹部が形成され、 該凹部内に前記回路部品が実装され、前記回路部品から
前記親回路基板に熱伝導されることを特徴とするハイブ
リッドモジュール。1. A hybrid module comprising: a circuit board; and a circuit component having heat generation mounted on the circuit board and used by being mounted on a parent circuit board. The concave portion is formed on a main surface facing the parent circuit board by laminating sheets having openings, and the circuit component is mounted in the concave portion. Characterized in that the module is thermally conducted to the parent circuit board from the substrate.
おいてほぼ均一に設定されていることを特徴とする請求
項1記載のハイブリッドモジュール。2. The hybrid module according to claim 1, wherein the density of the circuit board is set substantially uniformly over the entire circuit board.
及び表層電極は、銀又は銅からなることを特徴とする請
求項1又は2記載のハイブリッドモジュール。3. The hybrid module according to claim 1, wherein the internal electrode and the surface electrode formed on the circuit board are made of silver or copper.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1934298A JPH11220226A (en) | 1998-01-30 | 1998-01-30 | Hybrid module |
KR1019990002702A KR100563122B1 (en) | 1998-01-30 | 1999-01-28 | Hybrid module, manufacturing method thereof and installation method |
CNB991018370A CN1319422C (en) | 1998-01-30 | 1999-01-29 | Hybrid module and making method thereof and mounting method thereof |
DE69935628T DE69935628T2 (en) | 1998-01-30 | 1999-01-29 | hybrid module |
US09/239,669 US6163456A (en) | 1998-01-30 | 1999-01-29 | Hybrid module and methods for manufacturing and mounting thereof |
EP99101533A EP0933816B1 (en) | 1998-01-30 | 1999-01-29 | Hybrid module |
HK00100488.9A HK1021608B (en) | 1998-01-30 | 2000-01-26 | Hybrid module and methods for manufacturing and mounting thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1934298A JPH11220226A (en) | 1998-01-30 | 1998-01-30 | Hybrid module |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11220226A true JPH11220226A (en) | 1999-08-10 |
Family
ID=11996738
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1934298A Pending JPH11220226A (en) | 1998-01-30 | 1998-01-30 | Hybrid module |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11220226A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003060523A (en) * | 2001-08-09 | 2003-02-28 | Tdk Corp | Radio communication module |
US7190982B2 (en) | 2003-01-28 | 2007-03-13 | Matsushita Electric Industrial Co., Ltd. | Radio frequency device |
JP2013110303A (en) * | 2011-11-22 | 2013-06-06 | Ngk Insulators Ltd | Circuit board for peripheral circuit of large capacity module, large capacity module including peripheral circuit using circuit board, and manufacturing method of large capacity module |
WO2017086095A1 (en) * | 2015-11-17 | 2017-05-26 | 株式会社村田製作所 | Multilayer substrate and electronic apparatus |
-
1998
- 1998-01-30 JP JP1934298A patent/JPH11220226A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003060523A (en) * | 2001-08-09 | 2003-02-28 | Tdk Corp | Radio communication module |
US7190982B2 (en) | 2003-01-28 | 2007-03-13 | Matsushita Electric Industrial Co., Ltd. | Radio frequency device |
JP2013110303A (en) * | 2011-11-22 | 2013-06-06 | Ngk Insulators Ltd | Circuit board for peripheral circuit of large capacity module, large capacity module including peripheral circuit using circuit board, and manufacturing method of large capacity module |
WO2017086095A1 (en) * | 2015-11-17 | 2017-05-26 | 株式会社村田製作所 | Multilayer substrate and electronic apparatus |
JPWO2017086095A1 (en) * | 2015-11-17 | 2018-07-05 | 株式会社村田製作所 | Multilayer substrate and electronic device |
US10354939B2 (en) | 2015-11-17 | 2019-07-16 | Murata Manufacturing Co., Ltd. | Multilayer board and electronic device |
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