JPH11215132A - Device and method for processing information and distribution medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of synchronous communication disabled conditions between IEEE-1394 buses when the buses are connected to each other through a bridge. SOLUTION: When supplying a synchronizing signal to a node 4 from a node 3 through an IEEE-1394 bus 1 and transferring the synchronizing signal to another IEEE-1394 bus 2 from the node 4 through a node 5, the node 5 must be a cycle master which can output the synchronizing signal to the bus 2 to which the node 5 belongs. When the bus 2 is reset, a set packet is inserted into the bus 2 so that the node 5 itself may be the cycle master of the bus 2, because it is not guaranteed that the node 5 again becomes the cycle master.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, an information processing method, and a providing medium.
Synchronous communication (Isochronous Tran
The present invention relates to an information processing apparatus and method, and a providing medium, in which a synchronous signal can be transferred to another bus when performing a saction, so that synchronous communication can be performed between a plurality of buses.

[0002]

2. Description of the Related Art At present, P1394.1 (bridge) working group
In the IEEE1394 environment, standardization of bridge format within the IEEE1394 environment is being carried out (in this regard, P1394.1 Draft
0.03 Oct 18, 1997). IEEE1394 bridge (hereinafter,
A portal (port simply referred to as a bridge) is connected to an IEEE1394 bus (hereinafter, abbreviated as a bus as appropriate).
al), and can transmit data between a plurality of (two or more) buses via this bridge.

[0003] Data transmission on a bridge (between portals) can be performed using, for example, a cable, radio waves, or infrared rays.

[0004]

By the way, in the IEEE1394 bus, synchronous communication is performed in units of 125 μsec. However, the synchronization signal of each bus used in the synchronous communication is:
Basically, it differs for each bus. Therefore, in order to perform synchronous communication on a plurality of IEEE1394 buses, a bridge connecting the plurality of buses needs to transfer a synchronization signal from one bus to the other bus. For each bus, a cycle master is defined as the only node in the bus that can emit a synchronization signal. In other words, since only the cycle master can transmit a synchronization signal into the bus, a bridge must be configured to enable the synchronization signal from one bus to be transferred to the other bus. It is necessary that at least one of the portals connected to the other bus be the cycle master of the other bus.

However, among a plurality of nodes connected to each bus, if there are a plurality of nodes which can be cycle masters, the IEEE 1394 determines at the time of the reset processing that the one which has completed the reset processing last is the root. It is defined that the route becomes a cycle master. As a result, even when the portal is configured as a node that can be the cycle master, the portal may not always be the cycle master. as a result,
In some cases, the synchronization signal cannot be transferred from one bus to the other bus (synchronous communication cannot be performed).

[0006] The present invention has been made in view of such a situation, and it is possible to reliably transfer a synchronization signal from one bus to another bus, that is, to enable synchronous communication. Things.

[0007]

An information processing apparatus according to claim 1 performs first processing for making itself a route on the bus to which the information processing apparatus belongs, and resets the bus to which the information processing apparatus belongs. And a second means for performing processing for performing the processing.

According to a third aspect of the present invention, there is provided an information processing method comprising: a first step of performing processing for setting an information processing apparatus to a route on a bus to which the information processing apparatus belongs; And a second step of performing the following.

According to a fourth aspect of the present invention, there is provided a computer program for use in an information processing apparatus for transmitting and receiving data by synchronous communication between another bus and a bus to which the own bus belongs. A first step of performing a process for setting a route on a bus to which the information processing apparatus belongs, and a second step of performing a process for resetting a bus to which the information processing device belongs.
And a computer program comprising the steps of:

[0010] The information processing apparatus according to claim 1, claim 3,
In the information processing method described in the above, and in the providing medium described in the claim 4, while the information processing apparatus that transmits and receives data by synchronous communication between buses, a process for becoming a route on the bus to which the information processing apparatus belongs is performed, Processing for resetting the bus to which the bus belongs is performed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. In order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, each means is described. When the features of the present invention are described by adding the corresponding embodiment (however, an example) in parentheses after the parentheses, the result is as follows. However, of course, this description does not mean that each means is limited to those described.

The information processing apparatus according to the first aspect performs first processing (for example, step S12 in FIG. 3) for making itself a route on a bus to which the information processing apparatus belongs.
And a second means (for example, step S12 in FIG. 3) for performing processing for resetting the bus to which the self belongs.

FIG. 1 shows an information processing system to which an information processing apparatus according to the present invention (hereinafter, the information processing apparatus is also referred to as a node). FIG. 3 is a block diagram showing an example of a configuration of the present invention. In this example, IE
Node 3 and node 4 (portalL) are connected to the EE1394 bus 1, while node 5 and node 4 are connected to the IEEE1394 bus 2.
(PortalR) and the node 6 are connected. A bridge 7 is formed by the nodes 4 and 5 as portals of the respective buses. In this case, two devices (node 3 and node 4) are connected to the IEEE1394 bus 1, and two devices (node 5 and node 6) are connected to the IEEE1394 bus 2, respectively. ,
Each of these buses can connect up to 63 devices.

Each node is set with a node_ID as an identification number when the power is turned on. This node_ID is
As shown in FIG. 2, it is composed of a bus_ID for identifying a connected bus and a physical_ID for identifying which of the nodes connected to the bus.

The node 3 includes an IEEE1394 communication unit 31, a control unit 32, a RAM 33, and a ROM (including a configuration ROM) 3.
4 and an application unit 35. The IEEE1394 communication unit 31 is controlled by the control unit 32 or the application unit 35, packetizes data supplied from the control unit 32 or the application unit 35, transmits the packetized data via the IEEE1394 bus 1, and
94 Data is extracted from the packet received from the bus 1 and output to the control unit 32 or the application unit 35. The control unit 32 includes the application unit 3
Each part is controlled in response to a command from the control unit 5.

The RAM 33 stores the IEEE1394 CSR (Control and
The control unit 32 appropriately stores data and programs necessary for the control unit 32 to execute various processes. The ROM 34 stores various programs, various parameters, and the like. The node 6 has the same configuration as the node 3.

The node 4 (portalL) is a device that functions as a portal of the bridge 7, and includes an IEEE1394 communication unit 4.
1, a control unit 42, a RAM (functioning as a CSR for an IEEE1394 bridge) 43, and a ROM (including a Configuration ROM) 44. IEEE1394 communication unit 41
Is controlled by the control unit 42, packetizes data supplied from the control unit 42, transmits the packetized data via the IEEE1394 bus 1 or the infrared communication unit 61, and
The control unit 42 extracts data from the received packet and
Alternatively, the data is output to the infrared communication unit 61, and further, data is extracted from the packet received from the infrared communication unit 61 and output to the control unit 42 or the IEEE1394 bus 1. The control unit 42 can control the infrared communication unit 61 via an infrared communication control unit 62 in addition to controlling each unit.

In the RAM 43, a STREAM_CONTROL reg for describing a stream number used for synchronous communication and a PORTAL_C for describing information of a portal of the bridge 7 are described.
ONTROL reg is prepared. Here, reg is
Means register. The type of bridge (b
ridge type) is described in a bridge_type field.

The infrared communication unit 61 and the infrared communication unit 71
The infrared communication control unit 62 and the infrared communication control unit 7 respectively
2 to transmit and receive data between the node 4 and the node 5 using an infrared signal. Note that other communication means such as a cable or a radio wave may be used without using the infrared communication.

Node 5 as a portal of bridge 7
(PortalR) is an IEEE1394 communication unit 51, a control unit 52, an RA
M (CSR) 53 and ROM (including Configuration ROM)
54. The IEEE1394 communication unit 51 is controlled by the control unit 52, packetizes data supplied from the control unit 52, transmits the packetized data via the IEEE1394 bus 2 or the infrared communication unit 71, and transmits data from the packet received from the IEEE1394 bus 2 Is extracted and output to the control unit 52 or the infrared communication unit 71.
The control unit 5 extracts data from the received packet.
2 or IEEE1394 bus 2. The control unit 52 controls each unit, and also controls the infrared communication unit 71 via the infrared communication control unit 72.

The RAM 53 has a STREAM_CONTROL reg and a PORTAL_CONTROL reg. A bridge_type field is prepared in the ROM 54.

Next, the operation of the information processing system having the above configuration will be described. First, in the embodiment of the present invention,
The device (cycle master) that transmits the synchronization signal used in the synchronous communication is set for each bus.
It is assumed that the node 3 on the 1394 bus 1 and the node 5 on the IEEE 1394 bus 2 are cycle masters and transmit a synchronization signal. At this time, in the node 4, the IEEE1394 communication unit 41 receives the synchronization signal of the IEEE1394 bus 1, and the control unit 42 controls the infrared communication control unit 62, the infrared communication unit 61, the infrared communication unit 71, the infrared communication control unit 72, The control unit 52 causes the control unit 52 to transmit the synchronization signal to the node 5 via the unit 52.
Is transmitting a synchronization signal to the IEEE1394 bus 2.

Now, at a node connected to the IEEE1394 bus 2 (for example, the node 6), a situation arises in which a reset is required for some reason (for example, the power of the node 6 is manually turned on), and the bus is reset on the IEEE1394 bus 2. Is generated. In this case, each node connected to the IEEE1394 bus 2 erases data stored in the RAM 53. Then, when the reset processing is completed, another node is requested to become the root of the IEEE1394 bus 2 (highest node). As a result of the respective nodes performing the same processing, the node that has been reset most slowly among the nodes connected to the IEEE1394 bus 2 becomes the root. The node that has become the root becomes the cycle master, and outputs a synchronization signal after the bus setting initialization processing. Now, it is assumed that in the subsequent initialization of the bus setting, the node 5 as the portal has not become the cycle master of the IEEE1394 bus 2.

At this time, the node 5 executes the initialization processing shown in FIG. First, in step S11, the node 5
The control unit 52 checks whether it is the cycle master of the IEEE1394 bus 2 and ends the process if it is the cycle master. When each node becomes a cycle master, data indicating that the node itself has become a cycle master is described in a register of the IEEE1394 communication unit. Therefore, the control unit 52 can determine whether or not the node 5 is the cycle master by checking the register of the IEEE1394 communication unit 51.

If the node 5 is not the cycle master, the control unit 52 transmits a configuration packet (PHY Configuration Packet) for the node 5 to become the root of the IEEE1394 bus 2 in step S12.
Is transferred to each node connected thereto via the IEEE1394 bus 2 and the setting is transmitted to the entire bus. This notification is held in the register of the IEEE1394 communication unit of each node.

Next, at step 13, the control unit 52
Executes the bus reset for the IEEE1394 bus 2 through the IEEE1394 communication unit 51 and ends the processing. Each node erases the contents of the CSR.

In the register of the IEEE1394 communication unit of each node, which node becomes the root is stored based on the notification transmitted in step S12, so that the node 5 becomes the root of the IEEE1394 bus 2 and the node 5 becomes the root of the IEEE1394 bus 2. IEEE
Being a cycle master of the 1394 bus 2 is guaranteed by the IEEE1394 protocol. Therefore, after that, the node 5 outputs a synchronization signal to the IEEE1394 bus 2 as a cycle master after the completion of the initialization processing. Therefore, when the synchronization signal output from the node 3 to the IEEE1394 bus 1 is transferred via the node 4, the node 5 can transfer this to the IEEE1394 bus 2. Synchronous communication between the IEEE1394 bus 1 and the IEEE1394 bus 2 becomes possible.

In the embodiment of the present invention, the control unit 52 of the node 5 determines whether or not it is the cycle master in step S11 of FIG. 3. Nodes (eg IEEE13
94 The control unit 32 or the application unit 35 of the node 3 of the bus 1 may determine and execute the processing shown in the subsequent steps.

In the above description, an example has been described in which the node 5 performs the process of setting itself as the cycle master. However, as shown in FIG. 4, for example, the node 3 as the bridge manager sets the node 5 as the cycle master. May be performed. In this case, first, in step S21, the control unit 32 or the application unit 35 of the node 3 knows that a bus reset has occurred on the IEEE1394 bus 2 (when a bus reset occurs, it is a bridge manager (in this case, The notification is sent to the node 3), and a packet for inquiring whether the node 5 is the cycle master is transmitted to the control unit 52 of the node 5. This packet is transmitted to the IEEE 1394 communication unit 31, the IEEE 1394 bus 1, the IEEE 1394 communication unit 41, the infrared communication unit 61, the infrared communication unit 71, and the IEEE 1394 communication unit.
The data is sent to the control unit 52 via the 1394 communication unit 51. The control unit 52 of the node 5 transmits the inquiry to the node 3 via the reverse route.

Upon receiving the result from the control unit 52 of the node 5, the control unit 32 or the application unit 35 of the node 3 determines whether or not the node 5 is the cycle master in step S22 based on the received result. If it is the master, the process ends. Node 5
Is not the cycle master, the control unit 32 or the application unit 35 transmits the setting packet for the node 5 to become the root of the IEEE1394 bus 2 to the control unit of the node 5 in step S23. Request to 52. When receiving this request, the control unit 52 of the node 5 transmits a setting packet for making the node 5 the root to the IEEE1394 bus 2 as in the case of step S12 of FIG.

Next, in step S24, the control unit 3
2 or the application section 35 is an IEEE1394 bus 2
, The control unit 52 of the node 5 is requested to execute a bus reset, and the process ends. In response to this request, the control unit 52 of the node 5 responds to step S13 in FIG.
The bus reset of the IEEE1394 bus 2 is executed in the same manner as in the above case. As a result, the node 5 can be the root of the IEEE1394 bus 2 and the protocol of IEEE1394 ensures that the node 5 becomes the cycle master of the IEEE1394 bus 2.

The control unit 32 or the application unit 35 of the node 3 recognizes that the node 5 needs to be a cycle master in order to realize synchronous communication between the IEEE 1394 bus 1 and the IEEE 1394 bus 2. Therefore, the node 3 needs to be a bridge manager having a function of managing information on a plurality of bridges. Therefore, at this time, the control unit 32 and the application unit 35 of the node 3 have a function for the node 3 to be a bridge manager, the RAM 33 functions as a CSR for the bridge manager, and the ROM 34 is a ROM for the bridge manager. Hold necessary information.

Further, in the above, the control unit 52 of the node 5 executes the processing required to make the node 5 a cycle master of the IEEE1394 bus 2 in steps S12 and S13 of FIG. In this case, the control unit 52 of the node 5 may request another node (for example, the control unit 62 of the node 6 or the application unit 65) on the IEEE1394 bus 2 to perform processing.

FIG. 5 shows a node 6 as a bus manager.
FIG. 9 is a flowchart illustrating a process performed when a request is received from a node 5 and the node 5 is set as a cycle master. That is, in the IEEE1394 bus, when there is no bus manager or a bus manager for managing the bus, the isochronous resource manager for managing the resources for the synchronous communication processing is already allowed to change the cycle master. So, in this example,
It requests the bus manager to change the cycle master.

First, in step S31, the control unit 52 of the node 5 checks whether it is the cycle master of the IEEE1394 bus 2, and ends the processing if it is the cycle master. If it is not the cycle master, in step S32, the control unit 52 sends the setting packet for setting the node 5 to the root of the IEEE1394 bus 2 to the IEEE1394 bus 2 so as to send the setting packet to the IEEE1394 bus 2.
Is transmitted to the bus manager (node 6 in this example). This packet is transmitted to the IEEE1394 communication unit 5
1, transmitted to the control unit 62 or the application unit 65 of the node 6 via the IEEE1394 bus 2 and the IEEE1394 communication unit 61.

Next, in step 33, the control unit 52 of the node 5 transmits a packet requesting the control unit 62 or the application unit 65 of the node 6 to execute a bus reset for the IEEE1394 bus 2. The process ends. As a result, the node 5 can become the root of the IEEE1394 bus 2, and it is guaranteed by the IEEE1394 protocol that the node 5 becomes the cycle master of the IEEE1394 bus 2.

The node 6 must be a node that can transmit a setting packet for changing the cycle master, and a bus manager that manages the IEEE1394 bus 2 or a bus manager that exists on the IEEE1394 bus 2 If not, it is necessary to be an isochronous resource manager that manages synchronous communication resources of the IEEE1394 bus 2. Therefore, at this time, the control unit 62 and the application unit 65 of the node 6 have a function for the node 6 to be a bus manager or an isochronous resource manager, and the RAM 63 has a CS for the bus manager or the isochronous resource manager.
Functioning as R, the ROM 64 holds information necessary for the ROM for the bus manager or the isochronous resource manager.

In the above description, the control unit 52 of the node 5 determines whether or not it is the cycle master in step S11 of FIG. 3. The control unit 32 or the application unit 35 of the node 3 of the bus 1 may determine and request another node (for example, the control unit 62 or the application unit 65 of the node 6) of the IEEE1394 bus 2 to perform processing.

FIG. 6 shows a node 6 as a bus manager.
Is a flowchart for explaining a process in a case where a request is received from a node 3 as a bridge manager and a node 5 is set as a cycle master. First, step S41
When the control unit 32 or the application unit 35 of the node 3 knows that a bus reset has occurred on the IEEE1394 bus 2, the control unit 52 or the application unit 35 inquires of the control unit 52 of the node 5 whether the node 5 is a cycle master. To send packets. Controller 52 of node 5
When the control unit 32 or the application unit 35 of the node 3 receives a response to this inquiry from
From the answer, it is determined in step S42 whether or not the node 5 is the cycle master. If the node 5 is the cycle master, the process ends.

When the node 5 is not the cycle master, the control unit 32 or the application unit 35
First, in step S43, a node (a bus manager, or an isochronous resource manager if no bus manager exists) that can execute the function of changing the cycle master of the IEEE1394 bus 2 is known to know which node (node 6 in this example). The control unit 52 of the node 5
Sends an inquiry packet to. Upon receiving the result from the control unit 52 of the node 5, the control unit 3 of the node 3
2 or the application unit 35 knows the node that transmits the request to set the node 5 as the cycle master from the result. Next, in step S44, the control unit 32 or the application unit 35 of the node 3 transmits the setting packet for the node 5 to become the root of the IEEE 1394 bus 2 to the control unit 6 of the node 6,
Request 2

In step S45, the control unit 32 or the application unit 35 of the node 3
It requests the control unit 62 of the node 6 to execute the bus reset for the bus 2 and ends the processing. As a result, the node 5 can be the root of the IEEE1394 bus 2 and the protocol of IEEE1394 ensures that the node 5 becomes the cycle master of the IEEE1394 bus 2.

The control unit 32 or the application unit 35 of the node 3 recognizes that the node 5 needs to be a cycle master in order to realize synchronous communication between the IEEE 1394 bus 1 and the IEEE 1394 bus 2. For this, the node 3 needs to be a bridge manager having a function of managing information on a plurality of bridges. In order for the node 6 to be a node that can transmit a setting packet for changing the cycle master, the IEEE 1394 bus 2
If the bus manager does not exist on the IEEE1394 bus 2, the
94 It is necessary to be an isochronous resource manager that manages synchronous communication resources of the bus 2.

As described above, it is possible to prevent synchronous communication between a plurality of buses via a bridge from becoming impossible.

The computer program for performing the above-described various processes is provided to the user via a recording medium such as a magnetic disk or a CD-ROM, or provided to the user via a providing medium such as a network. It can be stored in a built-in RAM or hard disk for use.

[0045]

As described above, the information processing apparatus according to the first aspect, the information processing method according to the third aspect, and the fourth aspect.
According to the provision medium described in the above, the information processing apparatus performs a process for making itself a route on the bus to which the information processing device belongs, and performs a process for resetting the bus to which the information processing device belongs. Between the buses
This prevents a situation in which synchronous communication cannot be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an information processing system according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a configuration example of a node_ID.

FIG. 3 is a flowchart illustrating an initialization process of a node 5;

FIG. 4 is a flowchart illustrating an initialization process of a node 5;

FIG. 5 is a flowchart illustrating an initialization process of a node 5;

FIG. 6 is a flowchart illustrating an initialization process of a node 5;

[Explanation of symbols]

1, 2, IEEE1394 bus, 3, 4, 5, 6 nodes,
7 Bridge, 31, 41, 51 IEEE1394 communication unit,
32, 42, 52 control unit, 33, 43, 53 RA
M, 34, 44, 54 ROM, 61, 71 infrared communication unit, 62, 72 infrared communication control unit

Claims (4)

[Claims] An information processing apparatus for transmitting and receiving data between another bus and a bus to which the self belongs by synchronous communication, wherein the first information processing apparatus performs a process for setting itself as a route on the bus to which the self belongs. An information processing apparatus comprising: means; and second means for performing processing for resetting the bus to which it belongs. 2. The information processing apparatus according to claim 1, wherein the bus is an IEEE 1394 bus. 3. An information processing method for an information processing apparatus for exchanging data by synchronous communication between another bus and a bus to which the own bus belongs, wherein the information processing apparatus is used as a route on the bus to which the information processing apparatus belongs. An information processing method, comprising: a first step of performing processing; and a second step of performing processing for resetting the bus to which the information processing device belongs. 4. A computer program for use in an information processing apparatus for transmitting and receiving data by synchronous communication between another bus and a bus to which the own bus belongs, wherein the information processing apparatus is a route in the bus to which the information processing apparatus belongs. For providing a computer program comprising: a first step of performing a process for resetting the bus to which the information processing device belongs; and a second step of performing a process of resetting the bus to which the information processing device belongs.