JPH11205632A - Sample-and-hold circuit and clamp circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sample-and-hold(S/H) circuit and a clamp circuit with which high-accuracy temperature compensation is possible. SOLUTION: This S/B circuit is provided with an amplifier circuit 13 having a differential input terminal, S/H circuits 11 and 12 and pseudo S/H circuits 14 and 15 constituted so as to have the same temperature change characteristics or impedance as the S/H circuits. Besides, a feedback clamp circuit uses this S/H circuit. By inputting the output voltages of the pseudo S/H circuits 14 and 15 to the other terminal of the operational amplifier 13, the temperature drift of the S/H circuit or error voltage operating circuit is canceled or reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit and a clamp circuit, and more particularly to a sample and hold circuit and a clamp circuit capable of performing highly accurate temperature compensation.

[0002]

2. Description of the Related Art Conventionally, as a clamp circuit used in a video camera circuit or the like, a feedback clamp circuit capable of highly accurate clamping has been employed. FIG.
FIG. 11 is a circuit diagram illustrating a configuration of a conventional feedback clamp circuit. The video signal input from the input terminal is amplified by the buffer amplifier including the operational amplifier 10 and output to the output terminal. The output signal voltage is sampled by an electronic switch circuit 11 including an analog switch in synchronization with a clamp pulse generated at a time position to be sampled, and is held in a hold capacitor 12. The voltage of the capacitor 12 is input to a + (plus) terminal of an integrating circuit including the operational amplifier 16. Further, a resistor 18 is connected to a − (minus) terminal of the integrating circuit from a reference clamp voltage terminal, and a capacitor 17 is connected to an output terminal of the operational amplifier 16.

In the circuit shown in FIG. 8, a buffer amplifier comprising an operational amplifier 10 and a sample-and-hold circuit comprising an electronic switch 11 and a capacitor 12 comprise an operational amplifier 16.
Is formed, and the DC level of the signal is feedback-controlled so that the voltage held in the capacitor 12 becomes the reference clamp voltage with the time constant determined by the resistor 18 and the capacitor 17.

[0004]

In the conventional feedback clamp circuit as described above, the operational amplifier 1
0 is in the feedback loop, so the amplifier 10
The feedback control is performed including the temperature drift of. However, the temperature drift of the operational amplifier 16 forming the integration circuit cannot be suppressed. Therefore, it is necessary to give sufficient consideration to the design, such as using an operational amplifier with a low temperature drift as the operational amplifier 16 used in the integration circuit. The electronic switch 11 of the sample and hold circuit is, for example, a CMOS.
Use an analog switch element using FET,
Temperature change characteristics such as on-resistance, off-resistance, parasitic capacitance, and switching time of this element also pose a problem.

An object of the present invention is to provide a sample-hold circuit and a clamp circuit which can solve the above-mentioned problems of the prior art and can perform temperature compensation with high accuracy.

[0006]

SUMMARY OF THE INVENTION According to the present invention, there is provided a sample and hold circuit, comprising: amplifying means having a differential input terminal;
Sample-and-hold means having a hold output connected to one end of a differential input terminal, and pseudo sample-and-hold means having an output connected to the other end of the differential input terminal and having the same temperature change characteristics as the sample-and-hold means And characterized in that: There is also a feature in a feedback clamp circuit using the sample and hold circuit. According to the present invention, the pseudo-sample-and-hold means having the same temperature change characteristics and impedance as the sample-and-hold means is provided, and the output voltage of the means is input to the other end of the operational amplifier. (CMRR) is used to cancel the temperature drift of the sample and hold circuit or the error voltage calculation circuit.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a block diagram illustrating a circuit configuration example of a general video camera device. CCD
The video signal generated from 20 is reduced in noise by a CDS (correlated double sampling) circuit 21, and is amplified by an amplifier 23 through an LPF (low-pass filter) circuit 22. The clamp circuit 24 to which the present invention is applied includes:
The DC level of the video signal is clamped to a reference level by the configuration and operation described below. The blanking clean circuit 25 removes an unnecessary signal included in the output from the CCD 20 during the horizontal blanking period, and substitutes for the REF signal generated by the REF signal generation circuit 27.
Apply a pulse.

FIG. 3 is a waveform diagram showing input / output signal waveforms of the blanking clean circuit 25. FIG. 3A shows an example of a video signal waveform input from the clamp circuit 24 to the blanking clean circuit 25, and FIG. 3B shows a REF signal waveform input from the REF signal generation circuit 27 to the blanking clean circuit 25. It is. The blanking clean circuit 25 switches so as to output the REF pulse signal during the horizontal blanking period. Therefore, if the accuracy of the clamp circuit 24 is low, a level difference occurs at the time of switching, which may cause a pedestal to be out of order or a decrease in gain accuracy. Therefore, the clamp circuit 24 is required to have high accuracy.

Returning to FIG. 2, the AGC circuit 28 controls the gain of the video signal based on the REF pulse, and the video signal is output to the outside via the gamma correction circuit 29, the white clip circuit 30, and the driver circuit 31. The timing control circuit 26 supplies necessary timing pulses to the CCD and other circuits.

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a feedback clamp circuit to which the present invention is applied. The difference from the conventional feedback clamp circuit shown in FIG. 8 is that a correction circuit surrounded by a dotted line is added between the sample hold circuit and the integration circuit. The + terminal of the operational amplifier 13 of the correction circuit is connected to the connection point between the electronic switch 11 and the holding capacitor 12 of the sample and hold circuit, and the-terminal is also connected to one end of a parallel connection circuit of the electronic switch 15 and the capacitor 14. Have been. The other end of the parallel connection circuit of the electronic switch 15 and the capacitor 14 is connected to the output of the operational amplifier 13,
The output is further connected to the + terminal of the operational amplifier 16 of the integration circuit.

The capacitor 14 has the same characteristics and capacity as the capacitor 12 of the sample and hold circuit, and the electronic switch 15 has the same configuration as the electronic switch 11 of the sample and hold circuit. Both of the two electronic switches 11 and 15 are on / off controlled by a clamp pulse output from the timing control circuit 26. The capacitor 14 and the electronic switch circuit 15
Form a so-called pseudo sample-and-hold circuit.

FIG. 4 is a circuit diagram showing a configuration example of a commercially available analog switch IC used as the electronic switches 11 and 15. PM as a switching element
A circuit in which the OSFET (Q3) and the NMOSFET (Q4) are connected in parallel is driven complementarily by an inverter circuit composed of MOSFETs, Q1, and Q2. FE
Since T is used as a switching element, on-resistance, off-resistance, parasitic capacitance between terminals, switching speed, and the like may affect the signal, and these parameters also change due to temperature change.

The inventors have made prototypes and measured various circuit configurations based on the basic idea of canceling the fluctuation by adding the level fluctuation due to temperature change to both the + terminal and the-terminal of the operational amplifier. It has been confirmed that the circuit shown in FIG. 1 reduces the DC drift with respect to the temperature change as compared with the conventional circuit. The correction circuit of FIG. 1 basically operates as a buffer amplifier having an amplification degree of one. The cause of the temperature compensation is that the change in the output voltage of the sample-and-hold circuit composed of the switch 11 and the capacitor 12 due to the temperature is caused by the switch 15 and the capacitor 1
It is considered that the output voltage of the pseudo sample-and-hold circuit composed of No. 4 is equal to the change due to temperature, and is canceled by the common mode signal rejection characteristic (CMRR) of the operational amplifier 13. Alternatively, since the impedances seen from the + terminal and the − terminal of the operational amplifier 13 become equal, the operational amplifier 1
It is considered that the drift due to the temperature of No. 3 was reduced.

FIG. 5 is a circuit diagram showing the configuration of a second embodiment of the feedback clamp circuit. The first shown in FIG.
Although the integration circuit and the correction circuit are configured separately in the embodiment, the second embodiment is an example in which the integration type sample and hold circuit is also provided with a clamp and a temperature compensation function. In the circuit of FIG.
0, 40, the electronic switch 11, and the capacitor 41 form an integral sample-and-hold circuit.

One terminal of the parallel circuit of the electronic switch 43 and the capacitor 42 is connected to the negative terminal of the operational amplifier 40, and a reference clamp voltage is applied to the other terminal. The electronic switch 43 and the capacitor 42 are the same as the electronic switch 11 and the capacitor 41, respectively. The electronic switch 43 and the capacitor 42 also form a pseudo sample-and-hold circuit, and cancel the temperature drift of the sample-and-hold circuit or adjust the temperature of the operational amplifier 40 by equalizing the impedance of both input terminals as in the first embodiment. Due to the reduced drift,
It is considered that a temperature compensation effect is exhibited.

FIG. 6 is a circuit diagram showing the configuration of a third embodiment of the feedback clamp circuit. This embodiment is a modification of the first embodiment shown in FIG. 1, and differs from the first embodiment in the configuration of the pseudo sample-hold circuit. In the circuit of FIG. 6, a pseudo sample hold circuit is formed by the electronic switch 51 and the capacitor 50.
This circuit actually samples and holds the reference clamp voltage with exactly the same configuration as the sample / hold circuit. Therefore, the effect of canceling the characteristic change due to the temperature of the sample hold circuit and reducing the temperature drift of the operational amplifier 13 by making the impedances of both input terminals uniform can be expected.

FIG. 7 is a circuit diagram showing the configuration of a fourth embodiment of the feedback clamp circuit. This embodiment is a modification of the second embodiment shown in FIG. 5, and differs from the second embodiment in the configuration of the pseudo sample hold circuit. In the circuit of FIG. 7, a pseudo sample-hold circuit is formed by the electronic switch 43 and the capacitor 42. One end of the capacitor 42 is connected to the ground, and actually samples and holds the reference clamp voltage. In this embodiment, as in the second embodiment, the effect of canceling the characteristic change due to the temperature of the sample and hold circuit and reducing the temperature drift of the operational amplifier 13 by making the impedances of both input terminals uniform can be expected.

Although an example in which the present invention is applied to a video signal clamp circuit has been disclosed above, the sample and hold circuit and the clamp circuit of the present invention can be applied to a sample and hold circuit and a clamp circuit for an arbitrary signal.

[0019]

As described above, in the present invention,
By providing pseudo sample and hold means having the same temperature change characteristics and impedance as the sample and hold means, and inputting the output voltage of the means to the other end of the operational amplifier,
Since the temperature drift of the sample and hold circuit or the error voltage calculation circuit is canceled by using the common mode signal rejection characteristic (CMRR) of the operational amplifier, a simple circuit can be used in the sample and hold circuit and the clamp circuit using the circuit. Therefore, there is an effect that highly accurate temperature compensation can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a foot back clamp circuit.

FIG. 2 is a block diagram showing a circuit configuration of a general video camera device.

FIG. 3 is a waveform diagram showing input / output signal waveforms of a feedback clean circuit.

FIG. 4 is a circuit diagram illustrating a configuration example of an analog switch IC.

FIG. 5 is a circuit diagram showing the configuration of a second embodiment of the foot back clamp circuit.

FIG. 6 is a circuit diagram showing the configuration of a third embodiment of the foot back clamp circuit.

FIG. 7 is a circuit diagram showing a configuration of a fourth embodiment of a foot back clamp circuit.

FIG. 8 is a circuit diagram showing a configuration of a conventional foot pack clamp circuit.

[Explanation of symbols]

10, 13, 16 ... operational amplifier, 11, 15 ... electronic switch element, 12, 14, 17 ... capacitor, 18 ... resistor

Claims (4)

[Claims] Amplifying means having a differential input terminal; sample and hold means having a hold output connected to one end of the differential input terminal; output being connected to the other end of the differential input terminal; And a pseudo sample-and-hold means configured to have a change in output voltage with respect to the same as the sample-and-hold means. Amplifying means having a differential input terminal, sample-and-hold means having a hold output connected to one end of the differential input terminal, and an output connected to the other end of the differential input terminal; And a pseudo sample-and-hold means configured to have a change in output voltage with respect to the sample-and-hold means having the same characteristics as the sample-and-hold means. 3. The pseudo sample and hold means is a parallel connection circuit of the same electronic switch element and capacitor as the element used for the sample and hold means, and one end of the parallel connection circuit is connected to a minus terminal of the amplification means. The other end is connected to the output end of the amplifying means. The output of the amplifying means is input to an integrating circuit. The output of the integrating circuit is a buffer amplifier for amplifying an input signal via a resistor. 3. The feedback clamp circuit according to claim 2, wherein the feedback clamp circuit is connected to a negative terminal of the means, and an output of the buffer amplifying means is connected to a sample hold circuit. 4. A connection point between one end of an electronic switch of the sample and hold circuit and a holding capacitor is connected to a minus terminal of the amplifying means, and the other end of the holding capacitor is connected to an output terminal of the amplifying means. The pseudo sample-and-hold means is a parallel connection circuit of the same electronic switch element and capacitor as the element used for the sample-and-hold means, and one end of the parallel connection circuit is connected to a plus terminal of the amplification means; The terminal is connected to a reference voltage to be clamped, the output of the amplifying means is connected via a resistor to the plus terminal of a buffer amplifying means for amplifying an input signal, and the output of the buffer amplifying means is a sample-and-hold circuit. To form an integral sample-and-hold circuit with a clamping function as a whole. Feedback clamping circuit according to claim 2, characterized in that.