JPH11204784A - Manufacture for semiconductor device - Google Patents
Manufacture for semiconductor deviceInfo
- Publication number
- JPH11204784A JPH11204784A JP305098A JP305098A JPH11204784A JP H11204784 A JPH11204784 A JP H11204784A JP 305098 A JP305098 A JP 305098A JP 305098 A JP305098 A JP 305098A JP H11204784 A JPH11204784 A JP H11204784A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- insulating film
- semiconductor device
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 39
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 24
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 abstract description 24
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 description 15
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 13
- 239000010936 titanium Substances 0.000 description 13
- 229910052719 titanium Inorganic materials 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910021341 titanium silicide Inorganic materials 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造に
関するもので、特に微細加工ゲートを有するＭＯＳＦＥ
Ｔに使用されるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of a semiconductor device, and more particularly to a MOSFE having a microfabricated gate.
It is used for T.
【０００２】[0002]
【従来の技術】微細加工ゲートを有するＭＯＳＦＥＴの
製造工程の従来の技術においては、シリサイド反応が進
まず、シリサイド層が薄くなり、抵抗が増大する細線効
果が問題であった。2. Description of the Related Art In the prior art of the manufacturing process of a MOSFET having a microfabricated gate, there has been a problem of a thin wire effect in which a silicide reaction does not proceed, a silicide layer becomes thinner, and resistance increases.
【０００３】従来の技術を図１０から図１７を用いて説
明する。図１０に示すように、シリコン基板１０１上
に、熱酸化法でゲート酸化膜１０２を６ｎｍ形成する。
続けて図１１に示すように、前記ゲート酸化膜１０２上
にＬＰＣＶＤ（Low Pressure Chemical Vapor Depositi
on）法で多結晶シリコン膜１０３を２００ｎｍ堆積す
る。A conventional technique will be described with reference to FIGS. As shown in FIG. 10, a 6-nm gate oxide film 102 is formed on a silicon substrate 101 by a thermal oxidation method.
Subsequently, as shown in FIG. 11, LPCVD (Low Pressure Chemical Vapor Deposition) is formed on the gate oxide film 102.
On), a polycrystalline silicon film 103 is deposited to a thickness of 200 nm.
【０００４】その後図１２に示すように、リソグラフィ
ー技術で、レジストパターンを形成し、そのレジストパ
ターンをマスクとし、反応性イオンエッチング技術で、
多結晶シリコン膜１０３をエッチングし、レジストパタ
ーンを除去することで、ゲート電極を形成する。Thereafter, as shown in FIG. 12, a resist pattern is formed by a lithography technique, and the resist pattern is used as a mask.
The gate electrode is formed by etching the polycrystalline silicon film 103 and removing the resist pattern.
【０００５】引き続き図１３に示すように、ＮＭＯＳを
例にとると、Ｐ（リン）を５×１０１15c ｍ-2をイオン
注入し、熱処理で活性化することで、低濃度拡散層領域
１０４を形成する。[0005] As shown in FIG. 13, in the case of an NMOS, P (phosphorus) is ion-implanted into 5 × 10 15 cm −2 and activated by heat treatment to thereby form a low concentration diffusion layer region 104. To form
【０００６】その後図１４に示すように、ＬＰＣＶＤ法
で全面にシリコン窒化膜１０５を１００ｎｍ堆積し、反
応性イオンエッチング技術で全面をエッチングしシリコ
ン窒化膜１０５のスペーサを形成する。Thereafter, as shown in FIG. 14, a silicon nitride film 105 is deposited on the entire surface by LPCVD to a thickness of 100 nm, and the entire surface is etched by a reactive ion etching technique to form a spacer of the silicon nitride film 105.
【０００７】更に図１５に示すように、ＮＭＯＳを例に
とると、Ａｓ（砒素）を５×１０15ｃｍ-2をイオン注入
し、熱処理で活性化することで、高濃度拡散層領域１０
６を形成する。Further, as shown in FIG. 15, taking an NMOS as an example, As (arsenic) is ion-implanted at 5 × 10 15 cm −2 and activated by a heat treatment to thereby form a high-concentration diffusion layer region 10.
6 is formed.
【０００８】その後図１６に示すように、ＨＦを含む液
にてゲート電極上、拡散層上にあるシリコン酸化膜を除
去した後、全面にチタン膜１０７を５０ｎｍ堆積する。
続いて図１７に示すように、７５０℃の窒素雰囲気で熱
処理を施し、多結晶シリコン膜１０３および高濃度拡散
層領域１０６上にチタンシリサイド膜１０８を１００ｎ
ｍ形成し、硫酸と過酸化水素水の混合液により未反応チ
タン膜１０７を除去する。この場合図１７に示すよう
に、特にチタンサリサイドを用いると、微細パターン
（０．３μｍ以下から顕著になる）ではシリサイド反応
が進まず、シリサイド層が薄くなり、抵抗が増大する事
がわかっている。これを細線効果という。Then, as shown in FIG. 16, after removing the silicon oxide film on the gate electrode and the diffusion layer with a solution containing HF, a titanium film 107 is deposited to a thickness of 50 nm on the entire surface.
Subsequently, as shown in FIG. 17, a heat treatment is performed in a nitrogen atmosphere at 750 ° C., and a titanium silicide film 108 is formed on the polycrystalline silicon film 103 and the high concentration diffusion layer region 106 by 100 n.
m, and the unreacted titanium film 107 is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution. In this case, as shown in FIG. 17, it is known that, particularly when titanium salicide is used, the silicide reaction does not proceed in a fine pattern (remarkable from 0.3 μm or less), the silicide layer becomes thinner, and the resistance increases. . This is called the fine line effect.
【０００９】この細線効果を回避する方法として、側壁
のスペーサーの高さをゲートの上面よりも低くし、シリ
サイド反応をゲート上面と、側面からも起きるようにす
る方法が知られている。しかしながらシリコン窒化膜の
スペーサーの肩の高さを、ゲート電極よりも低くするの
はスペーサー形成のＲＩＥのエッチングをオーバーに行
う事、即ち拡散層を形成する基板表面に対し、オーバー
エッチングが起こる事を意味する。かかるエッチングを
行うと、基板を覆っている酸化膜では基板を保護でき
ず、基板を直接エッチングしてしまう場合が生ずる。As a method of avoiding the thin line effect, a method is known in which the height of the spacer on the side wall is made lower than the upper surface of the gate so that the silicide reaction occurs from the upper surface and the side surface of the gate. However, making the shoulder height of the spacer of the silicon nitride film lower than that of the gate electrode means that the RIE etching for forming the spacer is performed over, that is, over-etching occurs on the substrate surface on which the diffusion layer is formed. means. When such etching is performed, the oxide film covering the substrate cannot protect the substrate, and the substrate may be directly etched.
【００１０】このように基板表面をエッチングすると、
後の熱処理で、結晶欠陥（転位）が発生し易くなるなど
の問題がおきるため、シリコン窒化膜スペーサーのエッ
チング条件は酸化膜に対し、高い選択比が要求され、実
現が困難であった。When the substrate surface is etched as described above,
Since problems such as crystal defects (dislocations) are likely to be generated in the subsequent heat treatment, the etching conditions for the silicon nitride film spacer require a high selectivity with respect to the oxide film, making it difficult to realize.
【００１１】[0011]
【発明が解決しようとする課題】半導体装置の製造方法
の特に微細加工ゲートを有するＭＯＳＦＥＴにおいて、
チタンサリサイドを用いたときに、シリサイド反応が十
分に進まず、シリサイド層が薄くなり、これにより抵抗
が増大するという細線効果の問題が起こる。SUMMARY OF THE INVENTION In a method of manufacturing a semiconductor device, particularly in a MOSFET having a microfabricated gate,
When titanium salicide is used, the silicide reaction does not proceed sufficiently, and the silicide layer becomes thinner, which causes a problem of a thin wire effect that the resistance increases.
【００１２】本発明の目的はこの細線効果を防止し、制
御性良くシリコン窒化膜スペーサーの肩を落とすことが
でき、細いゲートでも抵抗の増大を防ぐ事ができる半導
体装置を提供することである。An object of the present invention is to provide a semiconductor device which can prevent the thin line effect, can lower the shoulder of the silicon nitride film spacer with good controllability, and can prevent an increase in resistance even with a thin gate.
【００１３】[0013]
【課題を解決するための手段】本発明による半導体装置
の製造方法は、半導体基板上にゲート酸化膜を形成する
工程と、上記ゲート酸化膜上に多結晶シリコンからなる
所定の形状のゲート電極を形成する工程と、前記ゲート
電極の側壁を含め基板表面に酸化膜とシリコン窒化膜か
らなる絶縁膜を形成する工程と、異方性エッチングによ
り前記ゲート電極の側壁に前記酸化膜とシリコン窒化膜
からなる絶縁膜スペーサを形成する工程と、前記スペー
サ膜のゲート側壁側に形成された絶縁膜の肩部を落とす
ようにエッチングして前記ゲート電極の側壁の上部を露
出させる工程と、ソースおよびドレイン部表面の酸化膜
を除去し、基板表面に金属膜を堆積する工程と、熱処理
により前記金層膜と前記多結晶シリコンおよび半導体基
板の前記ソースおよびドレイン部を反応させ、該ゲート
電極上部と該半導体基板上部に金属シリサイドを形成す
る工程とを備えた半導体装置の製造方法である。According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a gate oxide film on a semiconductor substrate, and forming a gate electrode of a predetermined shape made of polycrystalline silicon on the gate oxide film. Forming an insulating film made of an oxide film and a silicon nitride film on the substrate surface including the side wall of the gate electrode; and forming the insulating film made of the oxide film and the silicon nitride film on the side wall of the gate electrode by anisotropic etching. Forming an insulating film spacer, etching the lower portion of the insulating film formed on the side wall of the gate of the spacer film to expose the upper portion of the side wall of the gate electrode, and forming a source and drain portion. Removing a surface oxide film and depositing a metal film on the substrate surface; and heat treating the gold layer film, the polycrystalline silicon and the source and the semiconductor substrate. Fine drain portion is reacted, a method of manufacturing a semiconductor device including the step of forming a metal silicide on the gate electrode portion and the semiconductor substrate upper portion.
【００１４】そして、前記スペーサ膜がゲート電極側に
シリコン窒化膜外側にシリコン酸化膜の２層からなり、
りん酸を主成分にしたエッチング液でシリコン窒化膜の
肩部を落とすエッチングを行うことを特徴とする半導体
装置の製造方法であり、前記スペーサ膜がゲート電極側
にシリコン酸化膜外側にシリコン窒化膜の２層からな
り、フッ酸を含むエッチング液でシリコン酸化膜をエッ
チングし、肩を落とす事を特徴とする半導体装置の製造
方法であり、前記スペーサ膜がゲート電極側にシリコン
窒化膜外側にシリコン酸化膜の２層からなり、前記エッ
チングがケミカルドライエッチング（ＣＤＥ）技術を用
いたエッチングで、シリコン窒化膜をシリコン酸化膜に
対し選択的にエッチングすることを特徴とする半導体装
置の製造方法である。The spacer film is composed of two layers of a silicon oxide film outside the silicon nitride film on the gate electrode side,
A method of manufacturing a semiconductor device, wherein etching is performed by dropping a shoulder portion of a silicon nitride film with an etching solution containing phosphoric acid as a main component, wherein the spacer film has a silicon nitride film on a gate electrode side and a silicon nitride film on a gate electrode side. A method of manufacturing a semiconductor device, comprising etching a silicon oxide film with an etchant containing hydrofluoric acid and dropping a shoulder, wherein the spacer film has a silicon film on the gate electrode side and a silicon film on the outside of the silicon nitride film. A method of manufacturing a semiconductor device, comprising two layers of an oxide film, wherein the etching is performed using a chemical dry etching (CDE) technique, and the silicon nitride film is selectively etched with respect to the silicon oxide film. .
【００１５】本発明による半導体装置は、第１導電型の
半導体基板と、該半導体基板に形成された第２導電型の
ソースおよびドレイン領域と、第１導電型の半導体基板
表面に形成されたゲート酸化膜と、該ゲート酸化膜上に
形成された多結晶シリコン層からなるゲート電極とを有
する半導体装置において、前記多結晶シリコン層の側壁
に第１の絶縁膜が形成され、該第１の絶縁膜の外側にさ
らに第２の絶縁膜が形成され、そして前記多結晶シリコ
ン層の上部に金属シリサイド層が形成されていることを
特徴とする半導体装置である。さらに、第１の絶縁膜は
シリコン窒化膜であり第２の絶縁膜はシリコン酸化膜で
あることを特徴とする半導体装置であり、第１の絶縁膜
はシリコン酸化膜であり第２の絶縁膜はシリコン窒化膜
であることを特徴とする半導体装置であり、さらに前記
第１の絶縁膜の厚さは前記第２の絶縁膜より厚いことを
特徴とする半導体装置である。A semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type formed on the semiconductor substrate, and a gate formed on a surface of the semiconductor substrate of the first conductivity type. In a semiconductor device having an oxide film and a gate electrode made of a polycrystalline silicon layer formed on the gate oxide film, a first insulating film is formed on a side wall of the polycrystalline silicon layer. A semiconductor device, wherein a second insulating film is further formed outside the film, and a metal silicide layer is formed on the polycrystalline silicon layer. Further, the semiconductor device is characterized in that the first insulating film is a silicon nitride film and the second insulating film is a silicon oxide film, and the first insulating film is a silicon oxide film and the second insulating film Is a semiconductor device characterized by being a silicon nitride film, and the first insulating film is thicker than the second insulating film.
【００１６】[0016]
【発明の実施の形態】本発明は以下の実施の形態を図面
をもって説明するが、本発明はここで説明する実施の形
態に限定されるものではない。下記実施の形態は多様に
変化することができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the following embodiments with reference to the drawings, but the present invention is not limited to the embodiments described here. The following embodiments can be variously changed.
【００１７】本発明の実施の形態を以下に図１から図９
を用いて説明する。まず図１に示すように、シリコン基
板１上に、熱酸化法でゲート酸化膜２を例えば６ｎｍ形
成する。なお、基板はシリコン基板に限定されるもので
はなく、例えばＧａＡｓなどのIII-V 族半導体基板など
他の半導体基板を用いることも可能である。またゲート
酸化膜の形成法は熱酸化法に限定されるものではなく、
例えば蒸着法によって形成することも可能である。An embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG. First, as shown in FIG. 1, a 6-nm thick gate oxide film 2 is formed on a silicon substrate 1 by a thermal oxidation method. Note that the substrate is not limited to a silicon substrate, and another semiconductor substrate such as a III-V semiconductor substrate such as GaAs can be used. Also, the method of forming the gate oxide film is not limited to the thermal oxidation method,
For example, it can be formed by a vapor deposition method.
【００１８】続いて図２に示すように、ゲート酸化膜２
上に例えばＬＰＣＶＤ法で多結晶シリコン膜３を２００
ｎｍ堆積する。その後、図３に示すように、リソグラフ
ィー技術で、レジストパターンを形成し、そのレジスト
パターンをマスクとし、反応性イオンエッチング技術
で、多結晶シリコン膜３をエッチングし、その後レジス
トパターンを除去することで、ゲート電極を形成する。Subsequently, as shown in FIG. 2, the gate oxide film 2
For example, the polycrystalline silicon film 3 is
nm. Thereafter, as shown in FIG. 3, a resist pattern is formed by a lithography technique, the polycrystalline silicon film 3 is etched by a reactive ion etching technique using the resist pattern as a mask, and then the resist pattern is removed. Then, a gate electrode is formed.
【００１９】引き続き図４に示すように、ＮＭＯＳを例
にとると、Ｐ（リン）を１ｘ１０13ｃｍ-2をイオン注入
し、熱処理で活性化することで、ソースおよびドレイン
領域となる低濃度拡散層領域４を形成する。As shown in FIG. 4, taking an NMOS as an example, P (phosphorus) is ion-implanted at 1 × 10 13 cm −2 and activated by a heat treatment, so that low-concentration diffusions serving as source and drain regions are obtained. The layer region 4 is formed.
【００２０】その後図５に示すように、例えばＬＰＣＶ
Ｄ法で全面にシリコン窒化膜５を堆積し、引き続き例え
ばＰＣＶＤ法にてシリコン酸化膜９を堆積する。シリコ
ン窒化膜５の厚さはシリコン酸化膜より厚くするのが望
ましく、この実施の態様ではシリコン窒化膜５は厚さ８
０ｎｍで堆積し、シリコン酸化膜９は厚さ２０ｎｍで堆
積される。Thereafter, as shown in FIG.
A silicon nitride film 5 is deposited on the entire surface by the method D, and a silicon oxide film 9 is subsequently deposited by, for example, the PCVD method. It is desirable that the thickness of the silicon nitride film 5 be larger than that of the silicon oxide film. In this embodiment, the silicon nitride film 5 has a thickness of 8 mm.
The silicon oxide film 9 is deposited with a thickness of 20 nm.
【００２１】次に図６に示すように、反応性イオンエッ
チング技術を用いて、全面を縦方向に異方性エッチング
し、シリコン酸化膜９及びシリコン窒化膜５からなるス
ペーサを形成する。Next, as shown in FIG. 6, the entire surface is anisotropically etched in the vertical direction by using a reactive ion etching technique to form a spacer composed of a silicon oxide film 9 and a silicon nitride film 5.
【００２２】その後図７に示すように、熱燐酸処理に
て、ゲート電極側壁の形成したスペーサのシリコン窒化
膜５の上部を４００オングストローム程度除去する。本
実施の態様では、図７に示すように、シリコン窒化膜５
の幅は約８００オングストローム、シリコン酸化膜９の
幅は約２００オングストローム、多結晶シリコン膜３の
幅は約２５００オングストロームである。そしてシリコ
ン窒化膜５の上部表面は多結晶シリコン膜３の上部表面
より４００オングストローム下部に形成される。Then, as shown in FIG. 7, the upper portion of the silicon nitride film 5 of the spacer formed on the side wall of the gate electrode is removed by about 400 Å by hot phosphoric acid treatment. In the present embodiment, as shown in FIG.
Is about 800 angstroms, the width of the silicon oxide film 9 is about 200 angstroms, and the width of the polycrystalline silicon film 3 is about 2500 angstroms. The upper surface of silicon nitride film 5 is formed 400 angstroms lower than the upper surface of polycrystalline silicon film 3.
【００２３】このような状態にすると、シリコン窒化膜
５の上部領域が除去されたことにより、多結晶シリコン
膜３の左右露出した側面からも多結晶シリコン膜に次の
工程においてＡｓがイオン注入され、後のチタン膜によ
るシリサイド反応が容易に進行し、十分な厚さのシリサ
イド層を形成することができる。In this state, as the upper region of silicon nitride film 5 is removed, As is ion-implanted into the polycrystalline silicon film from the left and right exposed side surfaces of polycrystalline silicon film 3 in the next step. The silicide reaction by the subsequent titanium film easily proceeds, and a silicide layer having a sufficient thickness can be formed.
【００２４】さらに、ＮＭＯＳを例にとると、Ａｓ（砒
素）を５ｘ１０15ｃｍ-2をイオン注入し、熱処理で活性
化することで、高濃度拡散層領域６を形成する。その
後、希ＨＦ処理で、多結晶シリコン膜からなるゲート表
面及び高濃度拡散層領域６の基板表面の酸化膜を除去
し、例えばＤＣマグネトロンスパッタ法にて、図８に示
すように多結晶シリコン膜３上と高濃度拡散層領域６上
にチタン膜７を５０ｎｍ堆積する。チタンに代えて、例
えばモリブデンやタングステンなど他の高融点金属を用
いることも可能であるが、チタンがより望ましい。Further, taking an NMOS as an example, 5 × 10 15 cm −2 of As (arsenic) is ion-implanted and activated by heat treatment to form a high-concentration diffusion layer region 6. Thereafter, the oxide film on the gate surface made of the polycrystalline silicon film and the substrate surface in the high-concentration diffusion layer region 6 is removed by a dilute HF treatment, and the polycrystalline silicon film is formed by, for example, DC magnetron sputtering as shown in FIG. 3 and a high concentration diffusion layer region 6, a titanium film 7 is deposited to a thickness of 50 nm. Instead of titanium, other refractory metals such as molybdenum and tungsten can be used, but titanium is more preferable.
【００２５】次に、７５０℃の窒素雰囲気で熱処理を施
し、多結晶シリコン膜３およびソースおよびドレイン電
極が形成される高濃度拡散層領域６上に選択的にチタン
シリサイド膜８を１００ｎｍ形成し、硫酸と過酸化水素
水の混合液により未反応チタン膜７を除去する。多結晶
シリコン膜３上ではスペーサ膜の除去された上部側壁に
おいてもチタンと多結晶シリコンとが反応し、このため
図９に示すように、均一で十分な厚さのシリサイド層が
形成される。Next, heat treatment is performed in a nitrogen atmosphere at 750 ° C. to selectively form a 100 nm thick titanium silicide film 8 on the polycrystalline silicon film 3 and the high concentration diffusion layer region 6 where the source and drain electrodes are to be formed. The unreacted titanium film 7 is removed with a mixture of sulfuric acid and hydrogen peroxide. On the polycrystalline silicon film 3, titanium and polycrystalline silicon also react on the upper side wall from which the spacer film has been removed, and as a result, a uniform and sufficient thickness silicide layer is formed as shown in FIG.
【００２６】また、本発明の実施の形態ではシリコン窒
化膜の上部領域を除去するために、熱燐酸を用いたが、
ケミカルドライエッチング（ＣＤＥ）技術によるエッチ
ングでも同じ効果が得られる。In the embodiment of the present invention, hot phosphoric acid is used to remove the upper region of the silicon nitride film.
The same effect can be obtained by chemical dry etching (CDE).
【００２７】以上の実施の態様のスペーサ膜は、内側
（ゲート側）にシリコン窒化膜を形成し、外側にシリコ
ン酸化膜を形成したものであるが、逆に内側にシリコン
酸化膜を形成し、外側にシリコン窒化膜を形成する方法
を用いることも可能である。この場合には、フッ酸を含
むエッチング液で該内側シリコン酸化膜をエッチングし
て、スペーサの肩を落とす方法を用いる。The spacer film of the above embodiment has a silicon nitride film formed on the inner side (gate side) and a silicon oxide film formed on the outer side. Conversely, a silicon oxide film is formed on the inner side. It is also possible to use a method of forming a silicon nitride film on the outside. In this case, a method is used in which the inner silicon oxide film is etched with an etchant containing hydrofluoric acid to drop the shoulder of the spacer.
【００２８】図１８はゲートのシート抵抗のゲート幅依
存性を示す図である。図１８は縦軸にシート抵抗、横軸
にゲート幅を取っており、ゲート幅を微細化していく
と、従来技術では０．３５μｍ前後で急激にシート抵抗
が上昇してしまうのに対し、本発明による方法を用いる
と、シート抵抗が上昇するのは０．２μｍ前後と低下す
る。FIG. 18 is a diagram showing the gate width dependence of the gate sheet resistance. FIG. 18 shows the sheet resistance on the ordinate and the gate width on the abscissa. As the gate width is reduced, the sheet resistance sharply increases at around 0.35 μm in the prior art. With the method according to the invention, the increase in sheet resistance decreases to around 0.2 μm.
【００２９】このことからもわかるように、本発明を用
いることにより、制御性良くシリコン窒化膜スペーサー
の上部領域を除去してゲート側壁の上部を露出すること
ができ、その結果、微細なゲート電極でも十分な厚さの
シリサイドを形成でき、ゲート電極部の抵抗の増大を防
ぐ事ができる。As can be seen from the above, by using the present invention, the upper region of the silicon nitride film spacer can be removed and the upper portion of the gate sidewall can be exposed with good controllability. However, a silicide having a sufficient thickness can be formed, and an increase in the resistance of the gate electrode portion can be prevented.
【００３０】[0030]
【発明の効果】上記のように本発明を用いることによ
り、制御性良くシリコン窒化膜スペーサーの上部領域を
除去することができ、微細なゲート電極でも均一で十分
な厚さのチタンシリサイドを形成することができるよう
になり、その結果、抵抗の急激な増大を防ぐ事ができる
ようになった。As described above, by using the present invention, the upper region of the silicon nitride film spacer can be removed with good controllability, and a uniform and sufficient thickness of titanium silicide can be formed even with a fine gate electrode. As a result, it is possible to prevent a sudden increase in resistance.
【図１】本発明の実施形態に係る半導体装置製造方法の
ゲート酸化膜形成後を示す断面図。FIG. 1 is a sectional view showing a state after a gate oxide film is formed in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の実施形態に係る半導体装置製造方法の
多結晶シリコン膜形成後を示す断面図。FIG. 2 is a sectional view showing a state after a polycrystalline silicon film is formed in the method for manufacturing a semiconductor device according to the embodiment of the present invention.
【図３】本発明の実施形態に係る半導体装置製造方法の
ゲート電極形成後を示す断面図。FIG. 3 is a sectional view showing a state after a gate electrode is formed in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
【図４】本発明の実施形態に係る半導体装置製造方法の
低濃度拡散層領域形成後を示す断面図。FIG. 4 is a sectional view showing a state after forming a low-concentration diffusion layer region in the semiconductor device manufacturing method according to the embodiment of the present invention;
【図５】本発明の実施形態に係る半導体装置製造方法の
シリコン窒化膜およびシリコン酸化膜形成後を示す断面
図。FIG. 5 is a sectional view showing a state after a silicon nitride film and a silicon oxide film are formed in the semiconductor device manufacturing method according to the embodiment of the present invention;
【図６】本発明の実施形態に係る半導体装置製造方法の
スペーサ形成後を示す断面図。FIG. 6 is a sectional view showing a state after a spacer is formed in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
【図７】本発明の実施形態に係る半導体装置製造方法の
シリコン窒化膜の肩部を落とした後を示す断面図。FIG. 7 is a sectional view showing a state after the shoulder of the silicon nitride film is dropped in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
【図８】本発明の実施形態に係る半導体装置製造方法の
チタン膜形成後を示す断面図。FIG. 8 is a sectional view showing a state after a titanium film is formed in the method for manufacturing a semiconductor device according to the embodiment of the present invention.
【図９】本発明の実施形態に係る半導体装置製造方法の
チタンシリサイド膜形成後を示す断面図。FIG. 9 is a sectional view showing a state after a titanium silicide film is formed in the semiconductor device manufacturing method according to the embodiment of the present invention.
【図１０】従来の技術の半導体装置製造方法のゲート酸
化膜形成後を示す断面図。FIG. 10 is a sectional view showing a state after a gate oxide film is formed in a conventional semiconductor device manufacturing method.
【図１１】従来の技術の半導体装置製造方法の多結晶シ
リコン膜形成後を示す断面図。FIG. 11 is a cross-sectional view showing a state after a polycrystalline silicon film is formed in a conventional semiconductor device manufacturing method.
【図１２】従来の技術の半導体装置製造方法のゲート電
極形成後を示す断面図。FIG. 12 is a sectional view showing a state after a gate electrode is formed in a conventional semiconductor device manufacturing method.
【図１３】従来の技術の半導体装置製造方法の低濃度拡
散層領域形成後を示す断面図。FIG. 13 is a cross-sectional view showing a state after forming a low-concentration diffusion layer region in a conventional semiconductor device manufacturing method.
【図１４】従来の技術の半導体装置製造方法のスペーサ
形成後を示す断面図。FIG. 14 is a sectional view showing a state after a spacer is formed in a conventional semiconductor device manufacturing method.
【図１５】従来の技術の半導体装置製造方法の高濃度拡
散層領域形成後を示す断面図。FIG. 15 is a cross-sectional view showing a state after forming a high-concentration diffusion layer region in a conventional semiconductor device manufacturing method.
【図１６】従来の技術の半導体装置製造方法のチタン膜
形成後を示す断面図。FIG. 16 is a sectional view showing a state after a titanium film is formed in a conventional semiconductor device manufacturing method.
【図１７】従来の技術の半導体装置製造方法のチタンシ
リサイド膜形成後を示す断面図。FIG. 17 is a sectional view showing a state after a titanium silicide film is formed in a conventional semiconductor device manufacturing method.
【図１８】本発明の実施形態に係る半導体装置を用いて
作製したゲートのシート抵抗のゲート幅依存性を示す
図。FIG. 18 is a view showing the gate width dependence of the sheet resistance of a gate manufactured using the semiconductor device according to the embodiment of the present invention.
【符号の説明】 １、１０１…シリコン基板 ２、１０２…ゲート酸化膜 ３、１０３…多結晶シリコン膜 ４、１０４…低濃度拡散層領域 ５、１０５…シリコン窒化膜 ６、１０６…高濃度拡散層領域 ９…シリコン酸化膜 ７、１０７…チタン膜 １０８…チタンシリサイド膜[Description of Signs] 1, 101: silicon substrate 2, 102: gate oxide film 3, 103: polycrystalline silicon film 4, 104: low-concentration diffusion layer region 5, 105: silicon nitride film 6, 106: high-concentration diffusion layer Region 9: silicon oxide film 7, 107: titanium film 108: titanium silicide film
Claims (8)
板上にゲート酸化膜を形成する工程と、 上記ゲート酸化膜上に多結晶シリコンからなる所定の形
状のゲート電極を形成する工程と、 前記ゲート電極の側壁を含め基板表面に酸化膜とシリコ
ン窒化膜からなる絶縁膜を形成する工程と、 前記絶縁膜を異方性エッチングして、前記ゲート電極の
側壁に残在させる工程と、 前記ゲート電極側壁側に残存する絶縁膜の上部領域を除
去して前記ゲート電極の側壁の上部を露出させる工程
と、 ソースおよびドレイン部表面の酸化膜を除去し、基板上
に金属膜を形成する工程と、 熱処理により前記金層膜と前記多結晶シリコンおよび半
導体基板の前記ソースおよびドレイン領域を反応させ、
該ゲート電極上部と該半導体基板上部に金属シリサイド
を形成する工程とを備えた半導体装置の製造方法。A step of forming a gate oxide film on a semiconductor substrate having source and drain regions; a step of forming a gate electrode of a predetermined shape made of polycrystalline silicon on the gate oxide film; Forming an insulating film composed of an oxide film and a silicon nitride film on the surface of the substrate including the side wall of the gate electrode; anisotropically etching the insulating film so as to remain on the side wall of the gate electrode; Removing the upper region of the insulating film remaining on the side to expose the upper portion of the side wall of the gate electrode; removing the oxide film on the surface of the source and drain portions to form a metal film on the substrate; By reacting the source and drain regions of the polycrystalline silicon and semiconductor substrate with the gold layer film,
Forming a metal silicide on the gate electrode and on the semiconductor substrate;
は、上部表面が露出したシリコン窒化膜の外側にシリコ
ン酸化膜が形成される２層構造からなり、りん酸を主成
分にしたエッチング液でシリコン窒化膜の上部領域を除
去することを特徴とする請求項１記載の半導体装置の製
造方法。2. An etching solution containing phosphoric acid as a main component, wherein the insulating film remaining on the side wall of the gate electrode has a two-layer structure in which a silicon oxide film is formed outside a silicon nitride film having an exposed upper surface. 2. The method according to claim 1, wherein the upper region of the silicon nitride film is removed by the method.
膜が形成される２層構造からなり、ケミカルドライエッ
チング（ＣＤＥ）で、シリコン酸化膜を除去することを
特徴とする請求項１または請求項２記載の半導体装置の
製造方法。3. The semiconductor device according to claim 1, wherein the silicon oxide film is formed outside the silicon nitride film and has a two-layer structure, and the silicon oxide film is removed by chemical dry etching (CDE). 3. The method for manufacturing a semiconductor device according to item 2.
膜が形成される２層構造からなり、フッ酸を含むエッチ
ング液でシリコン酸化膜の上部領域を除去することを特
徴とする請求項１から請求項３までの何れかに記載の半
導体装置の製造方法。4. The silicon oxide film has a two-layer structure in which a silicon oxide film is formed outside the silicon nitride film, and an upper region of the silicon oxide film is removed with an etching solution containing hydrofluoric acid. A method for manufacturing a semiconductor device according to claim 3.
成された導電型のソースおよびドレイン領域と、導電型
の半導体基板上に形成されたゲート酸化膜と、該ゲート
酸化膜上に形成された多結晶シリコン層からなるゲート
電極とを有する半導体装置において、 前記多結晶シリコン層の側壁に第１の絶縁膜が形成さ
れ、該第１の絶縁膜の外側に第２の絶縁膜が形成され、
前記多結晶シリコン層の上部に金属シリサイド層が形成
されていることを特徴とする半導体装置。5. A conductive semiconductor substrate, conductive source and drain regions formed on the semiconductor substrate, a gate oxide film formed on the conductive semiconductor substrate, and a gate oxide film formed on the gate oxide film. A first insulating film is formed on a side wall of the polycrystalline silicon layer, and a second insulating film is formed outside the first insulating film. And
A semiconductor device, wherein a metal silicide layer is formed on the polycrystalline silicon layer.
の絶縁膜はシリコン酸化膜であることを特徴とする請求
項５に記載の半導体装置。6. The method according to claim 1, wherein the first insulating film is a silicon nitride film.
6. The semiconductor device according to claim 5, wherein said insulating film is a silicon oxide film.
の絶縁膜はシリコン窒化膜であることを特徴とする請求
項５に記載の半導体装置。7. The first insulating film is a silicon oxide film and a second insulating film.
6. The semiconductor device according to claim 5, wherein said insulating film is a silicon nitride film.
縁膜より厚いことを特徴とする請求項５、６または７に
記載の半導体装置。8. The semiconductor device according to claim 5, wherein the first insulating film has a thickness greater than that of the second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP305098A JPH11204784A (en) | 1998-01-09 | 1998-01-09 | Manufacture for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP305098A JPH11204784A (en) | 1998-01-09 | 1998-01-09 | Manufacture for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11204784A true JPH11204784A (en) | 1999-07-30 |
Family
ID=11546503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP305098A Pending JPH11204784A (en) | 1998-01-09 | 1998-01-09 | Manufacture for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11204784A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030049566A (en) * | 2001-12-15 | 2003-06-25 | 주식회사 하이닉스반도체 | a method for manufacturing of transistor of semiconductor |
| JP2005093580A (en) * | 2003-09-16 | 2005-04-07 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| JP2007517398A (en) * | 2003-12-30 | 2007-06-28 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Method for forming rectangular spacer of semiconductor device |
| JP2014195091A (en) * | 1998-11-13 | 2014-10-09 | Intel Corp | Method and device for improving salicide resistance on polycrystal silicon gate |
-
1998
- 1998-01-09 JP JP305098A patent/JPH11204784A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014195091A (en) * | 1998-11-13 | 2014-10-09 | Intel Corp | Method and device for improving salicide resistance on polycrystal silicon gate |
| KR20030049566A (en) * | 2001-12-15 | 2003-06-25 | 주식회사 하이닉스반도체 | a method for manufacturing of transistor of semiconductor |
| JP2005093580A (en) * | 2003-09-16 | 2005-04-07 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| JP2007517398A (en) * | 2003-12-30 | 2007-06-28 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Method for forming rectangular spacer of semiconductor device |
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