JPH11204751A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: A method of manufacturing a semiconductor device, comprising the steps of forming a contact hole in an insulating film and connecting a conductive pattern through the contact hole, relates to a method for forming a contact hole having a large aspect ratio in a thick interlayer insulating film. Improve coverage. A step of forming an impurity diffusion layer formed in a semiconductor layer, and a step of forming a hole having a bow-shaped bulge at least partially by locally etching an interlayer insulating film. Thinning the interlayer insulating film 4 down to the portion where the hole 6 has the largest bulge or a portion lower than the portion by etching or polishing; Forming a conductive layer 9 therein, and patterning the conductive layer 9 so that the conductive layer 9 is left in the hole 6 and the interlayer insulating film 4 is formed.
Forming a wiring pattern thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a hole in an insulating film,
The present invention relates to a method for manufacturing a semiconductor device having a step of connecting a lower side and an upper side conductive pattern through the hole.

[0002]

2. Description of the Related Art DRAM (dynamic random access memor)
y) The storage electrode of the capacitor applied to the cell is roughly classified into three types: a planar type, a trench type, and a stack type. For example, a fin type or a cylindrical type is adopted as a stack type capacitor. It is necessary to increase the capacity per unit area of the DRAM cell capacitor from the viewpoint of the demand for higher storage capacity and higher density of the memory. For this reason, when the stack type is adopted, a structure in which the height of the capacitor is increased is adopted.

A DRAM cell having a capacitor having a cylindrical storage electrode has a structure as shown in FIG. 12, for example. In FIG. 12, a MOS transistor is formed on a surface of a semiconductor substrate 101 in a region surrounded by a field oxide film 102 for element isolation.
A transistor Tr is formed. The MOS transistor Tr has a gate electrode 105 formed on a silicon substrate 101 via a gate insulating film, and a pair of impurity diffusion layers 106 formed on the silicon substrate 101 on both sides of the gate electrode 105. I have. The top and side surfaces of the gate electrode 105 are covered with a gate covering insulating film 107.

[0004] The MOS transistor Tr, the field oxide film 102, and the gate covering insulating film 107 are covered with a first interlayer insulating film 110. Further, the first interlayer insulating film 110 has one impurity diffusion layer of the MOS transistor.
A contact hole 111 is formed to connect to the storage electrode 112 having a U-shaped cross section and the storage electrode 112.
A capacitor comprising a dielectric film 113 formed on the inner surface of the substrate and a counter electrode 114 further formed on the dielectric film 113 is formed.

The capacitor is covered with a second interlayer insulating film 116, and a contact hole 115 for a bit line is formed in the second interlayer insulating film and the first interlayer insulating film. When the DRAM cell having the above configuration is employed, the thick first and second interlayer insulating films 110 and 116 also exist in the peripheral circuits of the DRAM cell.

[0006]

However, the contact holes 115 formed in the thick first and second interlayer insulating films 110 and 116 become deeper according to the film thickness.
The coverage of the bit line formed in the contact hole 115 is deteriorated. It is an object of the present invention to provide a method of manufacturing a semiconductor device for improving the coverage of a conductive film in a contact hole having a large aspect ratio in a thick interlayer insulating film.

[0007]

Means for Solving the Problems The above-mentioned problems are solved in FIGS.
As illustrated in FIG. 2, a step of forming an impurity diffusion layer formed in a semiconductor layer or an interlayer insulating film covering a conductive pattern on the insulating film, and locally etching the interlayer insulating film, A step of partially forming a bulging hole having a bowing shape, and a step of thinning the interlayer insulating film up to a bulging part or a lower part of the hole by etching or polishing, Forming a conductive layer on the thinned interlayer insulating film and in the hole, and patterning the conductive layer to leave the hole in the hole and form a wiring pattern on the interlayer insulating film. And a step of forming a semiconductor device.

In the method of manufacturing a semiconductor device described above,
The first layer is made of silicon oxide containing an element which becomes an impurity of a semiconductor. In the method for manufacturing a semiconductor device described above, the growth of the insulating film includes a step of growing a first layer that suppresses the etching or the polishing, and a step of growing the first layer that is a target of the etching or the polishing. Growing on one layer. In this case, the growth of the second layer is a growth of silicon oxide containing an element serving as a semiconductor impurity, and the growth of the first layer is a growth of any of silicon nitride, silicon oxide, and silicon. Is also good. The growing of the interlayer insulating film may include a step of forming a third layer made of the same material as the second layer below the first layer.

In the method of manufacturing a semiconductor device described above,
The etching for thinning the interlayer insulating film,
It is characterized in that it is etching using fluorocarbon plasma, or the polishing for thinning the interlayer insulating film is chemical mechanical polishing. Next, the operation of the present invention will be described.

According to the present invention, the hole in the interlayer insulating film is formed in a bowing shape, and the upper opening of the hole is widened by removing the upper portion having a smaller diameter by polishing or etching. Holes that can improve wiring coverage are formed even with a thick interlayer insulating film. When plasma etching is used to remove the upper portion of the interlayer insulating film, the periphery of the opening above the hole is rounded, so that the coverage is further improved.

The interlayer insulating film may cover the diffusion layer of the semiconductor substrate or may be used for a multilayer wiring structure.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. (First Embodiment) FIGS. 1 (a) to 1 (c), 2 (a) to 2 (c)
FIGS. 3A and 3B are cross-sectional views showing steps of forming a multilayer wiring structure in a peripheral circuit of the semiconductor memory device according to the first embodiment of the present invention. FIGS. FIG. 4 is a cross-sectional view illustrating a step of forming a wiring.

An impurity diffusion layer 3 surrounded by a field oxide film 2 is formed on a silicon substrate (semiconductor substrate) 1 shown in FIG. The impurity diffusion layer 3 is p-type when the silicon substrate 1 is n-type, and is n-type when the silicon substrate 1 is p-type. An insulating material containing at least one of an n-type impurity and a p-type impurity, for example, BPSG (boro-ph) is formed on the impurity diffusion layer 3 and the field oxide film 2.
An interlayer insulating film 4 made of osphe silicate glass) is formed. BPSG is grown by a CVD method using a mixed gas containing, for example, silane (SiH ₄ ), diborane (B ₂ H ₆ ), phosphine (PH ₃ ), and oxygen (O ₂ ).
It is grown to a thickness of at least μm. In the first embodiment, the thickness is set to 2.5 μm.

Since the step of growing the interlayer insulating film 4 is performed after the formation of the capacitor 20 of the DRAM cell as shown in FIG. 3A, the DRAM cell is also covered with the interlayer insulating film 4. Become. The structure of the DRAM cell will be described later. Next, on the interlayer insulating film 4,
A resist 5 for excimer laser light is applied to a thickness of about 1.2 μm. The resist 5 is of a type suitable for the light used for exposure. For example, when exposure is performed by excimer laser light irradiation, a resist having a structure sensitive to excimer laser is used.

Thereafter, by exposing and developing the resist 5, a window 5a for forming a contact hole is formed above the impurity diffusion layer 3 as shown in FIG. 1B. Subsequently, the silicon substrate 1 is placed in the chamber 10 of the parallel plate type etching apparatus shown in FIG. Then, impurities (IIIb group element or Vb group element) are passed through the window 5a of the resist 5.
1 is etched to form an interlayer insulating film 4 containing
As shown in (c), holes 6 are formed in the interlayer insulating film 4.

The etching conditions are as follows. For example, the pressure in the chamber 10 shown in FIG.
orr, and a high-frequency power supply 12 having a frequency of 27 MHz and a power of 2000 W is connected to the upper electrode 11 therein.
3. High frequency power supply with frequency 800MHz and power 900W
4 is applied. In etching, CHF ₃ and Ar
A mixed gas containing O ₂ or a mixed gas containing C ₄ F ₈ , CO, Ar and O ₂ is introduced between the upper electrode 11 and the lower electrode 13 through the gas inlet 15, and either of the mixed gases is turned into plasma. , The interlayer insulating film 4 generated by the plasma generated thereby.
Is etched.

In the hole 6 formed under such conditions, a bulging bowing shape appears near the center.
The thickest part of the hole 6 was located at a position about 1.75 μm above the bottom of the hole 6. Next, after the resist 5 is removed, the interlayer insulating film 4 is polished by a chemical mechanical polishing (CMP) method so that the film thickness becomes about 0.75 μm.
The polishing is stopped at the portion where the hole 6 is thickest. The cross-sectional shape of the remaining hole 6 is shown in FIG.
As shown in the figure, the upper part has a cup-shaped bulge, and its aspect ratio is about 7. In this case, the adjustment of the film thickness of the interlayer insulating film 4 is performed by controlling the polishing time based on the polishing rate per unit time which has been checked in advance.

Subsequently, as shown in FIG. 2B, Ti, TiN and Al are sequentially formed on the interlayer insulating film 4 and in the holes 6 by a sputtering method. The multilayer metal is used as a conductive film 7 and is patterned by a photolithography method, so that the portion remaining in the hole 6 is used as a plug 8 and a wiring 9 passing over the hole 6 is formed.

On the other hand, as shown in FIG. 3B, a bit line contact hole 21 is formed in a portion of the interlayer insulating film 4 covering the DRAM cell.
1, the bit line BL may be formed. When the polishing is advanced until the swelling of the upper portion of the hole 6 is eliminated, the hole 6 has a mesa-shaped cross-sectional shape as shown in FIG. The mesa-shaped cross section of the hole 6 has a narrower upper frontage than a hole having a bulge at the top as shown in FIG. However, since the cross section of the hole 6 has a mesa shape,
When the conductive film 7 is made of polycrystalline silicon containing an impurity element, amorphous silicon containing an impurity element, or the like as the conductive material, the coverage is improved by the presence of the tapered surface on the inner periphery of the hole 6.

Next, the DRAM cell shown in FIG. 3A will be briefly described. On the surface of the silicon substrate 1,
Field oxide film 2 has a structure surrounding two DRAM cell regions as one set. Field oxide film 2
Are surrounded by two gate electrodes 21g and 22g.
Are formed on the silicon substrate 1 via the gate insulating films 21a and 22a, respectively, and the impurity diffusion layers 23a and 23
b, 23c are formed. Also, two impurity diffusion layers 23 not sandwiched between the two gate electrodes 21g and 22g.
a and 23c are cylindrical storage electrodes 20a made of silicon.
Is formed, and the dielectric film 2 is formed on the surface of the storage electrode 20a.
0b and the counter electrode 20c are formed in this order, and the capacitor 20 is constituted by the storage electrode 20a, the dielectric film 20b, and the counter electrode 20c.

A bit line BL as shown in FIG. 3B is connected to the impurity diffusion layer 23b existing between the two gate electrodes 21g and 22g. A contact hole 21 for passing the bit line BL may be formed in accordance with the steps shown in FIGS. (Second Embodiment) In the first embodiment, a polishing method is employed as a method for thinning the interlayer insulating film 4. However, etching by a chemical reaction may be employed. Will be described.

First, as in the first embodiment, after forming a hole 6 in the interlayer insulating film 4, the resist is removed as shown in FIG. Next, the silicon substrate 1 is placed in the chamber 10 of the parallel plate type plasma etching apparatus shown in FIG.
Insert Then, a high-frequency power supply 12 having a frequency of 380 kHz and a power of 800 W is applied to the upper electrode 11 disposed in the chamber 10 and the pressure in the chamber 10 is reduced to 2
At 40 mTorr, the lower electrode 13 is grounded. Further, a mixed gas containing CHF ₃ , CF ₄ and O ₂ as an etching gas is introduced into the chamber 10 through the gas inlet 15.

The interlayer insulating film 4 made of BPSG is etched by a reaction with the fluorocarbon plasma generated under such etching conditions to make the interlayer insulating film 4 thin. In this case, the adjustment of the film thickness of the interlayer insulating film 4 is performed by controlling the time based on the etching rate per unit time which has been examined in advance. When the interlayer insulating film 4 is etched back in this manner, a hole 6 having a bulge at the top as shown in FIG. 6B or a mesa-shaped hole 6 as shown in FIG. 6C is formed. Is possible.

However, the difference from the first embodiment is that
The edge of the upper opening of the hole 6 is chamfered to generate a roundness R, and the coverage is further improved as compared with the hole 6 of the first embodiment. In addition, hall 6
The method of embedding the conductive material in the inside is the same as in the first embodiment, and a description thereof will be omitted.

As described above, when a plasma etching method is used when thinning the interlayer insulating film, the thinning of the interlayer insulating film in the DRAM cell region can be prevented by the resist mask. (Third Embodiment) In the first and second embodiments,
The thickness of the interlayer insulating film 4 containing the impurity element was adjusted by polishing or etching back over time. However, it is troublesome to check the polishing rate and the etching rate every time the setting of the polishing condition or the condition of the etch back is changed. Therefore, the following adjustment of the film thickness when thinning the interlayer insulating film 4 is performed. May be adopted.

First, the operation until the state shown in FIG. On the silicon substrate 1, a lower layer 4a of an interlayer insulating film 4 made of BPSG is grown to a thickness of 1.75 μm.
The growth conditions are the same as those for growing the BPSG of the first embodiment. Subsequently, using a reaction gas containing SiH ₄ and NH ₄ ,
₃ N ₄ is grown and used as an intermediate layer 4b.

Subsequently, the upper layer 4c of the BPSG interlayer insulating film 4 is formed. Thereafter, holes 6 are formed in the interlayer insulating film 4 according to the etching conditions described in the first embodiment, as shown in FIG. If the same reaction gas as that shown in the first embodiment is used for the etching, the intermediate layer 4b of Si ₃ N ₄ is also etched in the same manner,
In the interlayer insulating film 4 including the intermediate layer 4b, a boring hole 6 having a thick central portion is formed.

Thereafter, as shown in FIG.
The interlayer insulating film 4 is thinned by polishing by a method or plasma etching. When the polishing method is employed, if framed silica is used as the slurry, the selectivity of polishing the upper layer portion 4c of the PBSG to the intermediate layer 4a of Si ₃ N ₄ becomes 12 in the interlayer insulating film, and Polishing will stop at layer 4b.

On the other hand, when plasma etching is employed, a parallel plate etching apparatus shown in FIG. 4 is used.
Then, the pressure in the chamber 10 and 50 mTorr, a high-frequency power source 12 of power 2000W is applied at a frequency 27MHz to the upper electrode 11, a high frequency power supply 14 of the power 900W was applied at a frequency 800MHz to the lower electrode 13, further, C ₄
Selectively etching the upper portion 4c of the interlayer insulating layer 4 using a mixed gas having a F _8, CO and Ar. The etching selectivity of the PBSG upper layer portion 4c to the intermediate layer 4c made of Si ₃ N ₄ is 40.

The material constituting the intermediate layer 4b is Si ₃ N
_In addition to growing ₄ , polycrystalline silicon grown using a gas containing SiH ₄ or SiO ₂ grown using a reaction gas containing SiH ₄ and O ₂ may be used. However, BPS for SiO ₂
Since the selectivity of G is not so large, it is preferable to use Si ₃ N ₄ or silicon. When the etching is stopped by the intermediate layer 4b, unlike the second embodiment, the edge of the upper opening of the hole 6 is hardly rounded.

The cross-sectional shape of the hole 6 can be changed by lowering the formation position of the intermediate layer 4b.
That is, by arranging the intermediate layer 4b in the middle of the bulging portion of the hole 6 as shown in FIG. 7B, the upper part of the hole 6 can be formed into a cup (torch) shape shown in FIG. 7C. Further, by arranging the intermediate layer 4b below the bulging portion of the hole 6 as shown in FIG.
As shown in FIG. 8B, the cross-sectional shape of the hole 6 can be substantially mesa-shaped.

The material of the interlayer insulating film 4 containing impurities includes PSG and BSG in addition to BPSG. Further, the above-described interlayer insulating film may be disposed between the lower and upper wiring layers, and the hole formed in this interlayer insulating film is called a via. Incidentally, the fact that the holes in the interlayer insulating film have a bowing shape in the above three embodiments has been found by experiments. The inventors consider that such a pouring shape is generated for the following reason.

That is, as shown in FIG. 9, when ions in the plasma are irradiated toward the silicon substrate during the plasma etching, the more the angle of incidence of the ions with respect to the silicon substrate surface deviates from 90 degrees, the more the bowing becomes. The shape tends to occur, and the larger the deviation, that is, the smaller the irradiation angle, the larger the diameter of the thick part at the center of the hole. Further, the bowing shape changes due to the difference in the distribution of the irradiation angle.

When the amount of ions trapped in the resist increases, the number of ions incident perpendicularly to the substrate surface increases, while the ions irradiated in the oblique direction are caused by Coulomb repulsion by ions in the resist. Works to make it difficult to irradiate the interlayer insulating film. As a result, it is difficult for the central portion of the hole to have a large diameter. Further, the polymer constituting the resist may adhere to the side wall of the hole 6 of the interlayer insulating film 4, but if the amount of adhesion is large, the side wall becomes difficult to be etched, so that a bowing shape hardly occurs.

FIGS. 10 (a) and 10 (b) and FIGS. 11 (a) to 11 (c) show differences in hole shapes obtained by experiments.
In FIGS. 10A and 10B, a bowing shape occurs in the entire hole. This is presumed to be due to the wide distribution of the incident angle of the ions during the etching to the interlayer insulating film.

In FIGS. 11A to 11C, bowing occurs locally in the hole. This is because the distribution of the incident angle of the ions during the etching to the interlayer insulating film is narrow,
This is probably because the amount of ions incident at a specific angle increases. It is considered that the change in the incident angle of ions as described above depends on the degree of charge-up of the resist mask and the gas type.

In the experiment for obtaining the states shown in FIGS. 10 and 11, BPSG was used as an interlayer insulating film at 2.4 μm.
A sample formed to a thickness of m was used. In addition, 2
High-frequency power was supplied at 000 to 2500 W and 650 to 900 W to the lower electrode. Further, as an etching gas, CH
Or etched using F ₃ and Ar and O _2, or a C ₄ F ₈
Two-step etching was performed in which a first mixed gas of CO, Ar and O ₂ and a _second mixed gas of CHF ₃ , Ar and O ₂ were changed.

[0038]

As described above, according to the present invention, a hole in an interlayer insulating film is formed in a bowing shape, and the upper portion of the hole having a small diameter is removed by polishing or etching to form an opening above the hole. Since the width is widened, it is possible to form a hole for improving the coverage of the wiring even with a thick interlayer insulating film.

When plasma etching is used to remove the upper part of the interlayer insulating film, the periphery of the opening above the hole is rounded, so that the coverage is further improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view (part 1) illustrating a step of forming a hole in an interlayer insulating film according to a first embodiment of the present invention.

FIG. 2 is a sectional view (part 2) showing a step of forming a hole in the interlayer insulating film according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a DRAM cell covered with an interlayer insulating film used in the first embodiment of the present invention.

FIG. 4 is a configuration diagram illustrating an example of an etching apparatus used in a step of forming a hole in an interlayer insulating film according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a second different shape of a hole formed according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step of forming a hole in an interlayer insulating film according to a second embodiment of the present invention.

FIG. 7 is a sectional view illustrating a step of forming a hole in an interlayer insulating film according to a third embodiment of the present invention.

FIG. 8 is a cross-sectional view showing another example of the step of forming a hole in an interlayer insulating film according to the third embodiment of the present invention.

FIG. 9 is a sectional view of a hole for explaining a change in the shape of the hole formed by the present invention.

FIG. 10 is a cross-sectional view showing first and second examples of a difference in shape of a hole formed by the present invention.

FIG. 11 is a cross-sectional view showing third, fourth, and fifth examples of differences in the shape of a hole formed by the present invention.

FIG. 12 is a cross-sectional view showing an example of an interlayer insulating film covering a conventional DRAM cell.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate (semiconductor substrate) 2 field oxide film 3 impurity diffusion tail 4 interlayer insulating film 4a lower layer 4b intermediate layer 4c upper layer 5 resist 5a window 6 hole

Claims (7)

[Claims] A step of forming an impurity diffusion layer formed in a semiconductor layer or an interlayer insulating film covering a conductive pattern on the insulating film; and locally etching the interlayer insulating film.
A step of forming a swelling hole having a bowing shape in at least a part thereof; anda step of thinning the interlayer insulating film until the swelling part or the lower part of the hole by etching or polishing. Forming a conductive layer on the thinned interlayer insulating film and in the hole; and patterning the conductive layer to leave the hole in the hole and wire on the interlayer insulating film. Forming a pattern. 2. The method according to claim 1, wherein said first layer is made of silicon oxide containing an element which becomes an impurity of a semiconductor. 3. The method of growing an insulating film, comprising: growing a first layer for suppressing the etching or the polishing; and forming a first layer to be etched or polished on the first layer. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of growing on the semiconductor device. 4. The method according to claim 1, wherein the second layer is formed by growing silicon oxide containing an element serving as a semiconductor impurity.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the growth is any of silicon nitride, silicon oxide, and silicon. 5. The method according to claim 1, wherein said step of growing said interlayer insulating film includes a step of forming a third layer made of the same material as said second layer under said first layer. 4. The method for manufacturing a semiconductor device according to item 3. 6. The method of manufacturing a semiconductor device according to claim 1, wherein said etching for thinning said interlayer insulating film is etching using fluorocarbon plasma. 7. The method according to claim 1, wherein the polishing for thinning the interlayer insulating film is a chemical mechanical polishing.