JPH11202002A - Current detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current detection circuit which can operate even if a potential difference between a power source VDD and a power source VSS becomes small. SOLUTION: A MOS.FET2 controlling a load current I1 and a MOS.FET5 far current detection that mirrors a current flowing in the MOS.FET2 to a small current I2 at a constant ratio are provided. The current I2 flowing in the MOS.FET5 is mirrored as a current I3 by a MOS.FET4 and a MOS.FET7 connected to a VDD power source, and the load current I1 is detected as a reference potential of a VSS power source by a current detection resistor 8 connected to the VSS power source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a current detection circuit.

[0002]

2. Description of the Related Art Conventionally, various current detection circuits for detecting a current flowing through a load have been proposed. For example, a sense resistor is inserted in series with a load, and a current flowing through the load is detected by determining a potential difference between both ends of the resistor.

However, in such a current detection circuit that detects a current flowing through a load by inserting such a sense resistor, a loss corresponding to a voltage drop due to the sense resistor occurs, and the efficiency of driving the load is reduced. there were.

On the other hand, Japanese Unexamined Patent Publication No. Hei 7-113826 discloses a current detection circuit capable of detecting a load current without loss and with high accuracy without interposing a sense resistor on a load current path. ing. The following Japanese Patent Application Laid-Open
A conventional current detection circuit disclosed in JP-A-113826 will be described.

FIG. 5 is a circuit diagram of a conventional current detection circuit disclosed in Japanese Patent Application Laid-Open No. 7-113826.

[0006] The current detection circuit shown in FIG.
It detects a current flowing through the load 37 connected between the power supply VSS and the power supply VSS.

In FIG. 5, on the power supply VSS side of the load 37, a power MOSFET 38 for controlling a load current based on an instruction from the current control circuit 43 is connected in series with the load 37. . 42 is power M
This is a current sensing power MOSFET that mirrors a load current flowing through the OS FET 38 to a small current at a fixed ratio, and is connected to the power MOSFET 38 with a common gate.

A feedback circuit is formed by the operational amplifier 39 and the feedback circuit MOS-FET 41, and the power-MOS-FET 38 and the current sense power-MO
The terminal voltage (drain /
Source-to-source voltage) is fixed. That is, the non-inverting input terminal of the operational amplifier 39 is connected to the drain of the power MOSFET 38, the inverting input terminal is connected to the drain of the power MOSFET 42 for current sensing, and the output terminal is the gate of the MOSFET 41 for the feedback circuit. It is connected to the.

Also, a MOS-FE for a feedback circuit
On the power supply voltage VDD side of T41, the current mirror circuit FE
T40 is inserted, and FE for current mirror circuit
The current mirror circuit FET 44 for mirroring the load current flowing to T40 to a small current at a constant ratio is used for the current mirror circuit F44.
ET40 and common gate connection. The power supply voltage VSS of the current mirror circuit FET 44 is
The sense resistor 45 is interposed.

[0010]

In the conventional example described above, as shown in FIG. 5, a power supply VDD and a power supply VSS are used.
There is a portion that requires three elements, namely, the power sensing MOSFET 42 for current sensing, the MOSFET 41 for feedback circuit, and the FET 40 for current mirror circuit.

For this reason, when this current detection circuit operates, as shown in FIG.
The voltage V1 is applied between the source electrode and the drain electrode of T42.
Is generated, and a voltage V2 is generated between the source electrode and the drain electrode of the MOS-FET 41 for the feedback circuit, and a voltage V3 is generated between the source electrode and the drain electrode of the MOS-FET 40 for the current mirror circuit. I do. In this case, the potential difference between the power supply VDD and the power supply VSS required for the circuit operation is the sum of the voltage V1, the voltage V2, and the voltage V3.

Therefore, in such a conventional current detection circuit, the number of elements connected in series between the power supply VDD and the power supply VSS is large, and when the potential difference between the power supply VDD and the power supply VSS is reduced. There was a problem that it would not work.

The present invention has been made in view of the above points, and provides a current detection circuit that can operate even when the potential difference between the power supply VDD and the power supply VSS becomes small. With the goal.

[0014]

In order to achieve the above object, the present invention provides a current detecting circuit for detecting a load current flowing through a load, wherein a drain electrode is connected to the load and a source electrode is connected to a second electrode. A first FET connected to a power supply for controlling the load current, and a gate electrode connected to the first F
A second FET connected to a gate electrode of the ET, a source electrode connected to the second power supply, and mirroring a current flowing through the first FET at a predetermined ratio;
A third FET having a drain electrode connected to the drain electrode of the second FET, a gate electrode connected to the gate electrode of the third FET, and a source electrode connected to the first power supply. A non-inverting input terminal is connected to the drain electrode of the second FET, and a non-inverting input terminal is connected to the first FET to mirror the current flowing through the third FET at a predetermined ratio. An operational amplifier connected to the drain electrode of the FET and having an output terminal connected to the gate electrode of the third FET; and a current detector inserted between the drain electrode of the fourth FET and the second power supply. Means.

Further, according to the present invention, in a current detecting circuit for detecting a load current flowing through a load, a source electrode is connected to a first power supply, a drain electrode is connected to the load, and a first electrode for controlling the load current. And a second FET having a gate electrode connected to the gate electrode of the first FET, a source electrode connected to the first power supply, and mirroring a current flowing through the first FET at a predetermined ratio. And a drain electrode is connected to the drain electrode of the second FET;
A third FET having a source electrode connected to the second power supply;
A gate electrode connected to the gate electrode of the third FET; a source electrode connected to the second power supply;
A fourth FET that mirrors the current flowing through the FET at a predetermined ratio, a non-inverting input terminal connected to the drain electrode of the second FET, and an inverting input terminal connected to the drain electrode of the first FET. The output terminal is the third FET
And an operational amplifier connected to the gate electrode of the fourth F
Current detection means interposed between the drain electrode of the ET and the first power supply.

Further, one end of the load is connected to the first power supply,
The second power supply or the first power supply and the second power supply
And a third power supply, which is different from the power supply, and the other end is connected to a drain electrode of the first FET.

Further, one end of the load is connected to the first power source, the second power source or the third power source via a phase switching switch element, and the other end is connected to the first power source.
And the drain electrode of the FET.

The phase switching switch element is a fifth FET whose source electrode is connected to the first power supply, the second power supply, or the third power supply.
The gate electrode of the ET is connected to a phase switching signal, and the drain electrode of the fifth FET is connected to one end of the load.

Further, the first FET and the second FE
T, the third FET, the fourth FET, and the fifth FET are MOS-FETs.

Further, the current detecting means is a current detecting resistor.

Further, the potential of the second power supply is a ground potential.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

The current detection circuit according to the present invention includes a power supply VDD.
The element connected in series between the power supply VSS and the
By reducing the number of elements from two to two, and in this case, by adopting a circuit configuration that can achieve the same circuit operation as before, the number of elements is reduced compared to conventional current detection circuits, and operation is possible even at low voltages It became.

FIG. 1 is a circuit diagram of an embodiment of a current detection circuit according to the present invention.

The current detection circuit shown in FIG.
It detects a current flowing through the load 1 connected between the power supply VSS and the power supply VSS.

In FIG. 1, a load current I is supplied to the power supply VSS side of the load 1 based on an instruction from the current control circuit 6.
1 is connected in series to the load 1. Reference numeral 5 denotes an MO which mirrors the load current I1 flowing through the MOS-FET 2 to a small current at a constant ratio
This is an S-FET, and is connected to the MOS-FET 2 by a common gate.

That is, the drain terminal of the MOSFET 2 for controlling the load current I1 is connected to the load 1,
The source electrode is connected to the power supply VSS. MOS ・ FET
The gate electrode of the MOS-FET 5 that mirrors the current I1 flowing through 2 to a small current at a constant ratio is connected to the gate electrode of the MOS-FET 2 and the output of the current control circuit 6, and the source electrode is connected to the power supply VSS. Here, MOS F
The ET2 and the MOSFET 5 have the same element structure, and the size ratio is n: 1.

MOS FET constituting current mirror circuit
4 and the source electrode of the MOS FET 7 are connected to the power supply VDD, and the respective gate electrodes are connected to the output of the operational amplifier 3. Here, MOS • FET4 and MOS • F
It has the same element structure as ET7 and a size ratio of m to 1.
The drain electrode of the MOS-FET 4 is MOS-FE
Connected to the drain electrode of T5. Further, the non-inverting input of the operational amplifier 3 is connected to the drain electrode of the MOS-FET 5, and the inverting input is connected to the drain electrode of the MOS-FET 2. One end of the drain electrode of the MOSFET 7 is connected to a current detection resistor 8 connected to the power supply VSS.

Next, the operation of the current detection circuit shown in FIG. 1 will be described.

In this embodiment, in FIG. 1, a MOS-FET 2 for controlling a load current I1 and a MOS-F
A current detection MOS-FET 5 for mirroring a current flowing through the ET2 to a small current I2 at a constant ratio; and a current I2 flowing through the current detection MOS-FET 5 and a MOS-FET 4 connected to the VDD power supply side. The current I3 is mirrored by the FET 7 and the load current I1 is detected as a potential based on the VSS power supply by the current detection resistor 8 connected to the VSS power supply.

MOS-FET 4 and MOS-FET 7
Is connected to the output electrode of the operational amplifier 3, the non-inverting input of the operational amplifier 3 is connected to the drain electrode of the MOS-FET 5, and the inverting input of the operational amplifier 3 is connected to the MOS-F
By connecting to the drain electrode of ET2, MOS
The drain electrode of the FET2 and the drain electrode of the MOSFET5 have the same potential. Therefore, even when the MOS-FET 2 and the MOS-FET 5 operate in the linear region, the load current I1 is mirrored to the MOS-FET 5 with high accuracy as the small current I2.

More specifically, in the current detection circuit shown in FIG. 1, a MOS-FET through which a load current I1 flows is provided.
The operational amplifier 3 is connected to the MOSFET 4 so that the potentials of the respective drain electrodes of the current sensing MOSFET 5 which mirrors the load current I1 and its load current I1 on an n-to-one basis are equal.
Adjust the gate voltage of

Therefore, the MOS FET 2 and the MOS FET
Even when the FET 5 operates in the linear region, the load current adjusting MOS FET 2
The current mirrored by the FET 5 is the
The current I2, which is 1 / n of the load current I1, stably flows through the MOS FET 5 in a highly accurate manner determined by the size ratio n: 1 with the OS • FET5.

MOS FET constituting current mirror circuit
By operating the MOS FET 4 and the MOS FET 7 in the saturation region, the current I3 is determined with high accuracy at a size ratio of m: 1.
A current 1 / m of the load current I2, that is, a current I3 of 1 / (m × n) of the load current I1 flows stably through the OS • FET7. Therefore, the path through which the current I3 flows and the power supply VSS
The load current I3 can be detected based on the power supply VSS by interposing the current detection resistor 8 between the power supply VSS and the power supply VSS. If the current I3 can be detected, the load current I1 can be obtained from the above relationship.

FIG. 2 is a circuit diagram of a second embodiment of the current detection circuit according to the present invention.

The load 1 in FIG. 1 corresponds to the load 10 in FIG. 2, and the MOS • FET 2 in FIG.
1. The operational amplifier 3 in FIG. 1 corresponds to the operational amplifier 11 in FIG.
4 corresponds to the MOSFET 13 in FIG. 2, the MOSFET 5 in FIG. 1 corresponds to the MOSFET 12 in FIG. 2, the current control circuit 6 in FIG. 1 corresponds to the current control circuit 14 in FIG. 2 corresponds to the MOS.FET 16 in FIG. 2, and the current detection resistor 8 in FIG. 1 corresponds to the current detection resistor 16 in FIG.

That is, even with the circuit configuration shown in FIG. 2, the load current flowing through the load current 10 can be obtained by interposing the current detection resistor 16.

FIG. 3 is a circuit diagram of a third embodiment of the current detection circuit according to the present invention.

The load 1 in FIG. 1 corresponds to the load 18 in FIG. 3. The load 18 in FIG. 3 has a source electrode connected to the power supply VDD and a gate electrode connected to the phase switching circuit 20.
Connected to the drain electrode of S.FET17. The phase switching circuit 20 makes the MOS-FET 17 conductive if necessary, and supplies the VDD potential to one end of the load.

The MOS-FET 2 in FIG.
1 corresponds to the OS • FET 19, and corresponds to the operational amplifier 3 in FIG.
Corresponds to the operational amplifier 21 in FIG. 3, and the MOS in FIG.
FET 4 corresponds to the MOS FET 22 in FIG.
The MOS FET 5 in FIG.
The current control circuit 6 in FIG. 1 corresponds to the current control circuit 24 in FIG. 3, the MOSFET 7 in FIG. 1 corresponds to the MOSFET 25 in FIG. 3, and the current detection resistor 8 in FIG. Of the current detection resistor 26 of FIG.

That is, even in the case of the circuit configuration shown in FIG. 3, the load current flowing through the load current 18 can be obtained by interposing the current detection resistor 26.

FIG. 4 is a circuit diagram of a fourth embodiment of the current detection circuit according to the present invention.

The load 1 in FIG. 1 corresponds to the load 28 in FIG. 4. The load 28 in FIG. 4 has a source electrode connected to the power supply VSS and a gate electrode connected to the phase switching circuit 31.
Connected to the drain electrode of S • FET29. The phase switching circuit 28 makes the MOS-FET 29 conductive if necessary, and supplies the VSS potential to one end of the load.

The MOS FET 2 in FIG.
The OS · FET 27 corresponds to the operational amplifier 3 in FIG.
Corresponds to the operational amplifier 30 in FIG.
FET 4 corresponds to the MOS FET 33 in FIG.
The MOS.FET 5 in FIG.
The current control circuit 6 in FIG. 1 corresponds to the current control circuit 34 in FIG. 4, the MOSFET 7 in FIG. 1 corresponds to the MOSFET 36 in FIG. 4, and the current detection resistor 8 in FIG. Of the current detection resistor 35.

That is, even in the case of the circuit configuration shown in FIG. 4, the load current flowing through the load current 28 can be obtained by interposing the current detection resistor 35.

In each of the embodiments described above, the voltage applied to the load and the voltage applied to the mirror circuit are the same, but it goes without saying that the present invention is not limited to this.

[0047]

The first effect is that the feedback control M used in the conventional current detection circuit shown in FIG.
Since the OS • FET 41 becomes unnecessary, the number of elements can be reduced.

The second effect is that the feedback control M
By eliminating OS • FET41,
The voltage required between the source electrode and the drain electrode of the feedback control MOS-FET 41 during the operation is eliminated, and the minimum operating voltage (power supply VDD) is reduced by the voltage.
Potential difference between the power supply voltage VSS and the power supply voltage VSS) and the power supply voltage VDD
The operation of the circuit is guaranteed even when the potential difference between the power supply and the power supply VSS is low.

That is, in the conventional example, three elements are required between the power supply VDD and the power supply VSS, but according to the present invention, two elements are required between the power supply VDD and the power supply VSS.
It becomes an element, and it becomes possible to lower the minimum operating voltage.
Therefore, according to the present invention, current detection can be performed with high accuracy even in a device whose voltage has been reduced to suppress power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a current detection circuit according to the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the current detection circuit according to the present invention.

FIG. 3 is a circuit diagram of a current detection circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a fourth embodiment of the current detection circuit according to the present invention.

FIG. 5 is a circuit diagram of a conventional current detection circuit disclosed in JP-A-7-113826.

[Explanation of symbols]

1, 10, 18, 28, 37 loads 2, 4, 5, 7, 9, 12, 13, 16, 17, 19,
22, 23, 25, 27, 29, 32, 33, 36, 3
8, 40, 41, 42, 44 MOS-FETs 3, 11, 21, 30, 39 Operational amplifiers 6, 14, 24, 34, 43 Current control circuits 8, 15, 26, 35, 45 Current detection resistors 20, 31 phases Switching circuit

Claims (8)

[Claims] 1. A current detection circuit for detecting a load current flowing through a load, wherein a drain electrode is connected to the load, and a source electrode is connected to a second electrode.
A first FE connected to a power supply for controlling the load current
T; a gate electrode connected to the gate electrode of the first FET; a source electrode connected to the second power supply;
A second FET that mirrors a current flowing through the first FET at a predetermined ratio, and a third FE whose source electrode is connected to the first power supply and whose drain electrode is connected to the drain electrode of the second FET.
T, a gate electrode is connected to the gate electrode of the third FET, a source electrode is connected to the first power supply,
A fourth FET that mirrors the current flowing through the FET at a predetermined ratio, a non-inverting input terminal connected to the drain electrode of the second FET, and an inverting input terminal connected to the drain electrode of the first FET. And an operational amplifier having an output terminal connected to the gate electrode of the third FET, and current detection means interposed between the drain electrode of the fourth FET and the second power supply. Characteristic current detection circuit. 2. A current detection circuit for detecting a load current flowing through a load, wherein a source electrode is connected to a first power supply, a drain electrode is connected to the load, and a first FE controlling the load current.
T; a gate electrode connected to the gate electrode of the first FET; a source electrode connected to the first power supply;
A second FET that mirrors a current flowing through the first FET at a predetermined ratio, and a third FE whose drain electrode is connected to the drain electrode of the second FET and whose source electrode is connected to the second power supply.
T, a gate electrode is connected to the gate electrode of the third FET, a source electrode is connected to the second power supply,
A fourth FET that mirrors the current flowing through the FET at a predetermined ratio, a non-inverting input terminal connected to the drain electrode of the second FET, and an inverting input terminal connected to the drain electrode of the first FET. And an operational amplifier having an output terminal connected to the gate electrode of the third FET, and current detection means interposed between the drain electrode of the fourth FET and the first power supply. Characteristic current detection circuit. 3. One end of the load is connected to the first power source, the second power source, or a third power source different from the first power source and the second power source, and the other end is connected to the first power source.
3. The FET according to claim 1, which is connected to a drain electrode of the FET.
3. The current detection circuit according to claim 1. 4. One end of the load is connected to the first power supply, the second power supply or the third power supply via a phase switching switch element, and the other end is connected to the first F.
3. The current detection circuit according to claim 1, wherein the current detection circuit is connected to a drain electrode of the ET. 5. The phase switching switch element is a fifth FET having a source electrode connected to the first power supply, the second power supply, or the third power supply.
Is connected to a phase switching signal, and the fifth
5. The current detection circuit according to claim 4, wherein a drain electrode of the FET is connected to one end of the load. 6. The first FET, the second FET,
6. The current detection circuit according to claim 1, wherein the third FET, the fourth FET, and the fifth FET are MOS-FETs. 7. The current detection circuit according to claim 1, wherein said current detection means is a current detection resistor. 8. The current detection circuit according to claim 1, wherein the potential of said second power supply is a ground potential.