JPH11195681A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reinforce a connection terminal without using a reinforcing resin. A semiconductor device includes a chip and a substrate.
Are electrically and mechanically connected by a plurality of connection terminals 31 formed by CCB from the solder bumps, and between the connection terminals 31 in the gap between the chip 11 and the substrate 20. Reinforcing connection 32
Are arranged to mechanically connect the chip 11 and the substrate 20. [Effect] By mechanically connecting the chip and the substrate separately from the connection terminal by the reinforcing connection portion, the stress due to the difference in thermal expansion coefficient between the chip and the substrate can be dispersed to the reinforcing connection portion. The occurrence of metal fatigue can be prevented, and the connection terminals can be prevented from being damaged. By omitting the step of injecting the curing resin and the step of curing, a reduction in productivity can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, a semiconductor chip (hereinafter referred to as "chip") bonded to a wiring board (hereinafter simply referred to as "substrate") by flip chip connection. Regarding a semiconductor device, for example, a chip in which an integrated circuit is formed is mounted on a substrate by a controlled collapse boad.
nding. Hereinafter, it is called CCB. The present invention relates to a technique which is effective when applied to a semiconductor device which is mechanically and electrically connected by the above method.

[0002]

2. Description of the Related Art Flip chip connection is a technique in which a chip is connected with its active element surface facing a substrate. Usually, bumps (protruding electrodes, bumps) are formed on the chip by soldering or the like, and after the chip is turned upside down and aligned with a specified position on the substrate, the bumps are melted to form a collective connection terminal group. It is connected mechanically and electrically. Since the bumps can be arranged not only at the periphery of the chip but also at any position on the chip, it is possible to easily set the number of I / Os to 250 simply by forming a 15 × 15 matrix.

The reliability of connection terminals formed by bumps depends on the coefficient of thermal expansion (coefficie) between the chip and the substrate.
Since it is determined by the matching of nt of thermal expansion, the substrate material is silicon (Si, which is the same material as the chip), and the thermal expansion coefficient is 2.9 ppm /
C.), glass ceramic (SiO ₂ ), silicon carbide (SiC), and aluminum nitride (AlN) having a thermal expansion coefficient close to that of silicon. By the way,
As an expression to express the thermal fatigue of metal, Coffin-Ma
The nson equation is widely known. In the case of a combination that cannot ensure the thermal matching between the chip and the board,
A method of reinforcing with resin is used.

By the way, in mounting a computer, it is essential to reduce the area occupied by the package in order to minimize the mounting delay. Therefore, a package that is as compact as the chip size is required, and a package using flip-chip connection has been developed. Such packages include microcarriers (mic)
ro carrier for LSIChip. Hereinafter, it is called MCC. ). In other words, the MCC has a chip on the board that is flipped by CCB with solder bumps.
It is a package connected to a chip. In order to ensure thermal matching with a silicon chip, in MCC, mullite (SiO ₂ —Al ₂ O ₃ , coefficient of thermal expansion: 3) is applied to the substrate.
(1 ppm / ° C.) Ceramic is used.

Further, in this MCC, a thin space between the chip and the substrate is filled with a reinforcing resin so that
Japanese Patent Application Laid-Open No. 9-64090 discloses an example of a technique for extending the connection life of a connection terminal portion using CB solder bumps.

[0006] As an example in which MCC is described, "Practical Course VLSI Packaging Technology (2)" published by Nikkei BP Co., Ltd., published on May 31, 1993, pages P173 to P173.
178.

[0007]

However, in the technique of extending the connection life of the connection terminal portion by the CCB solder bump by filling the thin space between the chip and the substrate with the reinforcing resin, the resin injection step or the resin There is a problem that not only the number of curing (baking) steps increases but also that the resin injection step is difficult to perform.

An object of the present invention is to provide a semiconductor device capable of reinforcing connection terminals without using a reinforcing resin.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in a semiconductor device in which a semiconductor chip is arranged on one main surface of a substrate and mechanically and electrically connected by a plurality of connection terminals formed from bumps, the semiconductor chip and the substrate are connected to each other. A reinforcing connecting portion is provided between the semiconductor chip and the substrate mechanically separately from the connecting terminal.

According to the above-described means, since the connection terminal is reinforced by the reinforcing connection portion, even if a stress due to a difference in thermal expansion coefficient between the semiconductor chip and the substrate acts on the connection terminal, the connection terminal is mechanically connected. And the electrical connection is not impaired.

On the other hand, according to the above-described means, the step of injecting the reinforcing resin can be omitted, so that a decrease in productivity can be suppressed.

[0014]

FIG. 1 is a view showing a semiconductor device according to an embodiment of the present invention, and FIGS. 2 and subsequent drawings are explanatory views showing a manufacturing method thereof.

In the present embodiment, the package of the semiconductor device according to the present invention is configured in the MCC. That is, in the semiconductor device 30 shown in FIG. 1, a square silicon chip (hereinafter, referred to as a chip) 11 is a substrate 20.
A plurality of connection terminals 31 arranged on one main surface (hereinafter, referred to as an upper surface) and formed by CCB from solder bumps
Connected mechanically and electrically by
A group of connection terminals 31 is arranged in a matrix on the chip 11, and a reinforcing connection portion 32 is arranged between each connection terminal 31 in a gap between the chip 11 and the substrate 20, so that the chip 11 and the substrate 20 Are mechanically connected to each other.

This semiconductor device is manufactured by the following manufacturing method. Hereinafter, a method for manufacturing the semiconductor device according to one embodiment of the present invention will be described. With this explanation,
The details of the configuration of the above-described semiconductor device will be clarified together.

In this method of manufacturing a semiconductor device, a chip 11 shown in FIG. 2 is used. The chip 11 is formed in the shape of a square flat plate using silicon, and a large number of solders are provided around the active element side main surface (active area side main surface; hereinafter referred to as the lower surface) of the chip 11. A plurality of rows (three rows in the illustrated example) of annular solder bumps (hereinafter, referred to as bump rows) 13 configured by arranging the bumps 12 in a square outline shape are arranged at intervals in the radial direction with the chip 11. Each is formed concentrically. The solder bumps 12 are formed in a substantially hemispherical shape by using a solder material.
2 are arranged in a line at equal intervals in the circumferential direction.
The pitch of the adjacent solder bumps 12 and 12 and the pitch of the adjacent bump rows 13 and 13 are designed to be at least twice the diameter of the solder bumps 12 by design.
The gap between 2 and 12 is set to be larger than the diameter of the solder bump 12.

At each of the center points of the four solder bumps 12 arranged in a matrix on the lower surface of the chip 11, connection pads 14 for mechanically connecting the reinforcing connection 32 to the chip 11 are formed. Have been. The connection portion pads 14 are not provided with the solder bumps 12 and are not electrically connected to the integrated circuit of the chip 11.

The operation of manufacturing the chips, solder bumps, and connection portion pads is performed in the form of a wafer in a so-called pre-process in the manufacturing process of the semiconductor device. Hereinafter, the manufacturing process of the chip will be described mainly on the process of forming the solder bumps and the connection portion pads.

In a so-called pre-process in the manufacturing process of the semiconductor device, an integrated circuit (not shown) including a desired semiconductor element is formed on the wafer so as to correspond to the chip. Then, as shown in FIG. As described above, the electric wiring 16 is formed on the insulating film 15. The operation of forming the electric wiring 16 is performed by using aluminum and performing a thin film forming process such as sputtering or vapor deposition, a lithography process, and an etching process. A passivation film 17 is deposited on the electric wiring 16. Passivation film 1
Reference numeral 7 denotes a hard insulating film such as a silicon oxide film or a silicon nitride film. A large number of through holes are formed in the passivation film 17 at predetermined locations spaced from each other in a matrix form, and each of the through holes is opened. A predetermined electric wiring 16 is provided on the bottom of each opened through-hole.
Are exposed, and thus the electrode pad 18 is substantially constituted by the through hole. Opening of the through hole is selectively performed by lithography and etching.

Thereafter, in a solder bump forming step, a thin film forming process, a lithography process, an etching process, and the like are used, and the solder bumps 12 are applied to the respective electrode pads 18 of the chip 11 via the metallized layer 19. Each is formed so as to be electrically connected. For example, the metallization layer 19 includes a first underlayer made of chromium, a second underlayer made of nickel, and a third underlayer made of gold from the side of the electrode pad 18. The solder material of the solder bump 12 is Pb whose melting point is higher than the melting point of the solder material used for mounting the semiconductor device on the mounting board, for example, [320 to 325 ° C.].
It is formed using -2 wt% Sn.

When the solder bumps 12 are formed, the solder bumps 12 are not formed on the connection portion pads 14. For example, when the solder bump 12 is formed after the formation of the metallization layer 19 on the connection portion pad 14, the connection portion pad 14 is formed.
The formation of the solder bumps 12 is avoided by masking. Further, the electric wiring 16 on which the connection portion pads 14 are formed is formed in a non-energized state as shown in FIG.

As described above, the wafer on which the chips 11, the solder bumps 12, and the connection pads 14 are formed is divided into the respective chips 11 in the dicing process. The chip 11 after the dicing is applied to the substrate 2
It is formed in a minute flat plate shape corresponding to the chip mounting area of No. 0. For example, the chip 11 is formed in a 10 mm × 10 mm square flat plate shape.

On the other hand, FIG.
The substrate 20 shown in FIG. The base 20 is made of a base 2 made of alumina ceramic.
1, and the base 21 is formed in a rectangular flat plate shape sufficiently larger than the size of the chip 11. On one main surface (hereinafter, referred to as an upper surface) of the base 21, a number of substrate-side pads 22 are formed so as to correspond to the respective solder bumps 12 protruding from the chip 11. . That is, the group of the substrate-side pads 22 is arranged in the pad annular row 23 corresponding to the bump row 13. The surface of the substrate side pad 22 is subjected to a surface treatment so as to ensure the solder wettability with the solder bump 12 described above.

On the lower surface of the base 21, a number of external terminals 24 corresponding to the number of the substrate-side pads 22 are annularly arranged around the outer periphery of the base 21, and each external terminal 24 is electrically connected to each of the substrate-side pads 22. Are connected via the respective electric wirings 25 so as to be independent from each other. The external terminals 24 are mechanically and electrically connected to mounting bumps and pins for mounting the semiconductor device on a mounting board.

At each of the center points of the four substrate-side pads 22 arranged in a matrix on the upper surface of the base 21, a convex portion 26 formed in the shape of a flared square pyramid, which is an example of a pillar shape, protrudes. The solder layer 28 is formed on the metallized layer 27 formed on the upper surface of the projection 26. Since each board side pad 22 corresponds to each solder bump 12 of the chip 11, each solder layer 28 is arranged at a position corresponding to each connection portion pad 24 arranged at the center point of the four solder bumps 12. It is in the state that was done.

The projection 26 can be formed at the same time when the base 21 is manufactured. When the base 21 is made of ceramics as in the present embodiment, a protrusion 26 is formed on the base 21 by adding one or two layers of green sheets during lamination and sintering. You. By the way, when the base 21 is made of a glass epoxy resin, one or two layers of glass cloth are added at the time of lamination and thermocompression bonding to form the base 21.
A convex portion 26 is formed on the upper part of.

The chip 11 having the above structure is mechanically and electrically connected to the substrate 20 manufactured as described above by the CCB in the connection terminal forming step. That is, as shown in FIG. 4, in a face-down state in which each solder bump 12 of the chip 11 is aligned with each board-side pad 22 of the board 20, the chip 11
And temporarily bonded by flux or solder cream (not shown). When each solder bump 12 is aligned with each board-side pad 22, each solder layer 28 is aligned with each connection portion pad 14 of the chip 11, and is temporarily bonded with flux or solder cream (not shown). You. At this time, each solder bump 1
2 is guided by the so-called angle of attack by the inclined surface of the truncated pyramid of each convex portion 26, so that each substrate-side pad 22 is guided.
Is self-aligned.

Thereafter, an inert gas (for example, nitrogen gas)
By performing the reflow soldering process using an atmosphere heating furnace or the like, each solder bump 12 and each solder layer 28
Are each melted at temperatures up to 350 ° C.

By the reflow soldering process, the connection terminals 31 formed by the solder bumps 12 and the reinforcing connection portions 32 formed by the protrusions 26 and the solder layers 28 are formed collectively as shown in FIG. . That is, the solder bumps 12
Is formed by melting the metallized layer 19 of the chip 11 and the board-side pad 22 of the board 20. The solder layer portion 33 of the reinforcing connection portion 32 formed by melting the solder layer 28 is
The connection portion pad 14 and the metallized layer 27 of the projection 26 are soldered.

By the formation of the connection terminals 31 and the reinforcing connection portions 32 described above, the semiconductor device 3 shown in FIG.
0 has been manufactured. In the semiconductor device 30,
The chip 11 is in a state of being mechanically connected to the substrate 20 by the connection terminals 31 and the reinforcing connection portions 32. The integrated circuit of the chip 11 is electrically connected to the external terminals 24 of the substrate 20 via the electrode pads 18, the connection terminals 31, the substrate-side pads 22, and the electric wiring 25.

In this state, since the reinforcing connecting portion 32 is formed by the convex portion 26 and the solder layer portion 33,
The chip 11 is in a state of being lifted at a certain height from the upper surface of the substrate 20 by the group of reinforcing connection portions 32.
Therefore, between the opposing surfaces of the chip 11 and the substrate 20,
A thin space 34 having an area equal to that of the chip 11 and a height equal to the height of the reinforcing connection portion 32 and wide and having a low height from the floor surface to the ceiling surface is formed. Since the chip 11 is lifted at a certain height from the upper surface of the substrate 20 by the reinforcing connection portion 32 group, the connection terminal 31 is located at the center in the height direction where the mechanical characteristics and the electrical characteristics are good. This results in the formation of a substantially cylindrical shape with a bulging portion.

The semiconductor device 30 having the above-described structure manufactured as described above is used by being mounted on a motherboard such as a computer. When the semiconductor device 30 operates,
As the chip 11 repeats heat generation and cooling, stress due to a difference in thermal expansion coefficient between the chip 11 of the semiconductor device 30 and the substrate 20 repeatedly acts on the connection terminals 31 and the reinforcing connection portions 32.

By the way, in the case of a conventional semiconductor device in which no reinforcing connection portion is formed between the chip and the substrate and the chip and the substrate are mechanically connected only by the connection terminal group, Since the stress due to the difference in thermal expansion coefficient with the substrate acts on all the connection terminals, the connection terminals may be damaged due to metal fatigue.

However, the semiconductor device 30 according to the present embodiment
In this case, since the reinforcing connection portion 32 is formed between the chip 11 and the substrate 20 in addition to the connection terminal 31, stress due to a difference in thermal expansion coefficient between the chip 11 and the substrate 20 is reduced. Therefore, the occurrence of metal fatigue in the connection terminal 31 is prevented, and the connection terminal 31 is not damaged.

According to the above embodiment, the following effects can be obtained. By mechanically connecting the chip and the substrate separately from the connection terminals by the reinforcing connection portion, the stress due to the difference in thermal expansion coefficient between the chip and the substrate can be dispersed to the reinforcing connection portion. The occurrence of metal fatigue can be prevented, and the connection terminals can be prevented from being damaged.

By dispersing the stress due to the difference in the coefficient of thermal expansion between the chip and the substrate to the reinforcing connection portion, the step of injecting and curing the reinforcing resin can be omitted, thereby suppressing a reduction in productivity. Can be.

As described above, since the strictness of matching of the thermal expansion coefficient between the substrate and the material of the chip (silicon) can be relaxed, a relatively low-cost material such as alumina ceramic or glass-impregnated epoxy resin can be used. The manufacturing cost of the semiconductor device can be reduced.

FIGS. 5A and 5B show a method of manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. 5A is a perspective view before a connection terminal forming step, and FIG. It is a sectional view equivalent to a section.

The second embodiment is different from the first embodiment in that the projection 26A is formed in a rod shape that is long in one direction.
The point is that the solder bumps 12 are formed on the board-side pads 22 of the board 20.

In the second embodiment, the reinforcing connecting portions 3
Since 2A is formed long, the degree of reinforcement can be further increased.

FIGS. 6A and 6B show a method of manufacturing a semiconductor device according to a third embodiment of the present invention. FIG. 6A is a perspective view before a connection terminal forming step, and FIG. It is a sectional view equivalent to a section.

The third embodiment is different from the first embodiment in that the protrusions 26B are formed in a lattice shape, and the solder bumps 12 are formed on the substrate-side pads 22 of the substrate 20.

In the third embodiment, the reinforcing connection 3
Since 2B is formed in a lattice shape, the degree of reinforcement can be further increased. Since the convex portions 26B are formed in a lattice shape, the connection terminals 31 are surrounded and the cleaning of the flux becomes difficult. Therefore, a flux that does not require cleaning is used, or the cleaning liquid is distributed to the convex portions 26B. It is desirable to open a circulation hole for making this possible.

FIGS. 7A and 7B show a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. FIG. 7A is a partially omitted perspective view before a connection terminal forming step, and FIG.

The fourth embodiment is different from the first embodiment in that the reinforcing member 35 for forming the convex portion is used, the convex portion 26C is formed in a lattice shape, and the solder bump 12 Are formed on the substrate-side pads 22 of the substrate 20.

In the fourth embodiment, the first embodiment
In addition to the effect of the above, an effect is obtained that the reinforcing projections need not be formed on the chip 11 and the substrate 20.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, the reinforcing connection portion is not limited to being formed by the protrusions formed on the substrate and the solder layer portion, but may be formed by a solder layer portion, or may be formed by a solder ball, a copper ball, a gold ball, or the like. You may comprise.

In the first embodiment, the solder bumps may be provided on the substrate side.
In 4, the solder bumps may be provided on the chip side.

The bumps are not limited to being formed of a solder material, but may be formed of copper balls, gold balls, or the like.

The external terminals are not limited to the surface mounting structure such as a ball grid array, but may be the insertion mounting structure such as a pin grid array.

The base of the substrate is not limited to being formed of alumina ceramic, but may be formed of a ceramic substrate such as silicon carbide, mullite or aluminum nitride, or an insulating substrate such as a glass-impregnated epoxy resin substrate.

[0054]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

By mechanically connecting the chip and the substrate separately from the connection terminals by a reinforcing connection portion, stress due to a difference in thermal expansion coefficient between the chip and the substrate can be dispersed to the reinforcing connection portion. Metal fatigue can be prevented from occurring in the connection terminal, and damage to the connection terminal can be prevented.

By dispersing the stress caused by the difference in the thermal expansion coefficient between the chip and the substrate to the reinforcing connection portion, it is possible to omit the step of injecting and curing the reinforcing resin, thereby suppressing a decrease in productivity. Can be.

Since the strictness of matching of the coefficient of thermal expansion between the substrate and the material of the chip (silicon) can be relaxed, the substrate is made of a relatively low-cost material such as alumina ceramic or glass impregnated epoxy resin. Accordingly, the manufacturing cost of the semiconductor device can be reduced.

[Brief description of the drawings]

1A and 1B show a semiconductor device according to an embodiment of the present invention, wherein FIG. 1A is a partially cut front view, FIG. 1B is a partially cut plan view of the right half, and a bottom view of the left half. .

FIGS. 2A and 2B show a chip used in a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG.
(B) is an enlarged partial sectional view along the bb line of (a).

3A and 3B show a substrate used in a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 3A is a plan view of a right half, a bottom view of a left half, and FIG. (A) b-
It is an expanded fragmentary sectional view which follows a b line.

FIG. 4 is a partially cut-away enlarged front view showing a connection terminal forming step of the method for manufacturing a semiconductor device according to one embodiment of the present invention;

5A and 5B show a method of manufacturing a semiconductor device according to a second embodiment of the present invention, wherein FIG. 5A is a perspective view before a connection terminal forming step, and FIG. 5B is a sectional view taken along line bb of FIG. It is a corresponding sectional view.

6A and 6B show a method for manufacturing a semiconductor device according to a third embodiment of the present invention, wherein FIG. 6A is a perspective view before a connection terminal forming step, and FIG. It is a corresponding sectional view.

FIGS. 7A and 7B show a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention, in which FIG. 7A is a partially omitted perspective view before a connection terminal forming step, and FIG.

[Explanation of symbols]

11: chip (semiconductor chip), 12: solder bump, 1
3 bump line (solder bump ring line), 14 connection pad, 15 insulating film, 16 electric wiring, 17 passivation film, 18 electrode pad, 19 metallization layer,
Reference numeral 20: substrate, 21: base, 22: substrate side pad, 23
... Pad annular row, 24. External terminals, 25.
6 ... convex part, 27 ... metallization layer, 28 ... solder layer, 30 ...
Semiconductor device, 31 connection terminal, 32 connection portion for reinforcement, 3
3 ... Solder layer part, 34 ... Thin space, 35 ... Reinforcing member.

Claims (10)

[Claims] 1. A semiconductor device in which a semiconductor chip is arranged on one main surface of a substrate and is mechanically and electrically connected by a plurality of connection terminals formed from bumps. A semiconductor device, characterized in that a reinforcing connection portion is provided between the semiconductor chip and the substrate mechanically separately from the connection terminal. 2. The reinforcing connection part according to claim 1, wherein the reinforcing connection part is constituted by a protrusion projecting from the substrate and a solder layer formed on the protrusion. Semiconductor device. 3. The semiconductor device according to claim 2, wherein said projection is formed in a columnar shape. 4. The semiconductor device according to claim 2, wherein said projection is formed in a bar shape. 5. The semiconductor device according to claim 2, wherein said convex portions are formed in a lattice shape. 6. The semiconductor device according to claim 2, wherein said convex portion is formed in a tapered shape expanding toward the end. 7. The semiconductor device according to claim 1, wherein the bump is provided on the semiconductor chip side.
7. The semiconductor device according to 5 or 6. 8. The semiconductor device according to claim 1, wherein the bump is provided on the substrate side. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip and the substrate are mechanically connected in a state where the bumps and the substrate-side pads are aligned. A method for manufacturing a semiconductor device, wherein the connection terminal and the reinforcing connection portion are formed. 10. The method according to claim 9, wherein the connection terminal and the reinforcing connection portion are formed by reflow soldering.