JPH11187648A - Boosting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the optimum on-off control of a switching FET without providing a boosting circuit with a resistor for detecting a coil current for boosting. SOLUTION: A boosting circuit 1 is arranged so as to take out a high-voltage VH by turning on and off a current flowing from a DC power source E to the boosting circuit 1. In this case, this circuit is provided with a first circuit 50 which outputs an on-control signal S1 for keeping an FET 12 on until a charge voltage of a capacitor charged via a resistor by the DC power source E exceeds the level of a first voltage V1, and a second circuit 60 for resetting the charge condition of a capacitor 52 when a drain voltage VDR of the FET 12 falls under the level of a second voltage V2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit capable of operating a booster circuit efficiently without monitoring a current flowing through a booster coil of the booster circuit.

[0002]

2. Description of the Related Art A conventional booster circuit used in various electronic devices turns on and off a current flowing from a DC power supply to a coil by a field effect transistor (FET).
In general, a high-level voltage is obtained by storing a high-level surge voltage generated in a coil in a capacitor.

FIG. 6 shows a conventional booster circuit in which a high-level surge voltage generated in the booster coil 101 is stored in a capacitor 104 via a diode 103 by turning on and off the booster coil 101 by a switching FET 102. A configuration example is shown. In this conventional booster circuit, the FET drive circuit 106 is operated in response to a pulse signal from the oscillation circuit 105, and the switching FET 102 is turned on and off in a predetermined constant pattern, so that the circuit configuration is simple. Although it has an advantage, it has a problem that the boosting time is slow.

That is, the rate of decrease of the coil current flowing through the booster coil when the switching FET 102 is turned off depends on the magnitude of the surge voltage, and the surge voltage is higher than the high voltage VH obtained from the capacitor 104 at the diode 103. Since it becomes higher by the amount of the drop, the high voltage V
As H increases, the surge voltage also increases. As a result, the decreasing speed of the coil current increases as the high voltage VH increases.

For the above reasons, according to the booster circuit shown in FIG. 6, as shown in FIG.
.. During which the coil current does not flow becomes longer as the level of the high voltage VH rises, causing a problem that the efficiency of the circuit deteriorates.

In order to solve this problem, FIG. 8 shows a conventional example of a booster circuit in which the on / off switching of the FET is controlled so that the level of the current flowing through the coil becomes appropriate. In the conventional booster circuit shown in FIG. 8, for example, a power supply voltage VB is applied via a resistor 107 to a booster coil 101
And the switching FET 102 provided between the other end of the step-up coil 101 and the ground is turned on and off by the FET drive circuit 106, and the surge voltage generated by this is stored in the capacitor 104 via the diode 103. Then, in a circuit in which a desired high voltage VH is obtained from the output terminal 100, the level of the current flowing through the resistor 107 is constantly monitored by the current value monitoring circuit 108, and the level of the current flowing through the resistor 107 is not less than a predetermined value. The switching FET 102 is turned off when the current is flowing, and the switching FET 102 is turned on when the current level flowing through the resistor 107 falls below a predetermined value.
This is a configuration for controlling the drive circuit 106. According to this configuration, there is no fear of overcurrent and the switching FET 10
2 can be avoided.

For this reason, for example, in a booster circuit used to apply a voltage higher than the power supply voltage at the initial stage of driving the injector for high-speed operation of the injector used in the in-cylinder gasoline injection system, one booster circuit is used. When the load on the boosting circuit is increased, as in the case where the cost is reduced by supplying a large number of injectors with the high voltage output of the above, the boosting circuit shown in FIG. 8 is extremely convenient.

[0008]

However, the booster coil 1
According to the configuration in which the resistor 107 is connected in series with the resistor 01, another problem arises in that power loss occurs in the resistor 107, thereby lowering the efficiency of the entire circuit and increasing the circuit scale.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a booster circuit in which optimum on / off control of a switching FET is performed without providing a resistor for detecting a current flowing through a booster coil. is there.

[0010]

A feature of the present invention to solve the above-mentioned problem is that a booster coil having one end connected to a DC power supply and a drain-source circuit connected between the other end of the booster coil and ground. And a field-effect transistor for controlling on / off of a current flowing through the booster coil, and configured to take out a high-voltage generated in the booster coil. A first circuit that includes a capacitor that is charged through the first circuit and outputs an ON control signal for keeping the field effect transistor on until the charged voltage of the capacitor exceeds a predetermined first level; and a drain of the field effect transistor. A second circuit for resetting a state of charge of the capacitor when the drain voltage falls below a predetermined second level in response to a voltage; Lies in the fact provided.

For example, when the power supply is turned on, the charging voltage of the capacitor starts to rise from 0 V, and until the voltage exceeds the first level, the field effect transistor is turned on by the on control signal, and a current flows through the booster coil. After a lapse of time according to a time constant determined by the capacitance of the capacitor and the value of the resistor, the field effect transistor is turned off by the on control signal.

When the field effect transistor is turned off, its drain voltage tends to decrease. At this time, the drain voltage once rises and then falls sharply due to the back electromotive force generated in the boosting coil. The high voltage energy generated by this rapid rise in drain voltage is stored in another capacitor. When the level becomes lower than the second level due to the drop of the drain voltage, the charge state of the capacitor is reset by the second circuit. As a result, the field effect transistor is turned on again, and the capacitor is charged again via the resistor. Thereafter, the field effect transistor is repeatedly turned on and off in this manner.

That is, the field effect transistor is turned on by the first and second circuits until the charged voltage of the capacitor exceeds the first level after the state of charge of the capacitor is reset, while the charged voltage of the capacitor is reduced to the first level. The field effect transistor is turned off until the drain voltage becomes lower than the second level after exceeding the level.
As a result, in particular, the off time of the field effect transistor is always controlled to an optimum state, and the booster circuit can be operated extremely efficiently.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an example of an embodiment of a booster circuit according to the present invention. The booster circuit 1 boosts the DC voltage VB applied from the DC power supply E to the power supply terminal 2 and outputs a DC high voltage of, for example, about several tens of volts to the output terminal 3.
And a booster 10.

The step-up unit 10 is composed of a step-up coil 11 and a switching field-effect transistor (FET) 12 connected as shown in the figure. The FET 12 is turned on and off to flow from the DC power source E to the step-up coil 11. The current is interrupted, and the high voltage generated in the step-up coil 11 by the high voltage storage capacitor 14
This is a known circuit configuration that is stored in a memory. here,
Reference numeral 15 denotes a diode for enabling the high-voltage storage capacitor 14 to be charged with the DC voltage VB. 16,
17 is a transistor, 18 and 19 are resistors, and these constitute a gate drive circuit 20 of the FET 12.

In FIG. 1, reference numeral 30 denotes a boosted voltage monitor circuit for monitoring the level of the high voltage stored in the high voltage storage capacitor 14.

As shown in detail in FIG. 2, the boosted voltage monitor circuit 30 divides the high voltage VH charged in the high voltage storage capacitor 14 by resistors 31 and 32, and divides the divided voltage VD by 5V. The stabilized voltage VS of about
The level is compared by a voltage comparator 35 with a reference voltage VR divided at 34. 36 is a pull-up resistor, and 37 is a smoothing capacitor.

According to this configuration, it is possible to determine whether the high voltage VH has reached a desired level by appropriately setting the value of the reference voltage VR. Voltage comparator 3
5, a monitor output MN indicating the result of the determination is extracted and input to the control circuit 40.

Returning to FIG. 1, the control circuit 40 operates the booster 1
0 is a circuit for controlling the ON time and the OFF time of the FET 12 in order to operate the FET 12 efficiently, a first circuit 50 that outputs an ON control signal S1 for determining the ON operation time of the FET 12, And a second circuit 60 for resetting the operation of the first circuit 50 to determine the operation time.

Referring to FIG. 3, the first circuit 50 has a capacitor 52 charged by a DC voltage VB via a resistor 51. Charge voltage VC of capacitor 52
Is compared by a voltage comparator 55 with a first voltage V1 obtained by dividing the stabilized voltage VS by resistors 53 and 54, and an output of the voltage comparator 55 is output as an ON control signal S1.
The voltage is applied to each base of the transistors 16 and 17 of the booster 10. Here, 56 is a pull-up resistor.

When VC ≦ V1, the output of the voltage comparator 55 is at a high level.
Is turned on. On the other hand, when VC> V1, the resistor 5
The output of No. 3 becomes low level, and the FET 12 is turned off.

Referring to FIG. 4, a second circuit 60 includes a second voltage V formed by dividing a DC voltage VB by resistors 61 and 62.
2 and a voltage comparator 63 for comparing the level of the drain voltage VDR of the FET 12 (see FIG. 1). The drain voltage VDR is connected to a resistor 65 via a diode 64,
The divided drain voltage DVDR divided by the voltage dividing circuit is applied to the + input terminal of the voltage comparator 63. Voltage comparator 6
3, a monitor output MN is applied via a diode 67 to the + input terminal, and an ON control signal S1
Is a timer circuit 7 including a resistor 71 and a capacitor 72.
0 and a diode 68.

Next, the operation of the booster circuit 1 shown in FIGS. 1 to 4 will be described with reference to FIG. 5A is a waveform diagram of the charging voltage VC, and FIG.
FIG. 4C is a diagram showing the ON / OFF state of T12, and FIG. 4C is a waveform diagram of the drain voltage VDR, and FIG. (D) is a current waveform diagram of the FET 12,
(E) is a waveform diagram of the charging current IC of the high-voltage storage capacitor 14, and (F) is a voltage waveform diagram of the + input terminal of the voltage comparator 63.

Considering the case where the power supply voltage is applied at timing T = T1, VC <V at T = T1.
Since it is 1, the ON control signal S1, which is the output of the voltage comparator 55, goes high, and the gate drive circuit 20 turns on the FET 12 in response to this. As a result, a current flows from the DC power supply E into the booster coil 11. The ON control signal S1 is supplied to the +
It is applied to the input terminal with a time delay. The level of the second voltage V2 is a reference voltage used to determine whether or not the value of the drain voltage VDR does not contribute to charging of the high-voltage storage capacitor 14.

When the FET 12 is turned on, the drain voltage V
Although the level of DR becomes substantially zero, the ON control signal S1 is applied to the + input terminal of the voltage comparator 63 via the timer circuit, so that the output of the voltage comparator 63 is open and the capacitor 52 is connected to the voltage comparator. There is no resetting by the reset signal S2 which is the ground signal output from 63.

As the time elapses, the level of the charging voltage VC gradually increases, and when VC = V1 at T = T2, the output of the voltage comparator 55 goes low, and the FET 12 is turned off.

Although the potential of the + input terminal of the voltage comparator 63 tends to decrease as a result, the level of the drain voltage VDR increases due to the back electromotive force generated in the booster coil 11 when the FET 12 is turned off ( FIG. 5 (C)). Therefore, at this point, the voltage comparator 6
The potential of the positive input terminal 3 is at a level corresponding to the surge voltage of the booster coil 11.

The high-voltage accumulating capacitor 14 is charged by the surge voltage generated in the booster coil 11, and the high-voltage storage capacitor 14 is charged.
Is obtained. High voltage storage capacitor 1 due to surge voltage
When the charging to No. 4 is completed, the surge voltage, that is, the level of the drain voltage VDR sharply decreases. As a result, the level of the divided drain voltage DVDR becomes lower than the level of the second voltage V2. At the timing of T = T3, the output of the voltage comparator 63 enters the low impedance state, and the reset signal S2 output reflecting this state removes the charge of the capacitor 52, and the value of the charge voltage VC becomes substantially zero.

As a result, the first circuit 50 is in the same circuit state as when T = T1, and the FET 12 is turned on again. Therefore, also in the second circuit 60, the output of the voltage comparator 63 becomes open as in the case of T = T1, the charging current flows from the DC power supply E into the capacitor 52, and the level of the charging voltage VC becomes a predetermined time constant. Ascend gradually.

As described above, the FET 12 is repeatedly turned on and off, and the high-voltage storage capacitor 14 is charged with the high-voltage. As can be seen from the above description, the second circuit 60
Monitors the level of the drain voltage VDR, resets the first circuit 50 by outputting a reset signal at the timing when the level of the drain voltage VDR decreases and the charging of the high-voltage storage capacitor 14 is substantially stopped. , FE
T12 can be immediately returned to the on state. As a result, the FET for charging the high-voltage storage capacitor 14
The on and off operations of the step 12 are performed extremely appropriately, and the step-up operation in the step-up unit 10 is efficiently performed.

In the illustrated embodiment, the monitor output MN is applied to the + input terminal of the voltage comparator 63,
When a high voltage of a sufficient level is stored in the high voltage storage capacitor 14, the voltage comparator 63 is output from the monitor output MN.
Is locked to a high level to keep the FET 12 in the off state.

According to the booster circuit 1, the optimum on / off operation of the FET 12 can be easily realized with a simple structure of monitoring the drain voltage of the FET 12. In this configuration, there is no need to connect a shunt resistor for monitoring the current value in series with the boosting coil unlike the conventional circuit, so that there is no wasteful power consumption in the boosting circuit and high efficiency.

As described above, since the FET 12 appropriately turns on and off, the time required for boosting is reduced,
Even when the load is large, high-pressure energy required for the load can be supplied with good responsiveness. Also, FET12
Since the unnecessary off time is not generated, there is also an advantage that the influence of noise due to the resonance phenomenon after the end of the surge, which is likely to occur when the FET 12 is turned off, can be effectively avoided.

[0035]

According to the present invention, the optimum on / off operation of the field effect transistor can be easily performed with a simple structure of monitoring the drain voltage of the field effect transistor for controlling on / off of the current flowing through the booster coil. Can be realized. As a result, there is no need to provide a shunt resistor for monitoring the value of the current flowing through the booster coil as in the conventional circuit, so that the booster circuit can be operated with high efficiency without wasteful power consumption. Can be.

Furthermore, since the field-effect transistor can be appropriately turned on and off as described above, the time required for boosting is shortened, and even when the load is large, the high-pressure energy required for the load is responsive. Can be supplied. Further, since no unnecessary off time of the field effect transistor is generated, the influence of noise due to the resonance phenomenon after the end of the surge, which is likely to occur when the field effect transistor is turned off, can be effectively avoided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of an embodiment of a booster circuit according to the present invention.

FIG. 2 is a detailed circuit diagram of the boosted voltage monitor circuit of FIG.

FIG. 3 is a detailed circuit diagram of a first circuit in FIG. 1;

FIG. 4 is a detailed circuit diagram of a second circuit in FIG. 1;

FIG. 5 is a waveform chart of each part for explaining the operation of the booster circuit shown in FIG. 1;

FIG. 6 is a circuit diagram showing a conventional booster circuit.

FIG. 7 is a waveform chart of each part for explaining the operation of the conventional booster circuit shown in FIG.

FIG. 8 is a circuit diagram showing another conventional booster circuit.

[Description of Signs] 1 Step-up circuit 2 Power supply terminal 10 Step-up unit 11 Step-up coil 12 FET 14 High-voltage storage capacitor 40 Control circuit 50 First circuit 60 Second circuit E DC power supply S1 ON control signal S2 Reset signal V1 First voltage V2 Second voltage VB DC voltage VC Charging voltage VDR Drain voltage VH High voltage

Claims (1)

[Claims] 1. A booster coil having one end connected to a DC power supply, and a drain-source circuit connected between the other end of the booster coil and ground for controlling on / off of a current flowing through the booster coil. A booster circuit configured to extract a high-voltage generated in the booster coil, the capacitor comprising a capacitor charged by the DC power supply via a resistor, wherein a charging voltage of the capacitor is a predetermined voltage. A first circuit that outputs an on-control signal for keeping the field-effect transistor on until the level exceeds one level; and the drain voltage falls below a predetermined second level in response to a drain voltage of the field-effect transistor. And a second circuit for resetting the state of charge of the capacitor in a case.